1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
5 # for checking defines we need to use the correct compiler flags
6 march_opt = '-march=@0@'.format(machine)
8 arm_force_native_march = false
9 arm_force_default_march = (machine == 'default')
11 flags_common_default = [
12 # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
13 # to determine the best threshold in code. Refer to notes in source file
14 # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
15 ['RTE_ARCH_ARM64_MEMCPY', false],
16 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
17 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
18 # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
20 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
21 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
22 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
24 ['RTE_LIBRTE_FM10K_PMD', false],
25 ['RTE_LIBRTE_SFC_EFX_PMD', false],
26 ['RTE_LIBRTE_AVP_PMD', false],
28 ['RTE_SCHED_VECTOR', false],
29 ['RTE_ARM_USE_WFE', false],
33 ['RTE_MACHINE', '"armv8a"'],
34 ['RTE_MAX_LCORE', 256],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_CACHE_LINE_SIZE', 128]]
38 ['RTE_MACHINE', '"armv8a"'],
39 ['RTE_MAX_LCORE', 16],
40 ['RTE_USE_C11_MEM_MODEL', true],
41 ['RTE_CACHE_LINE_SIZE', 64]]
43 ['RTE_CACHE_LINE_SIZE', 128],
44 ['RTE_MAX_NUMA_NODES', 2],
45 ['RTE_MAX_LCORE', 96],
46 ['RTE_MAX_VFIO_GROUPS', 128]]
48 ['RTE_MACHINE', '"dpaa"'],
49 ['RTE_USE_C11_MEM_MODEL', true],
50 ['RTE_CACHE_LINE_SIZE', 64],
51 ['RTE_MAX_NUMA_NODES', 1],
52 ['RTE_MAX_LCORE', 16],
53 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
55 ['RTE_MACHINE', '"emag"'],
56 ['RTE_CACHE_LINE_SIZE', 64],
57 ['RTE_MAX_NUMA_NODES', 1],
58 ['RTE_MAX_LCORE', 32]]
60 ['RTE_MACHINE', '"armv8a"'],
61 ['RTE_CACHE_LINE_SIZE', 64],
62 ['RTE_MAX_NUMA_NODES', 1],
63 ['RTE_MAX_LCORE', 16]]
65 flags_default_extra = []
67 ['RTE_MACHINE', '"n1sdp"'],
68 ['RTE_MAX_NUMA_NODES', 1],
70 ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
71 ['RTE_LIBRTE_VHOST_NUMA', false]]
72 flags_thunderx_extra = [
73 ['RTE_MACHINE', '"thunderx"'],
74 ['RTE_USE_C11_MEM_MODEL', false]]
75 flags_thunderx2_extra = [
76 ['RTE_MACHINE', '"thunderx2"'],
77 ['RTE_CACHE_LINE_SIZE', 64],
78 ['RTE_MAX_NUMA_NODES', 2],
79 ['RTE_MAX_LCORE', 256],
80 ['RTE_ARM_FEATURE_ATOMICS', true],
81 ['RTE_USE_C11_MEM_MODEL', true]]
82 flags_octeontx2_extra = [
83 ['RTE_MACHINE', '"octeontx2"'],
84 ['RTE_MAX_NUMA_NODES', 1],
85 ['RTE_MAX_LCORE', 36],
86 ['RTE_ARM_FEATURE_ATOMICS', true],
87 ['RTE_EAL_IGB_UIO', false],
88 ['RTE_USE_C11_MEM_MODEL', true]]
90 machine_args_generic = [
91 ['default', ['-march=armv8-a+crc']],
92 ['native', ['-march=native']],
93 ['0xd03', ['-mcpu=cortex-a53']],
94 ['0xd04', ['-mcpu=cortex-a35']],
95 ['0xd07', ['-mcpu=cortex-a57']],
96 ['0xd08', ['-mcpu=cortex-a72']],
97 ['0xd09', ['-mcpu=cortex-a73']],
98 ['0xd0a', ['-mcpu=cortex-a75']],
99 ['0xd0b', ['-mcpu=cortex-a76']],
100 ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
102 machine_args_cavium = [
103 ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
104 ['native', ['-march=native']],
105 ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
106 ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
107 ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
108 ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_thunderx2_extra],
109 ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_octeontx2_extra]]
111 machine_args_emag = [
112 ['default', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
113 ['native', ['-march=native']]]
115 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
116 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
117 impl_0x41 = ['Arm', flags_arm, machine_args_generic]
118 impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
119 impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
120 impl_0x44 = ['DEC', flags_generic, machine_args_generic]
121 impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
122 impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
123 impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
124 impl_0x50 = ['Ampere Computing', flags_emag, machine_args_emag]
125 impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
126 impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
127 impl_0x56 = ['Marvell ARMADA', flags_armada, machine_args_generic]
128 impl_0x69 = ['Intel', flags_generic, machine_args_generic]
129 impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
131 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
133 if not dpdk_conf.get('RTE_ARCH_64')
134 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
135 dpdk_conf.set('RTE_ARCH_ARM', 1)
136 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
137 # the minimum architecture supported, armv7-a, needs the following,
138 # mk/machine/armv7a/rte.vars.mk sets it too
139 machine_args += '-mfpu=neon'
141 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
142 dpdk_conf.set('RTE_ARCH_ARM64', 1)
145 cmd_generic = ['generic', '', '', 'default', '']
146 cmd_output = cmd_generic # Set generic by default
147 machine_args = [] # Clear previous machine args
148 if arm_force_default_march and not meson.is_cross_build()
149 machine = impl_generic
151 elif not meson.is_cross_build()
152 # The script returns ['Implementer', 'Variant', 'Architecture',
153 # 'Primary Part number', 'Revision']
154 detect_vendor = find_program(join_paths(
155 meson.current_source_dir(), 'armv8_machine.py'))
156 cmd = run_command(detect_vendor.path())
157 if cmd.returncode() == 0
158 cmd_output = cmd.stdout().to_lower().strip().split(' ')
160 # Set to generic if variable is not found
161 machine = get_variable('impl_' + cmd_output[0], ['generic'])
162 if machine[0] == 'generic'
163 machine = impl_generic
164 cmd_output = cmd_generic
166 impl_pn = cmd_output[3]
167 if arm_force_native_march == true
171 impl_id = meson.get_cross_property('implementor_id', 'generic')
172 impl_pn = meson.get_cross_property('implementor_pn', 'default')
173 machine = get_variable('impl_' + impl_id)
176 # Apply Common Defaults. These settings may be overwritten by machine
178 foreach flag: flags_common_default
180 dpdk_conf.set(flag[0], flag[1])
184 message('Implementer : ' + machine[0])
185 foreach flag: machine[1]
187 dpdk_conf.set(flag[0], flag[1])
191 foreach marg: machine[2]
192 if marg[0] == impl_pn
193 foreach flag: marg[1]
194 if cc.has_argument(flag)
198 # Apply any extra machine specific flags.
199 foreach flag: marg.get(2, flags_default_extra)
201 dpdk_conf.set(flag[0], flag[1])
207 message(machine_args)
209 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
210 cc.get_define('__aarch64__', args: machine_args) != '')
211 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
214 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
215 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
218 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
219 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
220 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']