1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
5 # for checking defines we need to use the correct compiler flags
6 march_opt = '-march=@0@'.format(machine)
8 arm_force_native_march = false
9 arm_force_default_march = (machine == 'default')
11 flags_common_default = [
12 # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
13 # to determine the best threshold in code. Refer to notes in source file
14 # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
15 ['RTE_ARCH_ARM64_MEMCPY', false],
16 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
17 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
18 # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
20 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
21 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
22 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
24 ['RTE_LIBRTE_FM10K_PMD', false],
25 ['RTE_LIBRTE_SFC_EFX_PMD', false],
26 ['RTE_LIBRTE_AVP_PMD', false],
28 ['RTE_SCHED_VECTOR', false],
32 ['RTE_MACHINE', '"armv8a"'],
33 ['RTE_MAX_LCORE', 256],
34 ['RTE_USE_C11_MEM_MODEL', true],
35 ['RTE_CACHE_LINE_SIZE', 128]]
37 ['RTE_MACHINE', '"armv8a"'],
38 ['RTE_MAX_LCORE', 16],
39 ['RTE_USE_C11_MEM_MODEL', true],
40 ['RTE_CACHE_LINE_SIZE', 64]]
42 ['RTE_CACHE_LINE_SIZE', 128],
43 ['RTE_MAX_NUMA_NODES', 2],
44 ['RTE_MAX_LCORE', 96],
45 ['RTE_MAX_VFIO_GROUPS', 128]]
47 ['RTE_MACHINE', '"dpaa"'],
48 ['RTE_USE_C11_MEM_MODEL', true],
49 ['RTE_CACHE_LINE_SIZE', 64],
50 ['RTE_MAX_NUMA_NODES', 1],
51 ['RTE_MAX_LCORE', 16],
52 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
54 ['RTE_MACHINE', '"emag"'],
55 ['RTE_CACHE_LINE_SIZE', 64],
56 ['RTE_MAX_NUMA_NODES', 1],
57 ['RTE_MAX_LCORE', 32]]
59 ['RTE_MACHINE', '"armv8a"'],
60 ['RTE_CACHE_LINE_SIZE', 64],
61 ['RTE_MAX_NUMA_NODES', 1],
62 ['RTE_MAX_LCORE', 16]]
64 flags_default_extra = []
66 ['RTE_MACHINE', '"n1sdp"'],
67 ['RTE_MAX_NUMA_NODES', 1],
69 ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
70 ['RTE_LIBRTE_VHOST_NUMA', false]]
71 flags_thunderx_extra = [
72 ['RTE_MACHINE', '"thunderx"'],
73 ['RTE_USE_C11_MEM_MODEL', false]]
74 flags_thunderx2_extra = [
75 ['RTE_MACHINE', '"thunderx2"'],
76 ['RTE_CACHE_LINE_SIZE', 64],
77 ['RTE_MAX_NUMA_NODES', 2],
78 ['RTE_MAX_LCORE', 256],
79 ['RTE_ARM_FEATURE_ATOMICS', true],
80 ['RTE_USE_C11_MEM_MODEL', true]]
81 flags_octeontx2_extra = [
82 ['RTE_MACHINE', '"octeontx2"'],
83 ['RTE_MAX_NUMA_NODES', 1],
84 ['RTE_MAX_LCORE', 24],
85 ['RTE_ARM_FEATURE_ATOMICS', true],
86 ['RTE_EAL_IGB_UIO', false],
87 ['RTE_USE_C11_MEM_MODEL', true]]
89 machine_args_generic = [
90 ['default', ['-march=armv8-a+crc']],
91 ['native', ['-march=native']],
92 ['0xd03', ['-mcpu=cortex-a53']],
93 ['0xd04', ['-mcpu=cortex-a35']],
94 ['0xd07', ['-mcpu=cortex-a57']],
95 ['0xd08', ['-mcpu=cortex-a72']],
96 ['0xd09', ['-mcpu=cortex-a73']],
97 ['0xd0a', ['-mcpu=cortex-a75']],
98 ['0xd0b', ['-mcpu=cortex-a76']],
99 ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
101 machine_args_cavium = [
102 ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
103 ['native', ['-march=native']],
104 ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
105 ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
106 ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
107 ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_thunderx2_extra],
108 ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_octeontx2_extra]]
110 machine_args_emag = [
111 ['default', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
112 ['native', ['-march=native']]]
114 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
115 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
116 impl_0x41 = ['Arm', flags_arm, machine_args_generic]
117 impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
118 impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
119 impl_0x44 = ['DEC', flags_generic, machine_args_generic]
120 impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
121 impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
122 impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
123 impl_0x50 = ['Ampere Computing', flags_emag, machine_args_emag]
124 impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
125 impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
126 impl_0x56 = ['Marvell ARMADA', flags_armada, machine_args_generic]
127 impl_0x69 = ['Intel', flags_generic, machine_args_generic]
128 impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
130 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
132 if not dpdk_conf.get('RTE_ARCH_64')
133 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
134 dpdk_conf.set('RTE_ARCH_ARM', 1)
135 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
136 # the minimum architecture supported, armv7-a, needs the following,
137 # mk/machine/armv7a/rte.vars.mk sets it too
138 machine_args += '-mfpu=neon'
140 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
141 dpdk_conf.set('RTE_ARCH_ARM64', 1)
144 cmd_generic = ['generic', '', '', 'default', '']
145 cmd_output = cmd_generic # Set generic by default
146 machine_args = [] # Clear previous machine args
147 if arm_force_default_march and not meson.is_cross_build()
148 machine = impl_generic
150 elif not meson.is_cross_build()
151 # The script returns ['Implementer', 'Variant', 'Architecture',
152 # 'Primary Part number', 'Revision']
153 detect_vendor = find_program(join_paths(
154 meson.current_source_dir(), 'armv8_machine.py'))
155 cmd = run_command(detect_vendor.path())
156 if cmd.returncode() == 0
157 cmd_output = cmd.stdout().to_lower().strip().split(' ')
159 # Set to generic if variable is not found
160 machine = get_variable('impl_' + cmd_output[0], ['generic'])
161 if machine[0] == 'generic'
162 machine = impl_generic
163 cmd_output = cmd_generic
165 impl_pn = cmd_output[3]
166 if arm_force_native_march == true
170 impl_id = meson.get_cross_property('implementor_id', 'generic')
171 impl_pn = meson.get_cross_property('implementor_pn', 'default')
172 machine = get_variable('impl_' + impl_id)
175 # Apply Common Defaults. These settings may be overwritten by machine
177 foreach flag: flags_common_default
179 dpdk_conf.set(flag[0], flag[1])
183 message('Implementer : ' + machine[0])
184 foreach flag: machine[1]
186 dpdk_conf.set(flag[0], flag[1])
190 foreach marg: machine[2]
191 if marg[0] == impl_pn
192 foreach flag: marg[1]
193 if cc.has_argument(flag)
197 # Apply any extra machine specific flags.
198 foreach flag: marg.get(2, flags_default_extra)
200 dpdk_conf.set(flag[0], flag[1])
206 message(machine_args)
208 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
209 cc.get_define('__aarch64__', args: machine_args) != '')
210 dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1)
211 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
214 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
215 dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1)
216 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
219 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
220 dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
221 dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1)
222 dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1)
223 dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1)
224 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
225 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']