1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific aarch64 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific aarch64 flags have higher priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
40 'generic': {'machine_args': ['-march=armv8-a+crc',
45 part_number_config_arm = {
46 '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
47 '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
48 '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
49 '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
50 '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
51 '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
52 '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
54 'machine_args': ['-march=armv8.2-a+crypto',
57 ['RTE_MACHINE', '"neoverse-n1"'],
58 ['RTE_ARM_FEATURE_ATOMICS', true],
59 ['RTE_MAX_MEM_MB', 1048576],
60 ['RTE_MAX_LCORE', 160],
61 ['RTE_MAX_NUMA_NODES', 2]
65 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
67 ['RTE_MACHINE', '"neoverse-n2"'],
68 ['RTE_ARM_FEATURE_ATOMICS', true],
69 ['RTE_MAX_LCORE', 64],
70 ['RTE_MAX_NUMA_NODES', 1]
77 ['RTE_MACHINE', '"armv8a"'],
78 ['RTE_USE_C11_MEM_MODEL', true],
79 ['RTE_CACHE_LINE_SIZE', 64],
80 ['RTE_MAX_LCORE', 64],
81 ['RTE_MAX_NUMA_NODES', 4]
83 'part_number_config': part_number_config_arm
86 flags_part_number_thunderx = [
87 ['RTE_MACHINE', '"thunderx"'],
88 ['RTE_USE_C11_MEM_MODEL', false]
90 implementer_cavium = {
91 'description': 'Cavium',
93 ['RTE_MAX_VFIO_GROUPS', 128],
94 ['RTE_MAX_LCORE', 96],
95 ['RTE_MAX_NUMA_NODES', 2]
97 'part_number_config': {
99 'machine_args': ['-mcpu=thunderxt88'],
100 'flags': flags_part_number_thunderx
103 'machine_args': ['-mcpu=thunderxt81'],
104 'flags': flags_part_number_thunderx
107 'machine_args': ['-mcpu=thunderxt83'],
108 'flags': flags_part_number_thunderx
111 'machine_args': ['-march=armv8.1-a+crc+crypto',
112 '-mcpu=thunderx2t99'],
114 ['RTE_MACHINE', '"thunderx2"'],
115 ['RTE_ARM_FEATURE_ATOMICS', true],
116 ['RTE_USE_C11_MEM_MODEL', true],
117 ['RTE_CACHE_LINE_SIZE', 64],
118 ['RTE_MAX_LCORE', 256]
122 'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
125 ['RTE_MACHINE', '"octeontx2"'],
126 ['RTE_ARM_FEATURE_ATOMICS', true],
127 ['RTE_USE_C11_MEM_MODEL', true],
128 ['RTE_MAX_LCORE', 36],
129 ['RTE_MAX_NUMA_NODES', 1]
135 implementer_ampere = {
136 'description': 'Ampere Computing',
138 ['RTE_MACHINE', '"emag"'],
139 ['RTE_CACHE_LINE_SIZE', 64],
140 ['RTE_MAX_LCORE', 32],
141 ['RTE_MAX_NUMA_NODES', 1]
143 'part_number_config': {
144 '0x0': {'machine_args': ['-march=armv8-a+crc+crypto',
149 implementer_hisilicon = {
150 'description': 'HiSilicon',
152 ['RTE_USE_C11_MEM_MODEL', true],
153 ['RTE_CACHE_LINE_SIZE', 128]
155 'part_number_config': {
157 'machine_args': ['-march=armv8.2-a+crypto',
160 ['RTE_MACHINE', '"Kunpeng 920"'],
161 ['RTE_ARM_FEATURE_ATOMICS', true],
162 ['RTE_MAX_LCORE', 256],
163 ['RTE_MAX_NUMA_NODES', 8]
167 'machine_args': ['-march=armv8.2-a+crypto+sve'],
169 ['RTE_MACHINE', '"Kunpeng 930"'],
170 ['RTE_ARM_FEATURE_ATOMICS', true],
171 ['RTE_MAX_LCORE', 1280],
172 ['RTE_MAX_NUMA_NODES', 16]
178 implementer_qualcomm = {
179 'description': 'Qualcomm',
181 ['RTE_MACHINE', '"armv8a"'],
182 ['RTE_USE_C11_MEM_MODEL', true],
183 ['RTE_CACHE_LINE_SIZE', 64],
184 ['RTE_MAX_LCORE', 64],
185 ['RTE_MAX_NUMA_NODES', 1]
187 'part_number_config': {
188 '0xc00': {'machine_args': ['-march=armv8-a+crc']}
192 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
194 'generic': implementer_generic,
195 '0x41': implementer_arm,
196 '0x43': implementer_cavium,
197 '0x48': implementer_hisilicon,
198 '0x50': implementer_ampere,
199 '0x51': implementer_qualcomm
202 # SoC specific aarch64 flags have the highest priority
203 # (will overwrite all other flags)
205 'description': 'Generic un-optimized build for all aarch64 machines',
206 'implementer': 'generic',
207 'part_number': 'generic'
211 'description': 'Marvell ARMADA',
212 'implementer': '0x41',
213 'part_number': '0xd08',
215 ['RTE_MAX_LCORE', 16],
216 ['RTE_MAX_NUMA_NODES', 1]
222 'description': 'NVIDIA BlueField',
223 'implementer': '0x41',
224 'part_number': '0xd08',
226 ['RTE_MAX_LCORE', 16],
227 ['RTE_MAX_NUMA_NODES', 1]
233 'description': 'NXP DPAA',
234 'implementer': '0x41',
235 'part_number': '0xd08',
237 ['RTE_MACHINE', '"dpaa"'],
238 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
239 ['RTE_MAX_LCORE', 16],
240 ['RTE_MAX_NUMA_NODES', 1]
246 'description': 'Ampere eMAG',
247 'implementer': '0x50',
252 'description': 'AWS Graviton2',
253 'implementer': '0x41',
254 'part_number': '0xd0c',
259 'description': 'HiSilicon Kunpeng 920',
260 'implementer': '0x48',
261 'part_number': '0xd01',
266 'description': 'HiSilicon Kunpeng 930',
267 'implementer': '0x48',
268 'part_number': '0xd02',
273 'description': 'Arm Neoverse N1SDP',
274 'implementer': '0x41',
275 'part_number': '0xd0c',
283 'description': 'Arm Neoverse N2',
284 'implementer': '0x41',
285 'part_number': '0xd49',
290 'description': 'Marvell OCTEON TX2',
291 'implementer': '0x43',
292 'part_number': '0xb2',
297 'description': 'Broadcom Stingray',
298 'implementer': '0x41',
300 ['RTE_MAX_LCORE', 16],
301 ['RTE_MAX_NUMA_NODES', 1]
303 'part_number': '0xd08',
308 'description': 'Marvell ThunderX2 T99',
309 'implementer': '0x43',
310 'part_number': '0xaf'
314 'description': 'Marvell ThunderX T88',
315 'implementer': '0x43',
316 'part_number': '0xa1'
320 'generic': soc_generic,
321 'armada': soc_armada,
322 'bluefield': soc_bluefield,
325 'graviton2': soc_graviton2,
326 'kunpeng920': soc_kunpeng920,
327 'kunpeng930': soc_kunpeng930,
330 'octeontx2': soc_octeontx2,
331 'stingray': soc_stingray,
332 'thunderx2': soc_thunderx2,
333 'thunderxt88': soc_thunderxt88
336 dpdk_conf.set('RTE_ARCH_ARM', 1)
337 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
339 if dpdk_conf.get('RTE_ARCH_32')
341 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
342 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
343 # the minimum architecture supported, armv7-a, needs the following,
344 machine_args += '-mfpu=neon'
347 soc = get_option('platform')
349 if not meson.is_cross_build()
350 if machine == 'generic'
353 error('Building for a particular platform is ' +
354 'unsupported with generic build.')
356 implementer_id = 'generic'
357 part_number = 'generic'
359 soc_config = socs.get(soc, {'not_supported': true})
362 # The script returns ['Implementer', 'Variant', 'Architecture',
363 # 'Primary Part number', 'Revision']
364 detect_vendor = find_program(join_paths(
365 meson.current_source_dir(), 'armv8_machine.py'))
366 cmd = run_command(detect_vendor.path())
367 if cmd.returncode() == 0
368 cmd_output = cmd.stdout().to_lower().strip().split(' ')
369 implementer_id = cmd_output[0]
370 part_number = cmd_output[3]
372 error('Error when getting Arm Implementer ID and part number.')
377 soc = meson.get_cross_property('platform', '')
379 error('Arm SoC must be specified in the cross file.')
381 soc_config = socs.get(soc, {'not_supported': true})
385 if soc_config.has_key('not_supported')
386 error('SoC @0@ not supported.'.format(soc))
387 elif soc_config != {}
388 implementer_id = soc_config['implementer']
389 implementer_config = implementers[implementer_id]
390 part_number = soc_config['part_number']
391 soc_flags = soc_config.get('flags', [])
392 if not soc_config.get('numa', true)
396 disable_drivers += ',' + soc_config.get('disable_drivers', '')
397 enable_drivers += ',' + soc_config.get('enable_drivers', '')
400 if implementers.has_key(implementer_id)
401 implementer_config = implementers[implementer_id]
403 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
404 'Please add support for it or use the generic ' +
405 '(-Dmachine=generic) build.')
408 message('Arm implementer: ' + implementer_config['description'])
409 message('Arm part number: ' + part_number)
411 part_number_config = implementer_config['part_number_config']
412 if part_number_config.has_key(part_number)
413 # use the specified part_number machine args if found
414 part_number_config = part_number_config[part_number]
416 # unknown part number
417 error('Unsupported part number @0@ of implementer @1@. '
418 .format(part_number, implementer_id) +
419 'Please add support for it or use the generic ' +
420 '(-Dmachine=generic) build.')
423 # add/overwrite flags in the proper order
424 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
426 # apply supported machine args
427 machine_args = [] # Clear previous machine args
428 foreach flag: part_number_config['machine_args']
429 if cc.has_argument(flag)
435 foreach flag: dpdk_flags
437 dpdk_conf.set(flag[0], flag[1])
441 message('Using machine args: @0@'.format(machine_args))
443 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
444 cc.get_define('__aarch64__', args: machine_args) != '')
445 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
448 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
449 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
452 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
453 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
454 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']