1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific aarch64 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific aarch64 flags have higher priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
40 'generic': {'machine_args': ['-march=armv8-a+crc', '-moutline-atomics']}
44 part_number_config_arm = {
45 '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
46 '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
47 '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
48 '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
49 '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
50 '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
51 '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
53 'machine_args': ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
55 ['RTE_MACHINE', '"neoverse-n1"'],
56 ['RTE_ARM_FEATURE_ATOMICS', true],
57 ['RTE_MAX_MEM_MB', 1048576],
58 ['RTE_MAX_LCORE', 160],
59 ['RTE_MAX_NUMA_NODES', 2]
63 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
65 ['RTE_MACHINE', '"neoverse-n2"'],
66 ['RTE_ARM_FEATURE_ATOMICS', true],
67 ['RTE_MAX_LCORE', 64],
68 ['RTE_MAX_NUMA_NODES', 1]
75 ['RTE_MACHINE', '"armv8a"'],
76 ['RTE_USE_C11_MEM_MODEL', true],
77 ['RTE_CACHE_LINE_SIZE', 64],
78 ['RTE_MAX_LCORE', 64],
79 ['RTE_MAX_NUMA_NODES', 4]
81 'part_number_config': part_number_config_arm
84 flags_part_number_thunderx = [
85 ['RTE_MACHINE', '"thunderx"'],
86 ['RTE_USE_C11_MEM_MODEL', false]
88 implementer_cavium = {
89 'description': 'Cavium',
91 ['RTE_MAX_VFIO_GROUPS', 128],
92 ['RTE_MAX_LCORE', 96],
93 ['RTE_MAX_NUMA_NODES', 2]
95 'part_number_config': {
97 'machine_args': ['-mcpu=thunderxt88'],
98 'flags': flags_part_number_thunderx
101 'machine_args': ['-mcpu=thunderxt81'],
102 'flags': flags_part_number_thunderx
105 'machine_args': ['-mcpu=thunderxt83'],
106 'flags': flags_part_number_thunderx
109 'machine_args': ['-march=armv8.1-a+crc+crypto', '-mcpu=thunderx2t99'],
111 ['RTE_MACHINE', '"thunderx2"'],
112 ['RTE_ARM_FEATURE_ATOMICS', true],
113 ['RTE_USE_C11_MEM_MODEL', true],
114 ['RTE_CACHE_LINE_SIZE', 64],
115 ['RTE_MAX_LCORE', 256]
119 'machine_args': ['-march=armv8.2-a+crc+crypto+lse', '-mcpu=octeontx2'],
121 ['RTE_MACHINE', '"octeontx2"'],
122 ['RTE_ARM_FEATURE_ATOMICS', true],
123 ['RTE_USE_C11_MEM_MODEL', true],
124 ['RTE_MAX_LCORE', 36],
125 ['RTE_MAX_NUMA_NODES', 1]
131 implementer_ampere = {
132 'description': 'Ampere Computing',
134 ['RTE_MACHINE', '"emag"'],
135 ['RTE_CACHE_LINE_SIZE', 64],
136 ['RTE_MAX_LCORE', 32],
137 ['RTE_MAX_NUMA_NODES', 1]
139 'part_number_config': {
140 '0x0': {'machine_args': ['-march=armv8-a+crc+crypto', '-mtune=emag']}
144 implementer_hisilicon = {
145 'description': 'HiSilicon',
147 ['RTE_USE_C11_MEM_MODEL', true],
148 ['RTE_CACHE_LINE_SIZE', 128]
150 'part_number_config': {
152 'machine_args': ['-march=armv8.2-a+crypto', '-mtune=tsv110'],
154 ['RTE_MACHINE', '"Kunpeng 920"'],
155 ['RTE_ARM_FEATURE_ATOMICS', true],
156 ['RTE_MAX_LCORE', 256],
157 ['RTE_MAX_NUMA_NODES', 8]
161 'machine_args': ['-march=armv8.2-a+crypto+sve'],
163 ['RTE_MACHINE', '"Kunpeng 930"'],
164 ['RTE_ARM_FEATURE_ATOMICS', true],
165 ['RTE_MAX_LCORE', 1280],
166 ['RTE_MAX_NUMA_NODES', 16]
172 implementer_qualcomm = {
173 'description': 'Qualcomm',
175 ['RTE_MACHINE', '"armv8a"'],
176 ['RTE_USE_C11_MEM_MODEL', true],
177 ['RTE_CACHE_LINE_SIZE', 64],
178 ['RTE_MAX_LCORE', 64],
179 ['RTE_MAX_NUMA_NODES', 1]
181 'part_number_config': {
182 '0xc00': {'machine_args': ['-march=armv8-a+crc']}
186 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
188 'generic': implementer_generic,
189 '0x41': implementer_arm,
190 '0x43': implementer_cavium,
191 '0x48': implementer_hisilicon,
192 '0x50': implementer_ampere,
193 '0x51': implementer_qualcomm
196 # SoC specific aarch64 flags have the highest priority
197 # (will overwrite all other flags)
199 'description': 'Generic un-optimized build for all aarch64 machines',
200 'implementer': 'generic',
201 'part_number': 'generic'
205 'description': 'Marvell ARMADA',
206 'implementer': '0x41',
207 'part_number': '0xd08',
209 ['RTE_MAX_LCORE', 16],
210 ['RTE_MAX_NUMA_NODES', 1]
216 'description': 'NVIDIA BlueField',
217 'implementer': '0x41',
218 'part_number': '0xd08',
220 ['RTE_MAX_LCORE', 16],
221 ['RTE_MAX_NUMA_NODES', 1]
227 'description': 'Qualcomm Centriq 2400',
228 'implementer': '0x51',
229 'part_number': '0xc00',
234 'description' : 'Marvell OCTEON 10',
235 'implementer' : '0x41',
237 ['RTE_MAX_LCORE', 24],
238 ['RTE_MAX_NUMA_NODES', 1]
240 'part_number': '0xd49',
245 'description': 'NXP DPAA',
246 'implementer': '0x41',
247 'part_number': '0xd08',
249 ['RTE_MACHINE', '"dpaa"'],
250 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
251 ['RTE_MAX_LCORE', 16],
252 ['RTE_MAX_NUMA_NODES', 1]
258 'description': 'Ampere eMAG',
259 'implementer': '0x50',
264 'description': 'AWS Graviton2',
265 'implementer': '0x41',
266 'part_number': '0xd0c',
271 'description': 'HiSilicon Kunpeng 920',
272 'implementer': '0x48',
273 'part_number': '0xd01',
278 'description': 'HiSilicon Kunpeng 930',
279 'implementer': '0x48',
280 'part_number': '0xd02',
285 'description': 'Arm Neoverse N1SDP',
286 'implementer': '0x41',
287 'part_number': '0xd0c',
295 'description': 'Arm Neoverse N2',
296 'implementer': '0x41',
297 'part_number': '0xd49',
302 'description': 'Marvell OCTEON TX2',
303 'implementer': '0x43',
304 'part_number': '0xb2',
309 'description': 'Broadcom Stingray',
310 'implementer': '0x41',
312 ['RTE_MAX_LCORE', 16],
313 ['RTE_MAX_NUMA_NODES', 1]
315 'part_number': '0xd08',
320 'description': 'Marvell ThunderX2 T99',
321 'implementer': '0x43',
322 'part_number': '0xaf'
326 'description': 'Marvell ThunderX T88',
327 'implementer': '0x43',
328 'part_number': '0xa1'
333 generic: Generic un-optimized build for all aarch64 machines.
334 armada: Marvell ARMADA
335 bluefield: NVIDIA BlueField
336 centriq2400: Qualcomm Centriq 2400
337 cn10k: Marvell OCTEON 10
340 graviton2: AWS Graviton2
341 kunpeng920: HiSilicon Kunpeng 920
342 kunpeng930: HiSilicon Kunpeng 930
343 n1sdp: Arm Neoverse N1SDP
345 octeontx2: Marvell OCTEON TX2
346 stingray: Broadcom Stingray
347 thunderx2: Marvell ThunderX2 T99
348 thunderxt88: Marvell ThunderX T88
351 # The string above is included in the documentation, keep it in sync with the
354 'generic': soc_generic,
355 'armada': soc_armada,
356 'bluefield': soc_bluefield,
357 'centriq2400': soc_centriq2400,
361 'graviton2': soc_graviton2,
362 'kunpeng920': soc_kunpeng920,
363 'kunpeng930': soc_kunpeng930,
366 'octeontx2': soc_octeontx2,
367 'stingray': soc_stingray,
368 'thunderx2': soc_thunderx2,
369 'thunderxt88': soc_thunderxt88
372 dpdk_conf.set('RTE_ARCH_ARM', 1)
373 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
375 if dpdk_conf.get('RTE_ARCH_32')
377 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
378 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
379 # the minimum architecture supported, armv7-a, needs the following,
380 machine_args += '-mfpu=neon'
383 soc = get_option('platform')
385 if not meson.is_cross_build()
386 if machine == 'generic'
389 error('Building for a particular platform is unsupported with generic build.')
391 implementer_id = 'generic'
392 part_number = 'generic'
394 soc_config = socs.get(soc, {'not_supported': true})
397 # The script returns ['Implementer', 'Variant', 'Architecture',
398 # 'Primary Part number', 'Revision']
399 detect_vendor = find_program(join_paths(meson.current_source_dir(),
401 cmd = run_command(detect_vendor.path())
402 if cmd.returncode() == 0
403 cmd_output = cmd.stdout().to_lower().strip().split(' ')
404 implementer_id = cmd_output[0]
405 part_number = cmd_output[3]
407 error('Error when getting Arm Implementer ID and part number.')
412 soc = meson.get_cross_property('platform', '')
414 error('Arm SoC must be specified in the cross file.')
416 soc_config = socs.get(soc, {'not_supported': true})
420 if soc_config.has_key('not_supported')
421 error('SoC @0@ not supported.'.format(soc))
422 elif soc_config != {}
423 implementer_id = soc_config['implementer']
424 implementer_config = implementers[implementer_id]
425 part_number = soc_config['part_number']
426 soc_flags = soc_config.get('flags', [])
427 if not soc_config.get('numa', true)
431 disable_drivers += ',' + soc_config.get('disable_drivers', '')
432 enable_drivers += ',' + soc_config.get('enable_drivers', '')
435 if implementers.has_key(implementer_id)
436 implementer_config = implementers[implementer_id]
438 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
439 'Please add support for it or use the generic ' +
440 '(-Dmachine=generic) build.')
443 message('Arm implementer: ' + implementer_config['description'])
444 message('Arm part number: ' + part_number)
446 part_number_config = implementer_config['part_number_config']
447 if part_number_config.has_key(part_number)
448 # use the specified part_number machine args if found
449 part_number_config = part_number_config[part_number]
451 # unknown part number
452 error('Unsupported part number @0@ of implementer @1@. '
453 .format(part_number, implementer_id) +
454 'Please add support for it or use the generic ' +
455 '(-Dmachine=generic) build.')
458 # add/overwrite flags in the proper order
459 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
461 # apply supported machine args
462 machine_args = [] # Clear previous machine args
463 foreach flag: part_number_config['machine_args']
464 if cc.has_argument(flag)
470 foreach flag: dpdk_flags
472 dpdk_conf.set(flag[0], flag[1])
476 message('Using machine args: @0@'.format(machine_args))
478 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
479 cc.get_define('__aarch64__', args: machine_args) != '')
480 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
483 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
484 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
487 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
488 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
491 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
492 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
493 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']