1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
5 # common flags to all aarch64 builds, with lowest priority
7 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
8 # to determine the best threshold in code. Refer to notes in source file
9 # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
10 ['RTE_ARCH_ARM64_MEMCPY', false],
11 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
12 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
13 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
14 # unless there are strong reasons.
15 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
16 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
17 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
19 ['RTE_NET_FM10K', false],
20 ['RTE_NET_AVP', false],
22 ['RTE_SCHED_VECTOR', false],
23 ['RTE_ARM_USE_WFE', false],
24 ['RTE_ARCH_ARM64', true],
25 ['RTE_CACHE_LINE_SIZE', 128]
27 native_machine_args = ['-mcpu=native']
29 ## Part numbers are specific to Arm implementers
30 # implementer specific aarch64 flags have middle priority
31 # (will overwrite common flags)
32 # part number specific aarch64 flags have the highest priority
33 # (will overwrite both common and implementer specific flags)
34 implementer_generic = {
35 'description': 'Generic armv8',
37 ['RTE_MACHINE', '"armv8a"'],
38 ['RTE_USE_C11_MEM_MODEL', true],
39 ['RTE_MAX_LCORE', 256]
41 'part_number_config': {
42 'generic': {'machine_args': ['-march=armv8-a+crc',
47 part_number_config_arm = {
48 '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
49 '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
50 '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
51 '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
52 '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
53 '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
54 '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
56 'machine_args': ['-march=armv8.2-a+crypto',
59 ['RTE_MACHINE', '"neoverse-n1"'],
60 ['RTE_ARM_FEATURE_ATOMICS', true],
61 ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
62 ['RTE_LIBRTE_VHOST_NUMA', false],
63 ['RTE_MAX_MEM_MB', 1048576],
64 ['RTE_MAX_LCORE', 80],
65 ['RTE_MAX_NUMA_NODES', 1]
69 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
71 ['RTE_MACHINE', '"neoverse-n2"'],
72 ['RTE_ARM_FEATURE_ATOMICS', true],
73 ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
74 ['RTE_LIBRTE_VHOST_NUMA', false],
82 ['RTE_MACHINE', '"armv8a"'],
83 ['RTE_USE_C11_MEM_MODEL', true],
84 ['RTE_CACHE_LINE_SIZE', 64],
87 'part_number_config': part_number_config_arm
90 flags_part_number_thunderx = [
91 ['RTE_MACHINE', '"thunderx"'],
92 ['RTE_USE_C11_MEM_MODEL', false]
94 implementer_cavium = {
95 'description': 'Cavium',
97 ['RTE_MAX_VFIO_GROUPS', 128],
98 ['RTE_MAX_LCORE', 96],
99 ['RTE_MAX_NUMA_NODES', 2]
101 'part_number_config': {
103 'machine_args': ['-mcpu=thunderxt88'],
104 'flags': flags_part_number_thunderx
107 'machine_args': ['-mcpu=thunderxt81'],
108 'flags': flags_part_number_thunderx
111 'machine_args': ['-mcpu=thunderxt83'],
112 'flags': flags_part_number_thunderx
115 'machine_args': ['-march=armv8.1-a+crc+crypto',
116 '-mcpu=thunderx2t99'],
118 ['RTE_MACHINE', '"thunderx2"'],
119 ['RTE_ARM_FEATURE_ATOMICS', true],
120 ['RTE_USE_C11_MEM_MODEL', true],
121 ['RTE_CACHE_LINE_SIZE', 64],
122 ['RTE_MAX_LCORE', 256],
123 ['RTE_MAX_NUMA_NODES', 2]
127 'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
130 ['RTE_MACHINE', '"octeontx2"'],
131 ['RTE_ARM_FEATURE_ATOMICS', true],
132 ['RTE_USE_C11_MEM_MODEL', true],
133 ['RTE_EAL_IGB_UIO', false],
134 ['RTE_MAX_LCORE', 36],
135 ['RTE_MAX_NUMA_NODES', 1]
141 implementer_ampere = {
142 'description': 'Ampere Computing',
144 ['RTE_MACHINE', '"emag"'],
145 ['RTE_CACHE_LINE_SIZE', 64],
146 ['RTE_MAX_LCORE', 32],
147 ['RTE_MAX_NUMA_NODES', 1]
149 'part_number_config': {
150 '0x0': {'machine_args': ['-march=armv8-a+crc+crypto',
155 implementer_marvell = {
156 'description': 'Marvell ARMADA',
158 ['RTE_MACHINE', '"armv8a"'],
159 ['RTE_CACHE_LINE_SIZE', 64],
160 ['RTE_MAX_LCORE', 16],
161 ['RTE_MAX_NUMA_NODES', 1]
163 'part_number_config': part_number_config_arm
167 'description': 'NXP DPAA',
169 ['RTE_MACHINE', '"dpaa"'],
170 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
171 ['RTE_USE_C11_MEM_MODEL', true],
172 ['RTE_CACHE_LINE_SIZE', 64],
173 ['RTE_MAX_LCORE', 16],
174 ['RTE_MAX_NUMA_NODES', 1]
176 'part_number_config': part_number_config_arm
179 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
181 'generic': implementer_generic,
182 '0x41': implementer_arm,
183 '0x43': implementer_cavium,
184 '0x50': implementer_ampere,
185 '0x56': implementer_marvell,
186 'dpaa': implementer_dpaa
189 dpdk_conf.set('RTE_ARCH_ARM', 1)
190 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
192 if dpdk_conf.get('RTE_ARCH_32')
194 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
195 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
196 # the minimum architecture supported, armv7-a, needs the following,
197 machine_args += '-mfpu=neon'
200 use_native_machine_args = false
201 if not meson.is_cross_build()
202 if machine == 'default'
204 implementer_id = 'generic'
205 part_number = 'generic'
208 # The script returns ['Implementer', 'Variant', 'Architecture',
209 # 'Primary Part number', 'Revision']
210 detect_vendor = find_program(join_paths(
211 meson.current_source_dir(), 'armv8_machine.py'))
212 cmd = run_command(detect_vendor.path())
213 if cmd.returncode() == 0
214 cmd_output = cmd.stdout().to_lower().strip().split(' ')
215 implementer_id = cmd_output[0]
216 part_number = cmd_output[3]
218 error('Error when getting Arm Implementer ID and part number.')
220 use_native_machine_args = true
224 implementer_id = meson.get_cross_property('implementer_id')
225 part_number = meson.get_cross_property('part_number')
228 if implementers.has_key(implementer_id)
229 implementer_config = implementers[implementer_id]
231 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
232 'Please add support for it or use the generic ' +
233 '(-Dmachine=generic) build.')
236 message('Arm implementer: ' + implementer_config['description'])
237 message('Arm part number: ' + part_number)
239 part_number_config = implementer_config['part_number_config']
240 if part_number_config.has_key(part_number)
241 # use the specified part_number machine args if found
242 part_number_config = part_number_config[part_number]
244 # unknown part number
245 error('Unsupported part number @0@ of implementer @1@. '
246 .format(part_number, implementer_id) +
247 'Please add support for it or use the generic ' +
248 '(-Dmachine=generic) build.')
251 # use default flags with implementer flags
252 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', [])
254 # apply supported machine args
255 machine_args = [] # Clear previous machine args
256 if use_native_machine_args
257 candidate_machine_args = native_machine_args
259 candidate_machine_args = part_number_config['machine_args']
261 foreach flag: candidate_machine_args
262 if cc.has_argument(flag)
268 foreach flag: dpdk_flags
270 dpdk_conf.set(flag[0], flag[1])
274 message('Using machine args: @0@'.format(machine_args))
276 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
277 cc.get_define('__aarch64__', args: machine_args) != '')
278 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
281 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
282 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
285 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
286 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
287 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']