1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_ARM_USE_WFE', false],
21 ['RTE_ARCH_ARM64', true],
22 ['RTE_CACHE_LINE_SIZE', 128]
25 ## Part numbers are specific to Arm implementers
26 # implementer specific armv8 flags have middle priority
27 # (will overwrite common flags)
28 # part number specific armv8 flags have higher priority
29 # (will overwrite both common and implementer specific flags)
30 implementer_generic = {
31 'description': 'Generic armv8',
33 ['RTE_MACHINE', '"armv8a"'],
34 ['RTE_USE_C11_MEM_MODEL', true],
35 ['RTE_MAX_LCORE', 256],
36 ['RTE_MAX_NUMA_NODES', 4]
38 'part_number_config': {
41 'march_features': ['crc'],
42 'compiler_options': ['-moutline-atomics']
46 'compiler_options': ['-mfpu=neon'],
48 ['RTE_ARCH_ARM_NEON_MEMCPY', false],
49 ['RTE_ARCH_STRICT_ALIGN', true],
50 ['RTE_ARCH_ARMv8_AARCH32', true],
51 ['RTE_ARCH', 'armv8_aarch32'],
52 ['RTE_CACHE_LINE_SIZE', 64]
58 part_number_config_arm = {
59 '0xd03': {'compiler_options': ['-mcpu=cortex-a53']},
60 '0xd04': {'compiler_options': ['-mcpu=cortex-a35']},
61 '0xd07': {'compiler_options': ['-mcpu=cortex-a57']},
62 '0xd08': {'compiler_options': ['-mcpu=cortex-a72']},
63 '0xd09': {'compiler_options': ['-mcpu=cortex-a73']},
64 '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']},
65 '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']},
68 'march_features': ['crypto'],
69 'compiler_options': ['-mcpu=neoverse-n1'],
71 ['RTE_MACHINE', '"neoverse-n1"'],
72 ['RTE_ARM_FEATURE_ATOMICS', true],
73 ['RTE_MAX_MEM_MB', 1048576],
74 ['RTE_MAX_LCORE', 160],
75 ['RTE_MAX_NUMA_NODES', 2]
80 'march_features': ['sve2'],
82 ['RTE_MACHINE', '"neoverse-n2"'],
83 ['RTE_ARM_FEATURE_ATOMICS', true],
84 ['RTE_MAX_LCORE', 64],
85 ['RTE_MAX_NUMA_NODES', 1]
92 ['RTE_MACHINE', '"armv8a"'],
93 ['RTE_USE_C11_MEM_MODEL', true],
94 ['RTE_CACHE_LINE_SIZE', 64],
95 ['RTE_MAX_LCORE', 64],
96 ['RTE_MAX_NUMA_NODES', 4]
98 'part_number_config': part_number_config_arm
101 flags_part_number_thunderx = [
102 ['RTE_MACHINE', '"thunderx"'],
103 ['RTE_USE_C11_MEM_MODEL', false]
105 implementer_cavium = {
106 'description': 'Cavium',
108 ['RTE_MAX_VFIO_GROUPS', 128],
109 ['RTE_MAX_LCORE', 96],
110 ['RTE_MAX_NUMA_NODES', 2]
112 'part_number_config': {
114 'compiler_options': ['-mcpu=thunderxt88'],
115 'flags': flags_part_number_thunderx
118 'compiler_options': ['-mcpu=thunderxt81'],
119 'flags': flags_part_number_thunderx
122 'compiler_options': ['-march=armv8-a+crc', '-mcpu=thunderxt83'],
123 'flags': flags_part_number_thunderx
126 'march': 'armv8.1-a',
127 'march_features': ['crc', 'crypto'],
128 'compiler_options': ['-mcpu=thunderx2t99'],
130 ['RTE_MACHINE', '"thunderx2"'],
131 ['RTE_ARM_FEATURE_ATOMICS', true],
132 ['RTE_USE_C11_MEM_MODEL', true],
133 ['RTE_CACHE_LINE_SIZE', 64],
134 ['RTE_MAX_LCORE', 256]
138 'march': 'armv8.2-a',
139 'march_features': ['crc', 'crypto', 'lse'],
140 'compiler_options': ['-mcpu=octeontx2'],
142 ['RTE_MACHINE', '"cn9k"'],
143 ['RTE_ARM_FEATURE_ATOMICS', true],
144 ['RTE_USE_C11_MEM_MODEL', true],
145 ['RTE_MAX_LCORE', 36],
146 ['RTE_MAX_NUMA_NODES', 1]
152 implementer_ampere = {
153 'description': 'Ampere Computing',
155 ['RTE_MACHINE', '"emag"'],
156 ['RTE_CACHE_LINE_SIZE', 64],
157 ['RTE_MAX_LCORE', 32],
158 ['RTE_MAX_NUMA_NODES', 1]
160 'part_number_config': {
163 'march_features': ['crc', 'crypto'],
164 'compiler_options': ['-mtune=emag']
169 implementer_hisilicon = {
170 'description': 'HiSilicon',
172 ['RTE_USE_C11_MEM_MODEL', true],
173 ['RTE_CACHE_LINE_SIZE', 128]
175 'part_number_config': {
177 'march': 'armv8.2-a',
178 'march_features': ['crypto'],
179 'compiler_options': ['-mtune=tsv110'],
181 ['RTE_MACHINE', '"Kunpeng 920"'],
182 ['RTE_ARM_FEATURE_ATOMICS', true],
183 ['RTE_MAX_LCORE', 256],
184 ['RTE_MAX_NUMA_NODES', 8]
188 'march': 'armv8.2-a',
189 'march_features': ['crypto', 'sve'],
191 ['RTE_MACHINE', '"Kunpeng 930"'],
192 ['RTE_ARM_FEATURE_ATOMICS', true],
193 ['RTE_MAX_LCORE', 1280],
194 ['RTE_MAX_NUMA_NODES', 16]
200 implementer_qualcomm = {
201 'description': 'Qualcomm',
203 ['RTE_MACHINE', '"armv8a"'],
204 ['RTE_USE_C11_MEM_MODEL', true],
205 ['RTE_CACHE_LINE_SIZE', 64],
206 ['RTE_MAX_LCORE', 64],
207 ['RTE_MAX_NUMA_NODES', 1]
209 'part_number_config': {
212 'march_features': ['crc']
216 'march_features': ['crc']
221 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
223 'generic': implementer_generic,
224 '0x41': implementer_arm,
225 '0x43': implementer_cavium,
226 '0x48': implementer_hisilicon,
227 '0x50': implementer_ampere,
228 '0x51': implementer_qualcomm
231 # SoC specific armv8 flags have the highest priority
232 # (will overwrite all other flags)
234 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
235 'implementer': 'generic',
236 'part_number': 'generic'
239 soc_generic_aarch32 = {
240 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
241 'implementer': 'generic',
242 'part_number': 'generic_aarch32'
246 'description': 'Marvell ARMADA',
247 'implementer': '0x41',
248 'part_number': '0xd08',
250 ['RTE_MAX_LCORE', 16],
251 ['RTE_MAX_NUMA_NODES', 1]
257 'description': 'NVIDIA BlueField',
258 'implementer': '0x41',
259 'part_number': '0xd08',
261 ['RTE_MAX_LCORE', 16],
262 ['RTE_MAX_NUMA_NODES', 1]
268 'description': 'Qualcomm Centriq 2400',
269 'implementer': '0x51',
270 'part_number': '0xc00',
275 'description' : 'Marvell OCTEON 10',
276 'implementer' : '0x41',
278 ['RTE_MAX_LCORE', 24],
279 ['RTE_MAX_NUMA_NODES', 1],
280 ['RTE_MEMPOOL_ALIGN', 128]
282 'part_number': '0xd49',
283 'extra_march_features': ['crypto'],
289 'description': 'NXP DPAA',
290 'implementer': '0x41',
291 'part_number': '0xd08',
293 ['RTE_MACHINE', '"dpaa"'],
294 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
295 ['RTE_MAX_LCORE', 16],
296 ['RTE_MAX_NUMA_NODES', 1]
302 'description': 'Ampere eMAG',
303 'implementer': '0x50',
308 'description': 'AWS Graviton2',
309 'implementer': '0x41',
310 'part_number': '0xd0c',
315 'description': 'HiSilicon Kunpeng 920',
316 'implementer': '0x48',
317 'part_number': '0xd01',
322 'description': 'HiSilicon Kunpeng 930',
323 'implementer': '0x48',
324 'part_number': '0xd02',
329 'description': 'Arm Neoverse N1SDP',
330 'implementer': '0x41',
331 'part_number': '0xd0c',
339 'description': 'Arm Neoverse N2',
340 'implementer': '0x41',
341 'part_number': '0xd49',
346 'description': 'Marvell OCTEON 9',
347 'implementer': '0x43',
348 'part_number': '0xb2',
353 'description': 'Broadcom Stingray',
354 'implementer': '0x41',
356 ['RTE_MAX_LCORE', 16],
357 ['RTE_MAX_NUMA_NODES', 1]
359 'part_number': '0xd08',
364 'description': 'Marvell ThunderX2 T99',
365 'implementer': '0x43',
366 'part_number': '0xaf'
370 'description': 'Marvell ThunderX T88',
371 'implementer': '0x43',
372 'part_number': '0xa1'
376 'description': 'Marvell ThunderX T83',
377 'implementer': '0x43',
378 'part_number': '0xa3'
383 generic: Generic un-optimized build for armv8 aarch64 execution mode.
384 generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.
385 armada: Marvell ARMADA
386 bluefield: NVIDIA BlueField
387 centriq2400: Qualcomm Centriq 2400
388 cn9k: Marvell OCTEON 9
389 cn10k: Marvell OCTEON 10
392 graviton2: AWS Graviton2
393 kunpeng920: HiSilicon Kunpeng 920
394 kunpeng930: HiSilicon Kunpeng 930
395 n1sdp: Arm Neoverse N1SDP
397 stingray: Broadcom Stingray
398 thunderx2: Marvell ThunderX2 T99
399 thunderxt88: Marvell ThunderX T88
400 thunderxt83: Marvell ThunderX T83
403 # The string above is included in the documentation, keep it in sync with the
406 'generic': soc_generic,
407 'generic_aarch32': soc_generic_aarch32,
408 'armada': soc_armada,
409 'bluefield': soc_bluefield,
410 'centriq2400': soc_centriq2400,
415 'graviton2': soc_graviton2,
416 'kunpeng920': soc_kunpeng920,
417 'kunpeng930': soc_kunpeng930,
420 'stingray': soc_stingray,
421 'thunderx2': soc_thunderx2,
422 'thunderxt88': soc_thunderxt88,
423 'thunderxt83': soc_thunderxt83,
426 dpdk_conf.set('RTE_ARCH_ARM', 1)
427 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
431 if dpdk_conf.get('RTE_ARCH_32')
433 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
434 if meson.is_cross_build()
436 soc = meson.get_cross_property('platform', '')
438 error('Arm SoC must be specified in the cross file.')
440 soc_config = socs.get(soc, {'not_supported': true})
444 dpdk_conf.set('RTE_ARCH_ARMv7', true)
445 dpdk_conf.set('RTE_ARCH', 'armv7')
446 dpdk_conf.set('RTE_MAX_LCORE', 128)
447 dpdk_conf.set('RTE_MAX_NUMA_NODES', 1)
448 # the minimum architecture supported, armv7-a, needs the following,
449 machine_args += '-mfpu=neon'
453 dpdk_conf.set('RTE_ARCH', 'armv8')
456 if not meson.is_cross_build()
457 # for backwards compatibility:
458 # machine=native is the same behavior as soc=native
459 # machine=generic/default is the same as soc=generic
460 # cpu_instruction_set holds the proper value - native, generic or cpu
461 # the old behavior only distinguished between generic and native build
463 if cpu_instruction_set == 'generic'
473 # The script returns ['Implementer', 'Variant', 'Architecture',
474 # 'Primary Part number', 'Revision']
475 detect_vendor = find_program(join_paths(meson.current_source_dir(),
477 cmd = run_command(detect_vendor.path(), check: false)
478 if cmd.returncode() == 0
479 cmd_output = cmd.stdout().to_lower().strip().split(' ')
480 implementer_id = cmd_output[0]
481 part_number = cmd_output[3]
483 error('Error when getting Arm Implementer ID and part number.')
487 soc_config = socs.get(soc, {'not_supported': true})
491 soc = meson.get_cross_property('platform', '')
493 error('Arm SoC must be specified in the cross file.')
495 soc_config = socs.get(soc, {'not_supported': true})
500 if soc_config.has_key('not_supported')
501 error('SoC @0@ not supported.'.format(soc))
502 elif soc_config != {}
503 implementer_id = soc_config['implementer']
504 implementer_config = implementers[implementer_id]
505 part_number = soc_config['part_number']
506 soc_flags = soc_config.get('flags', [])
507 if not soc_config.get('numa', true)
511 disable_drivers += ',' + soc_config.get('disable_drivers', '')
512 enable_drivers += ',' + soc_config.get('enable_drivers', '')
515 if implementers.has_key(implementer_id)
516 implementer_config = implementers[implementer_id]
518 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
519 'Please add support for it or use the generic ' +
520 '(-Dplatform=generic) build.')
523 message('Arm implementer: ' + implementer_config['description'])
524 message('Arm part number: ' + part_number)
526 part_number_config = implementer_config['part_number_config']
527 if part_number_config.has_key(part_number)
528 # use the specified part_number machine args if found
529 part_number_config = part_number_config[part_number]
531 # unknown part number
532 error('Unsupported part number @0@ of implementer @1@. '
533 .format(part_number, implementer_id) +
534 'Please add support for it or use the generic ' +
535 '(-Dplatform=generic) build.')
538 # add/overwrite flags in the proper order
539 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
541 machine_args = [] # Clear previous machine args
543 # probe supported archs and their features
545 if part_number_config.has_key('march')
546 supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a',
547 'armv8.2-a', 'armv8.1-a', 'armv8-a']
548 check_compiler_support = false
549 foreach supported_march: supported_marchs
550 if supported_march == part_number_config['march']
551 # start checking from this version downwards
552 check_compiler_support = true
554 if (check_compiler_support and
555 cc.has_argument('-march=' + supported_march))
556 candidate_march = supported_march
557 # highest supported march version found
561 if candidate_march == ''
562 error('No suitable armv8 march version found.')
564 if candidate_march != part_number_config['march']
565 warning('Configuration march version is ' +
566 '@0@, but the compiler supports only @1@.'
567 .format(part_number_config['march'], candidate_march))
569 candidate_march = '-march=' + candidate_march
572 if part_number_config.has_key('march_features')
573 march_features += part_number_config['march_features']
575 if soc_config.has_key('extra_march_features')
576 march_features += soc_config['extra_march_features']
578 foreach feature: march_features
579 if cc.has_argument('+'.join([candidate_march, feature]))
580 candidate_march = '+'.join([candidate_march, feature])
582 warning('The compiler does not support feature @0@'
586 machine_args += candidate_march
589 # apply supported compiler options
590 if part_number_config.has_key('compiler_options')
591 foreach flag: part_number_config['compiler_options']
592 if cc.has_argument(flag)
595 warning('Configuration compiler option ' +
596 '@0@ isn\'t supported.'.format(flag))
602 foreach flag: dpdk_flags
604 dpdk_conf.set(flag[0], flag[1])
608 message('Using machine args: @0@'.format(machine_args))
610 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
611 cc.get_define('__aarch64__', args: machine_args) != '')
612 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
615 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
616 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
617 if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', true))
618 dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
622 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
623 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
626 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
627 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
628 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']