config/arm/meson.build

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright(c) 2017 Intel Corporation.
   3 # Copyright(c) 2017 Cavium, Inc
   4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
   5
   6 # common flags to all aarch64 builds, with lowest priority
   7 flags_common = [
   8         # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
   9         # to determine the best threshold in code. Refer to notes in source file
  10         # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
  11         ['RTE_ARCH_ARM64_MEMCPY', false],
  12         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
  13         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
  14         # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
  15         # unless there are strong reasons.
  16         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
  17         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
  18         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
  19
  20         ['RTE_NET_FM10K', false],
  21         ['RTE_NET_AVP', false],
  22
  23         ['RTE_SCHED_VECTOR', false],
  24         ['RTE_ARM_USE_WFE', false],
  25         ['RTE_ARCH_ARM64', true],
  26         ['RTE_CACHE_LINE_SIZE', 128]
  27 ]
  28
  29 ## Part numbers are specific to Arm implementers
  30 # implementer specific aarch64 flags have middle priority
  31 #     (will overwrite common flags)
  32 # part number specific aarch64 flags have the highest priority
  33 #     (will overwrite both common and implementer specific flags)
  34 implementer_generic = {
  35         'description': 'Generic armv8',
  36         'flags': [
  37                 ['RTE_MACHINE', '"armv8a"'],
  38                 ['RTE_USE_C11_MEM_MODEL', true],
  39                 ['RTE_MAX_LCORE', 256],
  40                 ['RTE_MAX_NUMA_NODES', 4]
  41         ],
  42         'part_number_config': {
  43                 'generic': {'machine_args': ['-march=armv8-a+crc',
  44                                              '-moutline-atomics']}
  45         }
  46 }
  47
  48 part_number_config_arm = {
  49         '0xd03': {'machine_args':  ['-mcpu=cortex-a53']},
  50         '0xd04': {'machine_args':  ['-mcpu=cortex-a35']},
  51         '0xd07': {'machine_args':  ['-mcpu=cortex-a57']},
  52         '0xd08': {'machine_args':  ['-mcpu=cortex-a72']},
  53         '0xd09': {'machine_args':  ['-mcpu=cortex-a73']},
  54         '0xd0a': {'machine_args':  ['-mcpu=cortex-a75']},
  55         '0xd0b': {'machine_args':  ['-mcpu=cortex-a76']},
  56         '0xd0c': {
  57                 'machine_args':  ['-march=armv8.2-a+crypto',
  58                                   '-mcpu=neoverse-n1'],
  59                 'flags': [
  60                         ['RTE_MACHINE', '"neoverse-n1"'],
  61                         ['RTE_ARM_FEATURE_ATOMICS', true],
  62                         ['RTE_MAX_MEM_MB', 1048576],
  63                         ['RTE_MAX_LCORE', 80]
  64                 ]
  65         },
  66         '0xd49': {
  67                 'machine_args':  ['-march=armv8.5-a+crypto+sve2'],
  68                 'flags': [
  69                         ['RTE_MACHINE', '"neoverse-n2"'],
  70                         ['RTE_ARM_FEATURE_ATOMICS', true],
  71                         ['RTE_MAX_LCORE', 64]
  72                 ]
  73         }
  74 }
  75 implementer_arm = {
  76         'description': 'Arm',
  77         'flags': [
  78                 ['RTE_MACHINE', '"armv8a"'],
  79                 ['RTE_USE_C11_MEM_MODEL', true],
  80                 ['RTE_CACHE_LINE_SIZE', 64],
  81                 ['RTE_MAX_LCORE', 16],
  82                 ['RTE_MAX_NUMA_NODES', 1]
  83         ],
  84         'part_number_config': part_number_config_arm
  85 }
  86
  87 flags_part_number_thunderx = [
  88         ['RTE_MACHINE', '"thunderx"'],
  89         ['RTE_USE_C11_MEM_MODEL', false]
  90 ]
  91 implementer_cavium = {
  92         'description': 'Cavium',
  93         'flags': [
  94                 ['RTE_MAX_VFIO_GROUPS', 128],
  95                 ['RTE_MAX_LCORE', 96],
  96                 ['RTE_MAX_NUMA_NODES', 2]
  97         ],
  98         'part_number_config': {
  99                 '0xa1': {
 100                         'machine_args': ['-mcpu=thunderxt88'],
 101                         'flags': flags_part_number_thunderx
 102                 },
 103                 '0xa2': {
 104                         'machine_args': ['-mcpu=thunderxt81'],
 105                         'flags': flags_part_number_thunderx
 106                 },
 107                 '0xa3': {
 108                         'machine_args': ['-mcpu=thunderxt83'],
 109                         'flags': flags_part_number_thunderx
 110                 },
 111                 '0xaf': {
 112                         'machine_args': ['-march=armv8.1-a+crc+crypto',
 113                                          '-mcpu=thunderx2t99'],
 114                         'flags': [
 115                                 ['RTE_MACHINE', '"thunderx2"'],
 116                                 ['RTE_ARM_FEATURE_ATOMICS', true],
 117                                 ['RTE_USE_C11_MEM_MODEL', true],
 118                                 ['RTE_CACHE_LINE_SIZE', 64],
 119                                 ['RTE_MAX_LCORE', 256]
 120                         ]
 121                 },
 122                 '0xb2': {
 123                         'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
 124                                          '-mcpu=octeontx2'],
 125                         'flags': [
 126                                 ['RTE_MACHINE', '"octeontx2"'],
 127                                 ['RTE_ARM_FEATURE_ATOMICS', true],
 128                                 ['RTE_USE_C11_MEM_MODEL', true],
 129                                 ['RTE_EAL_IGB_UIO', false],
 130                                 ['RTE_MAX_LCORE', 36],
 131                                 ['RTE_MAX_NUMA_NODES', 1]
 132                         ]
 133                 }
 134         }
 135 }
 136
 137 implementer_ampere = {
 138         'description': 'Ampere Computing',
 139         'flags': [
 140                 ['RTE_MACHINE', '"emag"'],
 141                 ['RTE_CACHE_LINE_SIZE', 64],
 142                 ['RTE_MAX_LCORE', 32],
 143                 ['RTE_MAX_NUMA_NODES', 1]
 144         ],
 145         'part_number_config': {
 146                 '0x0': {'machine_args':  ['-march=armv8-a+crc+crypto',
 147                                           '-mtune=emag']}
 148         }
 149 }
 150
 151 implementer_qualcomm = {
 152         'description': 'Qualcomm',
 153         'flags': [
 154                 ['RTE_MACHINE', '"armv8a"'],
 155                 ['RTE_USE_C11_MEM_MODEL', true],
 156                 ['RTE_CACHE_LINE_SIZE', 64],
 157                 ['RTE_MAX_LCORE', 64],
 158                 ['RTE_MAX_NUMA_NODES', 1]
 159         ],
 160         'part_number_config': {
 161                 '0xc00': {'machine_args':  ['-march=armv8-a+crc']}
 162         }
 163 }
 164
 165 implementer_marvell = {
 166         'description': 'Marvell ARMADA',
 167         'flags': [
 168                 ['RTE_MACHINE', '"armv8a"'],
 169                 ['RTE_CACHE_LINE_SIZE', 64],
 170                 ['RTE_MAX_LCORE', 16],
 171                 ['RTE_MAX_NUMA_NODES', 1]
 172         ],
 173         'part_number_config': part_number_config_arm
 174 }
 175
 176 implementer_dpaa = {
 177         'description': 'NXP DPAA',
 178         'flags': [
 179                 ['RTE_MACHINE', '"dpaa"'],
 180                 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
 181                 ['RTE_USE_C11_MEM_MODEL', true],
 182                 ['RTE_CACHE_LINE_SIZE', 64],
 183                 ['RTE_MAX_LCORE', 16],
 184                 ['RTE_MAX_NUMA_NODES', 1]
 185         ],
 186         'part_number_config': part_number_config_arm
 187 }
 188
 189 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
 190 implementers = {
 191         'generic': implementer_generic,
 192         '0x41': implementer_arm,
 193         '0x43': implementer_cavium,
 194         '0x50': implementer_ampere,
 195         '0x51': implementer_qualcomm,
 196         '0x56': implementer_marvell,
 197         'dpaa': implementer_dpaa
 198 }
 199
 200 dpdk_conf.set('RTE_ARCH_ARM', 1)
 201 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
 202
 203 if dpdk_conf.get('RTE_ARCH_32')
 204         # armv7 build
 205         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
 206         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
 207         # the minimum architecture supported, armv7-a, needs the following,
 208         machine_args += '-mfpu=neon'
 209 else
 210         # aarch64 build
 211         if not meson.is_cross_build()
 212                 if machine == 'generic'
 213                         # generic build
 214                         implementer_id = 'generic'
 215                         part_number = 'generic'
 216                 else
 217                         # native build
 218                         # The script returns ['Implementer', 'Variant', 'Architecture',
 219                         # 'Primary Part number', 'Revision']
 220                         detect_vendor = find_program(join_paths(
 221                                         meson.current_source_dir(), 'armv8_machine.py'))
 222                         cmd = run_command(detect_vendor.path())
 223                         if cmd.returncode() == 0
 224                                 cmd_output = cmd.stdout().to_lower().strip().split(' ')
 225                                 implementer_id = cmd_output[0]
 226                                 part_number = cmd_output[3]
 227                         else
 228                                 error('Error when getting Arm Implementer ID and part number.')
 229                         endif
 230                 endif
 231         else
 232                 # cross build
 233                 implementer_id = meson.get_cross_property('implementer_id')
 234                 part_number = meson.get_cross_property('part_number')
 235         endif
 236
 237         if implementers.has_key(implementer_id)
 238                 implementer_config = implementers[implementer_id]
 239         else
 240                 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
 241                       'Please add support for it or use the generic ' +
 242                       '(-Dmachine=generic) build.')
 243         endif
 244
 245         message('Arm implementer: ' + implementer_config['description'])
 246         message('Arm part number: ' + part_number)
 247
 248         part_number_config = implementer_config['part_number_config']
 249         if part_number_config.has_key(part_number)
 250                 # use the specified part_number machine args if found
 251                 part_number_config = part_number_config[part_number]
 252         else
 253                 # unknown part number
 254                 error('Unsupported part number @0@ of implementer @1@. '
 255                       .format(part_number, implementer_id) +
 256                       'Please add support for it or use the generic ' +
 257                       '(-Dmachine=generic) build.')
 258         endif
 259
 260         # use common flags with implementer flags
 261         dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', [])
 262
 263         # apply supported machine args
 264         machine_args = [] # Clear previous machine args
 265         foreach flag: part_number_config['machine_args']
 266                 if cc.has_argument(flag)
 267                         machine_args += flag
 268                 endif
 269         endforeach
 270
 271         # apply flags
 272         foreach flag: dpdk_flags
 273                 if flag.length() > 0
 274                         dpdk_conf.set(flag[0], flag[1])
 275                 endif
 276         endforeach
 277 endif
 278 message('Using machine args: @0@'.format(machine_args))
 279
 280 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 281     cc.get_define('__aarch64__', args: machine_args) != '')
 282         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 283 endif
 284
 285 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
 286         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
 287 endif
 288
 289 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
 290         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
 291         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 292 endif