config/arm/meson.build

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright(c) 2017 Intel Corporation.
   3 # Copyright(c) 2017 Cavium, Inc
   4
   5 arm_force_native_march = false
   6
   7 # common flags to all aarch64 builds, with lowest priority
   8 flags_common = [
   9         # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
  10         # to determine the best threshold in code. Refer to notes in source file
  11         # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
  12         ['RTE_ARCH_ARM64_MEMCPY', false],
  13         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
  14         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
  15         # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
  16         # unless there are strong reasons.
  17         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
  18         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
  19         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
  20
  21         ['RTE_NET_FM10K', false],
  22         ['RTE_NET_AVP', false],
  23
  24         ['RTE_SCHED_VECTOR', false],
  25         ['RTE_ARM_USE_WFE', false],
  26         ['RTE_ARCH_ARM64', true],
  27         ['RTE_CACHE_LINE_SIZE', 128]
  28 ]
  29
  30 ## Part numbers are specific to Arm implementers
  31 # implementer specific aarch64 flags have middle priority
  32 #     (will overwrite common flags)
  33 # part number specific aarch64 flags have the highest priority
  34 #     (will overwrite both common and implementer specific flags)
  35 implementer_generic = {
  36         'description': 'Generic armv8',
  37         'flags': [
  38                 ['RTE_MACHINE', '"armv8a"'],
  39                 ['RTE_USE_C11_MEM_MODEL', true],
  40                 ['RTE_MAX_LCORE', 256]
  41         ],
  42         'part_number_config': {
  43                 'generic': {'machine_args': ['-march=armv8-a+crc',
  44                                              '-moutline-atomics']}
  45         }
  46 }
  47
  48 part_number_config_arm = {
  49         'native': {'machine_args':  ['-march=native']},
  50         '0xd03': {'machine_args':  ['-mcpu=cortex-a53']},
  51         '0xd04': {'machine_args':  ['-mcpu=cortex-a35']},
  52         '0xd07': {'machine_args':  ['-mcpu=cortex-a57']},
  53         '0xd08': {'machine_args':  ['-mcpu=cortex-a72']},
  54         '0xd09': {'machine_args':  ['-mcpu=cortex-a73']},
  55         '0xd0a': {'machine_args':  ['-mcpu=cortex-a75']},
  56         '0xd0b': {'machine_args':  ['-mcpu=cortex-a76']},
  57         '0xd0c': {
  58                 'machine_args':  ['-march=armv8.2-a+crypto',
  59                                   '-mcpu=neoverse-n1'],
  60                 'flags': [
  61                         ['RTE_MACHINE', '"neoverse-n1"'],
  62                         ['RTE_ARM_FEATURE_ATOMICS', true],
  63                         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
  64                         ['RTE_LIBRTE_VHOST_NUMA', false],
  65                         ['RTE_MAX_MEM_MB', 1048576],
  66                         ['RTE_MAX_LCORE', 80],
  67                         ['RTE_MAX_NUMA_NODES', 1]
  68                 ]
  69         },
  70         '0xd49': {
  71                 'machine_args':  ['-march=armv8.5-a+crypto+sve2'],
  72                 'flags': [
  73                         ['RTE_MACHINE', '"neoverse-n2"'],
  74                         ['RTE_ARM_FEATURE_ATOMICS', true],
  75                         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
  76                         ['RTE_LIBRTE_VHOST_NUMA', false],
  77                         ['RTE_MAX_LCORE', 64]
  78                 ]
  79         }
  80 }
  81 implementer_arm = {
  82         'description': 'Arm',
  83         'flags': [
  84                 ['RTE_MACHINE', '"armv8a"'],
  85                 ['RTE_USE_C11_MEM_MODEL', true],
  86                 ['RTE_CACHE_LINE_SIZE', 64],
  87                 ['RTE_MAX_LCORE', 16]
  88         ],
  89         'part_number_config': part_number_config_arm
  90 }
  91
  92 flags_part_number_thunderx = [
  93         ['RTE_MACHINE', '"thunderx"'],
  94         ['RTE_USE_C11_MEM_MODEL', false]
  95 ]
  96 implementer_cavium = {
  97         'description': 'Cavium',
  98         'flags': [
  99                 ['RTE_MAX_VFIO_GROUPS', 128],
 100                 ['RTE_MAX_LCORE', 96],
 101                 ['RTE_MAX_NUMA_NODES', 2]
 102         ],
 103         'part_number_config': {
 104                 'native': {'machine_args': ['-march=native']},
 105                 '0xa1': {
 106                         'machine_args': ['-mcpu=thunderxt88'],
 107                         'flags': flags_part_number_thunderx
 108                 },
 109                 '0xa2': {
 110                         'machine_args': ['-mcpu=thunderxt81'],
 111                         'flags': flags_part_number_thunderx
 112                 },
 113                 '0xa3': {
 114                         'machine_args': ['-mcpu=thunderxt83'],
 115                         'flags': flags_part_number_thunderx
 116                 },
 117                 '0xaf': {
 118                         'machine_args': ['-march=armv8.1-a+crc+crypto',
 119                                          '-mcpu=thunderx2t99'],
 120                         'flags': [
 121                                 ['RTE_MACHINE', '"thunderx2"'],
 122                                 ['RTE_ARM_FEATURE_ATOMICS', true],
 123                                 ['RTE_USE_C11_MEM_MODEL', true],
 124                                 ['RTE_CACHE_LINE_SIZE', 64],
 125                                 ['RTE_MAX_LCORE', 256],
 126                                 ['RTE_MAX_NUMA_NODES', 2]
 127                         ]
 128                 },
 129                 '0xb2': {
 130                         'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
 131                                          '-mcpu=octeontx2'],
 132                         'flags': [
 133                                 ['RTE_MACHINE', '"octeontx2"'],
 134                                 ['RTE_ARM_FEATURE_ATOMICS', true],
 135                                 ['RTE_USE_C11_MEM_MODEL', true],
 136                                 ['RTE_EAL_IGB_UIO', false],
 137                                 ['RTE_MAX_LCORE', 36],
 138                                 ['RTE_MAX_NUMA_NODES', 1]
 139                         ]
 140                 }
 141         }
 142 }
 143
 144 implementer_ampere = {
 145         'description': 'Ampere Computing',
 146         'flags': [
 147                 ['RTE_MACHINE', '"emag"'],
 148                 ['RTE_CACHE_LINE_SIZE', 64],
 149                 ['RTE_MAX_LCORE', 32],
 150                 ['RTE_MAX_NUMA_NODES', 1]
 151         ],
 152         'part_number_config': {
 153                 '0x0': {'machine_args':  ['-march=armv8-a+crc+crypto',
 154                                           '-mtune=emag']},
 155                 'native': {'machine_args':  ['-march=native']}
 156         }
 157 }
 158
 159 implementer_marvell = {
 160         'description': 'Marvell ARMADA',
 161         'flags': [
 162                 ['RTE_MACHINE', '"armv8a"'],
 163                 ['RTE_CACHE_LINE_SIZE', 64],
 164                 ['RTE_MAX_LCORE', 16],
 165                 ['RTE_MAX_NUMA_NODES', 1]
 166         ],
 167         'part_number_config': part_number_config_arm
 168 }
 169
 170 implementer_dpaa = {
 171         'description': 'NXP DPAA',
 172         'flags': [
 173                 ['RTE_MACHINE', '"dpaa"'],
 174                 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
 175                 ['RTE_USE_C11_MEM_MODEL', true],
 176                 ['RTE_CACHE_LINE_SIZE', 64],
 177                 ['RTE_MAX_LCORE', 16],
 178                 ['RTE_MAX_NUMA_NODES', 1]
 179         ],
 180         'part_number_config': part_number_config_arm
 181 }
 182
 183 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
 184 implementers = {
 185         'generic': implementer_generic,
 186         '0x41': implementer_arm,
 187         '0x43': implementer_cavium,
 188         '0x50': implementer_ampere,
 189         '0x56': implementer_marvell,
 190         'dpaa': implementer_dpaa
 191 }
 192
 193 dpdk_conf.set('RTE_ARCH_ARM', 1)
 194 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
 195
 196 if dpdk_conf.get('RTE_ARCH_32')
 197         # armv7 build
 198         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
 199         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
 200         # the minimum architecture supported, armv7-a, needs the following,
 201         machine_args += '-mfpu=neon'
 202 else
 203         # aarch64 build
 204         if machine == 'default' and not meson.is_cross_build()
 205                 # default build
 206                 implementer_id = 'generic'
 207                 part_number = 'generic'
 208         elif not meson.is_cross_build()
 209                 # native build
 210                 # The script returns ['Implementer', 'Variant', 'Architecture',
 211                 # 'Primary Part number', 'Revision']
 212                 detect_vendor = find_program(join_paths(
 213                                 meson.current_source_dir(), 'armv8_machine.py'))
 214                 cmd = run_command(detect_vendor.path())
 215                 if cmd.returncode() == 0
 216                         cmd_output = cmd.stdout().to_lower().strip().split(' ')
 217                         implementer_id = cmd_output[0]
 218                         part_number = cmd_output[3]
 219                 else
 220                         error('Error when getting Arm Implementer ID and part number.')
 221                 endif
 222                 if arm_force_native_march == true
 223                         part_number = 'native'
 224                 endif
 225         else
 226                 # cross build
 227                 implementer_id = meson.get_cross_property('implementer_id')
 228                 part_number = meson.get_cross_property('part_number')
 229         endif
 230
 231         if implementers.has_key(implementer_id)
 232                 implementer_config = implementers[implementer_id]
 233         else
 234                 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
 235                       'Please add support for it or use the generic ' +
 236                       '(-Dmachine=generic) build.')
 237         endif
 238
 239         message('Arm implementer: ' + implementer_config['description'])
 240         message('Arm part number: ' + part_number)
 241
 242         part_number_config = implementer_config['part_number_config']
 243         if part_number_config.has_key(part_number)
 244                 # use the specified part_number machine args if found
 245                 part_number_config = part_number_config[part_number]
 246         else
 247                 # unknown part number
 248                 error('Unsupported part number @0@ of implementer @1@. '
 249                       .format(part_number, implementer_id) +
 250                       'Please add support for it or use the generic ' +
 251                       '(-Dmachine=generic) build.')
 252         endif
 253
 254         # use default flags with implementer flags
 255         dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', [])
 256
 257         # apply supported machine args
 258         machine_args = [] # Clear previous machine args
 259         foreach flag: part_number_config['machine_args']
 260                 if cc.has_argument(flag)
 261                         machine_args += flag
 262                 endif
 263         endforeach
 264
 265         # apply flags
 266         foreach flag: dpdk_flags
 267                 if flag.length() > 0
 268                         dpdk_conf.set(flag[0], flag[1])
 269                 endif
 270         endforeach
 271 endif
 272 message('Using machine args: @0@'.format(machine_args))
 273
 274 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 275     cc.get_define('__aarch64__', args: machine_args) != '')
 276         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 277 endif
 278
 279 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
 280         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
 281 endif
 282
 283 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
 284         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
 285         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 286 endif