1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific armv8 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific armv8 flags have higher priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
42 'march_features': ['crc'],
43 'compiler_options': ['-moutline-atomics']
47 'compiler_options': ['-mfpu=neon'],
49 ['RTE_ARCH_ARM_NEON_MEMCPY', false],
50 ['RTE_ARCH_STRICT_ALIGN', true],
51 ['RTE_ARCH_ARMv8_AARCH32', true],
52 ['RTE_ARCH', 'armv8_aarch32'],
53 ['RTE_CACHE_LINE_SIZE', 64]
59 part_number_config_arm = {
60 '0xd03': {'compiler_options': ['-mcpu=cortex-a53']},
61 '0xd04': {'compiler_options': ['-mcpu=cortex-a35']},
62 '0xd07': {'compiler_options': ['-mcpu=cortex-a57']},
63 '0xd08': {'compiler_options': ['-mcpu=cortex-a72']},
64 '0xd09': {'compiler_options': ['-mcpu=cortex-a73']},
65 '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']},
66 '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']},
69 'march_features': ['crypto'],
70 'compiler_options': ['-mcpu=neoverse-n1'],
72 ['RTE_MACHINE', '"neoverse-n1"'],
73 ['RTE_ARM_FEATURE_ATOMICS', true],
74 ['RTE_MAX_MEM_MB', 1048576],
75 ['RTE_MAX_LCORE', 160],
76 ['RTE_MAX_NUMA_NODES', 2]
81 'march_features': ['sve2'],
83 ['RTE_MACHINE', '"neoverse-n2"'],
84 ['RTE_ARM_FEATURE_ATOMICS', true],
85 ['RTE_MAX_LCORE', 64],
86 ['RTE_MAX_NUMA_NODES', 1]
93 ['RTE_MACHINE', '"armv8a"'],
94 ['RTE_USE_C11_MEM_MODEL', true],
95 ['RTE_CACHE_LINE_SIZE', 64],
96 ['RTE_MAX_LCORE', 64],
97 ['RTE_MAX_NUMA_NODES', 4]
99 'part_number_config': part_number_config_arm
102 flags_part_number_thunderx = [
103 ['RTE_MACHINE', '"thunderx"'],
104 ['RTE_USE_C11_MEM_MODEL', false]
106 implementer_cavium = {
107 'description': 'Cavium',
109 ['RTE_MAX_VFIO_GROUPS', 128],
110 ['RTE_MAX_LCORE', 96],
111 ['RTE_MAX_NUMA_NODES', 2]
113 'part_number_config': {
115 'compiler_options': ['-mcpu=thunderxt88'],
116 'flags': flags_part_number_thunderx
119 'compiler_options': ['-mcpu=thunderxt81'],
120 'flags': flags_part_number_thunderx
123 'compiler_options': ['-mcpu=thunderxt83'],
124 'flags': flags_part_number_thunderx
127 'march': 'armv8.1-a',
128 'march_features': ['crc', 'crypto'],
129 'compiler_options': ['-mcpu=thunderx2t99'],
131 ['RTE_MACHINE', '"thunderx2"'],
132 ['RTE_ARM_FEATURE_ATOMICS', true],
133 ['RTE_USE_C11_MEM_MODEL', true],
134 ['RTE_CACHE_LINE_SIZE', 64],
135 ['RTE_MAX_LCORE', 256]
139 'march': 'armv8.2-a',
140 'march_features': ['crc', 'crypto', 'lse'],
141 'compiler_options': ['-mcpu=octeontx2'],
143 ['RTE_MACHINE', '"cn9k"'],
144 ['RTE_ARM_FEATURE_ATOMICS', true],
145 ['RTE_USE_C11_MEM_MODEL', true],
146 ['RTE_MAX_LCORE', 36],
147 ['RTE_MAX_NUMA_NODES', 1]
153 implementer_ampere = {
154 'description': 'Ampere Computing',
156 ['RTE_MACHINE', '"emag"'],
157 ['RTE_CACHE_LINE_SIZE', 64],
158 ['RTE_MAX_LCORE', 32],
159 ['RTE_MAX_NUMA_NODES', 1]
161 'part_number_config': {
164 'march_features': ['crc', 'crypto'],
165 'compiler_options': ['-mtune=emag']
170 implementer_hisilicon = {
171 'description': 'HiSilicon',
173 ['RTE_USE_C11_MEM_MODEL', true],
174 ['RTE_CACHE_LINE_SIZE', 128]
176 'part_number_config': {
178 'march': 'armv8.2-a',
179 'march_features': ['crypto'],
180 'compiler_options': ['-mtune=tsv110'],
182 ['RTE_MACHINE', '"Kunpeng 920"'],
183 ['RTE_ARM_FEATURE_ATOMICS', true],
184 ['RTE_MAX_LCORE', 256],
185 ['RTE_MAX_NUMA_NODES', 8]
189 'march': 'armv8.2-a',
190 'march_features': ['crypto', 'sve'],
192 ['RTE_MACHINE', '"Kunpeng 930"'],
193 ['RTE_ARM_FEATURE_ATOMICS', true],
194 ['RTE_MAX_LCORE', 1280],
195 ['RTE_MAX_NUMA_NODES', 16]
201 implementer_qualcomm = {
202 'description': 'Qualcomm',
204 ['RTE_MACHINE', '"armv8a"'],
205 ['RTE_USE_C11_MEM_MODEL', true],
206 ['RTE_CACHE_LINE_SIZE', 64],
207 ['RTE_MAX_LCORE', 64],
208 ['RTE_MAX_NUMA_NODES', 1]
210 'part_number_config': {
213 'march_features': ['crc']
217 'march_features': ['crc']
222 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
224 'generic': implementer_generic,
225 '0x41': implementer_arm,
226 '0x43': implementer_cavium,
227 '0x48': implementer_hisilicon,
228 '0x50': implementer_ampere,
229 '0x51': implementer_qualcomm
232 # SoC specific armv8 flags have the highest priority
233 # (will overwrite all other flags)
235 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
236 'implementer': 'generic',
237 'part_number': 'generic'
240 soc_generic_aarch32 = {
241 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
242 'implementer': 'generic',
243 'part_number': 'generic_aarch32'
247 'description': 'Marvell ARMADA',
248 'implementer': '0x41',
249 'part_number': '0xd08',
251 ['RTE_MAX_LCORE', 16],
252 ['RTE_MAX_NUMA_NODES', 1]
258 'description': 'NVIDIA BlueField',
259 'implementer': '0x41',
260 'part_number': '0xd08',
262 ['RTE_MAX_LCORE', 16],
263 ['RTE_MAX_NUMA_NODES', 1]
269 'description': 'Qualcomm Centriq 2400',
270 'implementer': '0x51',
271 'part_number': '0xc00',
276 'description' : 'Marvell OCTEON 10',
277 'implementer' : '0x41',
279 ['RTE_MAX_LCORE', 24],
280 ['RTE_MAX_NUMA_NODES', 1],
281 ['RTE_MEMPOOL_ALIGN', 128]
283 'part_number': '0xd49',
284 'extra_march_features': ['crypto'],
289 'description': 'NXP DPAA',
290 'implementer': '0x41',
291 'part_number': '0xd08',
293 ['RTE_MACHINE', '"dpaa"'],
294 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
295 ['RTE_MAX_LCORE', 16],
296 ['RTE_MAX_NUMA_NODES', 1]
302 'description': 'Ampere eMAG',
303 'implementer': '0x50',
308 'description': 'AWS Graviton2',
309 'implementer': '0x41',
310 'part_number': '0xd0c',
315 'description': 'HiSilicon Kunpeng 920',
316 'implementer': '0x48',
317 'part_number': '0xd01',
322 'description': 'HiSilicon Kunpeng 930',
323 'implementer': '0x48',
324 'part_number': '0xd02',
329 'description': 'Arm Neoverse N1SDP',
330 'implementer': '0x41',
331 'part_number': '0xd0c',
339 'description': 'Arm Neoverse N2',
340 'implementer': '0x41',
341 'part_number': '0xd49',
346 'description': 'Marvell OCTEON 9',
347 'implementer': '0x43',
348 'part_number': '0xb2',
353 'description': 'Broadcom Stingray',
354 'implementer': '0x41',
356 ['RTE_MAX_LCORE', 16],
357 ['RTE_MAX_NUMA_NODES', 1]
359 'part_number': '0xd08',
364 'description': 'Marvell ThunderX2 T99',
365 'implementer': '0x43',
366 'part_number': '0xaf'
370 'description': 'Marvell ThunderX T88',
371 'implementer': '0x43',
372 'part_number': '0xa1'
377 generic: Generic un-optimized build for armv8 aarch64 execution mode.
378 generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.
379 armada: Marvell ARMADA
380 bluefield: NVIDIA BlueField
381 centriq2400: Qualcomm Centriq 2400
382 cn9k: Marvell OCTEON 9
383 cn10k: Marvell OCTEON 10
386 graviton2: AWS Graviton2
387 kunpeng920: HiSilicon Kunpeng 920
388 kunpeng930: HiSilicon Kunpeng 930
389 n1sdp: Arm Neoverse N1SDP
391 stingray: Broadcom Stingray
392 thunderx2: Marvell ThunderX2 T99
393 thunderxt88: Marvell ThunderX T88
396 # The string above is included in the documentation, keep it in sync with the
399 'generic': soc_generic,
400 'generic_aarch32': soc_generic_aarch32,
401 'armada': soc_armada,
402 'bluefield': soc_bluefield,
403 'centriq2400': soc_centriq2400,
408 'graviton2': soc_graviton2,
409 'kunpeng920': soc_kunpeng920,
410 'kunpeng930': soc_kunpeng930,
413 'stingray': soc_stingray,
414 'thunderx2': soc_thunderx2,
415 'thunderxt88': soc_thunderxt88
418 dpdk_conf.set('RTE_ARCH_ARM', 1)
419 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
423 if dpdk_conf.get('RTE_ARCH_32')
425 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
426 if meson.is_cross_build()
428 soc = meson.get_cross_property('platform', '')
430 error('Arm SoC must be specified in the cross file.')
432 soc_config = socs.get(soc, {'not_supported': true})
436 dpdk_conf.set('RTE_ARCH_ARMv7', true)
437 dpdk_conf.set('RTE_ARCH', 'armv7')
438 dpdk_conf.set('RTE_MAX_LCORE', 128)
439 dpdk_conf.set('RTE_MAX_NUMA_NODES', 1)
440 # the minimum architecture supported, armv7-a, needs the following,
441 machine_args += '-mfpu=neon'
445 dpdk_conf.set('RTE_ARCH', 'armv8')
448 if not meson.is_cross_build()
449 # for backwards compatibility:
450 # machine=native is the same behavior as soc=native
451 # machine=generic/default is the same as soc=generic
452 # cpu_instruction_set holds the proper value - native, generic or cpu
453 # the old behavior only distinguished between generic and native build
455 if cpu_instruction_set == 'generic'
465 # The script returns ['Implementer', 'Variant', 'Architecture',
466 # 'Primary Part number', 'Revision']
467 detect_vendor = find_program(join_paths(meson.current_source_dir(),
469 cmd = run_command(detect_vendor.path(), check: false)
470 if cmd.returncode() == 0
471 cmd_output = cmd.stdout().to_lower().strip().split(' ')
472 implementer_id = cmd_output[0]
473 part_number = cmd_output[3]
475 error('Error when getting Arm Implementer ID and part number.')
479 soc_config = socs.get(soc, {'not_supported': true})
483 soc = meson.get_cross_property('platform', '')
485 error('Arm SoC must be specified in the cross file.')
487 soc_config = socs.get(soc, {'not_supported': true})
492 if soc_config.has_key('not_supported')
493 error('SoC @0@ not supported.'.format(soc))
494 elif soc_config != {}
495 implementer_id = soc_config['implementer']
496 implementer_config = implementers[implementer_id]
497 part_number = soc_config['part_number']
498 soc_flags = soc_config.get('flags', [])
499 if not soc_config.get('numa', true)
503 disable_drivers += ',' + soc_config.get('disable_drivers', '')
504 enable_drivers += ',' + soc_config.get('enable_drivers', '')
507 if implementers.has_key(implementer_id)
508 implementer_config = implementers[implementer_id]
510 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
511 'Please add support for it or use the generic ' +
512 '(-Dplatform=generic) build.')
515 message('Arm implementer: ' + implementer_config['description'])
516 message('Arm part number: ' + part_number)
518 part_number_config = implementer_config['part_number_config']
519 if part_number_config.has_key(part_number)
520 # use the specified part_number machine args if found
521 part_number_config = part_number_config[part_number]
523 # unknown part number
524 error('Unsupported part number @0@ of implementer @1@. '
525 .format(part_number, implementer_id) +
526 'Please add support for it or use the generic ' +
527 '(-Dplatform=generic) build.')
530 # add/overwrite flags in the proper order
531 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
533 machine_args = [] # Clear previous machine args
535 # probe supported archs and their features
537 if part_number_config.has_key('march')
538 supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a',
539 'armv8.2-a', 'armv8.1-a', 'armv8-a']
540 check_compiler_support = false
541 foreach supported_march: supported_marchs
542 if supported_march == part_number_config['march']
543 # start checking from this version downwards
544 check_compiler_support = true
546 if (check_compiler_support and
547 cc.has_argument('-march=' + supported_march))
548 candidate_march = supported_march
549 # highest supported march version found
553 if candidate_march == ''
554 error('No suitable armv8 march version found.')
556 if candidate_march != part_number_config['march']
557 warning('Configuration march version is ' +
558 '@0@, but the compiler supports only @1@.'
559 .format(part_number_config['march'], candidate_march))
561 candidate_march = '-march=' + candidate_march
564 if part_number_config.has_key('march_features')
565 march_features += part_number_config['march_features']
567 if soc_config.has_key('extra_march_features')
568 march_features += soc_config['extra_march_features']
570 foreach feature: march_features
571 if cc.has_argument('+'.join([candidate_march, feature]))
572 candidate_march = '+'.join([candidate_march, feature])
574 warning('The compiler does not support feature @0@'
578 machine_args += candidate_march
581 # apply supported compiler options
582 if part_number_config.has_key('compiler_options')
583 foreach flag: part_number_config['compiler_options']
584 if cc.has_argument(flag)
587 warning('Configuration compiler option ' +
588 '@0@ isn\'t supported.'.format(flag))
594 foreach flag: dpdk_flags
596 dpdk_conf.set(flag[0], flag[1])
600 message('Using machine args: @0@'.format(machine_args))
602 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
603 cc.get_define('__aarch64__', args: machine_args) != '')
604 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
607 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
608 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
609 if (cc.check_header('arm_sve.h'))
610 dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
614 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
615 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
618 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
619 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
620 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']