1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific armv8 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific armv8 flags have higher priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
42 'march_features': ['crc'],
43 'compiler_options': ['-moutline-atomics']
47 'compiler_options': ['-mfpu=neon'],
49 ['RTE_ARCH_ARM_NEON_MEMCPY', false],
50 ['RTE_ARCH_STRICT_ALIGN', true],
51 ['RTE_ARCH_ARMv8_AARCH32', true],
52 ['RTE_ARCH', 'armv8_aarch32'],
53 ['RTE_CACHE_LINE_SIZE', 64]
59 part_number_config_arm = {
60 '0xd03': {'compiler_options': ['-mcpu=cortex-a53']},
61 '0xd04': {'compiler_options': ['-mcpu=cortex-a35']},
62 '0xd07': {'compiler_options': ['-mcpu=cortex-a57']},
63 '0xd08': {'compiler_options': ['-mcpu=cortex-a72']},
64 '0xd09': {'compiler_options': ['-mcpu=cortex-a73']},
65 '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']},
66 '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']},
69 'march_features': ['crypto'],
70 'compiler_options': ['-mcpu=neoverse-n1'],
72 ['RTE_MACHINE', '"neoverse-n1"'],
73 ['RTE_ARM_FEATURE_ATOMICS', true],
74 ['RTE_MAX_MEM_MB', 1048576],
75 ['RTE_MAX_LCORE', 160],
76 ['RTE_MAX_NUMA_NODES', 2]
81 'march_features': ['sve2'],
83 ['RTE_MACHINE', '"neoverse-n2"'],
84 ['RTE_ARM_FEATURE_ATOMICS', true],
85 ['RTE_MAX_LCORE', 64],
86 ['RTE_MAX_NUMA_NODES', 1]
93 ['RTE_MACHINE', '"armv8a"'],
94 ['RTE_USE_C11_MEM_MODEL', true],
95 ['RTE_CACHE_LINE_SIZE', 64],
96 ['RTE_MAX_LCORE', 64],
97 ['RTE_MAX_NUMA_NODES', 4]
99 'part_number_config': part_number_config_arm
102 flags_part_number_thunderx = [
103 ['RTE_MACHINE', '"thunderx"'],
104 ['RTE_USE_C11_MEM_MODEL', false]
106 implementer_cavium = {
107 'description': 'Cavium',
109 ['RTE_MAX_VFIO_GROUPS', 128],
110 ['RTE_MAX_LCORE', 96],
111 ['RTE_MAX_NUMA_NODES', 2]
113 'part_number_config': {
115 'compiler_options': ['-mcpu=thunderxt88'],
116 'flags': flags_part_number_thunderx
119 'compiler_options': ['-mcpu=thunderxt81'],
120 'flags': flags_part_number_thunderx
123 'compiler_options': ['-mcpu=thunderxt83'],
124 'flags': flags_part_number_thunderx
127 'march': 'armv8.1-a',
128 'march_features': ['crc', 'crypto'],
129 'compiler_options': ['-mcpu=thunderx2t99'],
131 ['RTE_MACHINE', '"thunderx2"'],
132 ['RTE_ARM_FEATURE_ATOMICS', true],
133 ['RTE_USE_C11_MEM_MODEL', true],
134 ['RTE_CACHE_LINE_SIZE', 64],
135 ['RTE_MAX_LCORE', 256]
139 'march': 'armv8.2-a',
140 'march_features': ['crc', 'crypto', 'lse'],
141 'compiler_options': ['-mcpu=octeontx2'],
143 ['RTE_MACHINE', '"cn9k"'],
144 ['RTE_ARM_FEATURE_ATOMICS', true],
145 ['RTE_USE_C11_MEM_MODEL', true],
146 ['RTE_MAX_LCORE', 36],
147 ['RTE_MAX_NUMA_NODES', 1]
153 implementer_ampere = {
154 'description': 'Ampere Computing',
156 ['RTE_MACHINE', '"emag"'],
157 ['RTE_CACHE_LINE_SIZE', 64],
158 ['RTE_MAX_LCORE', 32],
159 ['RTE_MAX_NUMA_NODES', 1]
161 'part_number_config': {
164 'march_features': ['crc', 'crypto'],
165 'compiler_options': ['-mtune=emag']
170 implementer_hisilicon = {
171 'description': 'HiSilicon',
173 ['RTE_USE_C11_MEM_MODEL', true],
174 ['RTE_CACHE_LINE_SIZE', 128]
176 'part_number_config': {
178 'march': 'armv8.2-a',
179 'march_features': ['crypto'],
180 'compiler_options': ['-mtune=tsv110'],
182 ['RTE_MACHINE', '"Kunpeng 920"'],
183 ['RTE_ARM_FEATURE_ATOMICS', true],
184 ['RTE_MAX_LCORE', 256],
185 ['RTE_MAX_NUMA_NODES', 8]
189 'march': 'armv8.2-a',
190 'march_features': ['crypto', 'sve'],
192 ['RTE_MACHINE', '"Kunpeng 930"'],
193 ['RTE_ARM_FEATURE_ATOMICS', true],
194 ['RTE_MAX_LCORE', 1280],
195 ['RTE_MAX_NUMA_NODES', 16]
201 implementer_qualcomm = {
202 'description': 'Qualcomm',
204 ['RTE_MACHINE', '"armv8a"'],
205 ['RTE_USE_C11_MEM_MODEL', true],
206 ['RTE_CACHE_LINE_SIZE', 64],
207 ['RTE_MAX_LCORE', 64],
208 ['RTE_MAX_NUMA_NODES', 1]
210 'part_number_config': {
213 'march_features': ['crc']
217 'march_features': ['crc']
222 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
224 'generic': implementer_generic,
225 '0x41': implementer_arm,
226 '0x43': implementer_cavium,
227 '0x48': implementer_hisilicon,
228 '0x50': implementer_ampere,
229 '0x51': implementer_qualcomm
232 # SoC specific armv8 flags have the highest priority
233 # (will overwrite all other flags)
235 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
236 'implementer': 'generic',
237 'part_number': 'generic'
240 soc_generic_aarch32 = {
241 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
242 'implementer': 'generic',
243 'part_number': 'generic_aarch32'
247 'description': 'Marvell ARMADA',
248 'implementer': '0x41',
249 'part_number': '0xd08',
251 ['RTE_MAX_LCORE', 16],
252 ['RTE_MAX_NUMA_NODES', 1]
258 'description': 'NVIDIA BlueField',
259 'implementer': '0x41',
260 'part_number': '0xd08',
262 ['RTE_MAX_LCORE', 16],
263 ['RTE_MAX_NUMA_NODES', 1]
269 'description': 'Qualcomm Centriq 2400',
270 'implementer': '0x51',
271 'part_number': '0xc00',
276 'description' : 'Marvell OCTEON 10',
277 'implementer' : '0x41',
279 ['RTE_MAX_LCORE', 24],
280 ['RTE_MAX_NUMA_NODES', 1]
282 'part_number': '0xd49',
283 'extra_march_features': ['crypto'],
288 'description': 'NXP DPAA',
289 'implementer': '0x41',
290 'part_number': '0xd08',
292 ['RTE_MACHINE', '"dpaa"'],
293 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
294 ['RTE_MAX_LCORE', 16],
295 ['RTE_MAX_NUMA_NODES', 1]
301 'description': 'Ampere eMAG',
302 'implementer': '0x50',
307 'description': 'AWS Graviton2',
308 'implementer': '0x41',
309 'part_number': '0xd0c',
314 'description': 'HiSilicon Kunpeng 920',
315 'implementer': '0x48',
316 'part_number': '0xd01',
321 'description': 'HiSilicon Kunpeng 930',
322 'implementer': '0x48',
323 'part_number': '0xd02',
328 'description': 'Arm Neoverse N1SDP',
329 'implementer': '0x41',
330 'part_number': '0xd0c',
338 'description': 'Arm Neoverse N2',
339 'implementer': '0x41',
340 'part_number': '0xd49',
345 'description': 'Marvell OCTEON 9',
346 'implementer': '0x43',
347 'part_number': '0xb2',
352 'description': 'Broadcom Stingray',
353 'implementer': '0x41',
355 ['RTE_MAX_LCORE', 16],
356 ['RTE_MAX_NUMA_NODES', 1]
358 'part_number': '0xd08',
363 'description': 'Marvell ThunderX2 T99',
364 'implementer': '0x43',
365 'part_number': '0xaf'
369 'description': 'Marvell ThunderX T88',
370 'implementer': '0x43',
371 'part_number': '0xa1'
376 generic: Generic un-optimized build for armv8 aarch64 execution mode.
377 generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.
378 armada: Marvell ARMADA
379 bluefield: NVIDIA BlueField
380 centriq2400: Qualcomm Centriq 2400
381 cn9k: Marvell OCTEON 9
382 cn10k: Marvell OCTEON 10
385 graviton2: AWS Graviton2
386 kunpeng920: HiSilicon Kunpeng 920
387 kunpeng930: HiSilicon Kunpeng 930
388 n1sdp: Arm Neoverse N1SDP
390 stingray: Broadcom Stingray
391 thunderx2: Marvell ThunderX2 T99
392 thunderxt88: Marvell ThunderX T88
395 # The string above is included in the documentation, keep it in sync with the
398 'generic': soc_generic,
399 'generic_aarch32': soc_generic_aarch32,
400 'armada': soc_armada,
401 'bluefield': soc_bluefield,
402 'centriq2400': soc_centriq2400,
407 'graviton2': soc_graviton2,
408 'kunpeng920': soc_kunpeng920,
409 'kunpeng930': soc_kunpeng930,
412 'stingray': soc_stingray,
413 'thunderx2': soc_thunderx2,
414 'thunderxt88': soc_thunderxt88
417 dpdk_conf.set('RTE_ARCH_ARM', 1)
418 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
422 if dpdk_conf.get('RTE_ARCH_32')
424 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
425 if meson.is_cross_build()
427 soc = meson.get_cross_property('platform', '')
429 error('Arm SoC must be specified in the cross file.')
431 soc_config = socs.get(soc, {'not_supported': true})
435 dpdk_conf.set('RTE_ARCH_ARMv7', true)
436 dpdk_conf.set('RTE_ARCH', 'armv7')
437 dpdk_conf.set('RTE_MAX_LCORE', 128)
438 dpdk_conf.set('RTE_MAX_NUMA_NODES', 1)
439 # the minimum architecture supported, armv7-a, needs the following,
440 machine_args += '-mfpu=neon'
444 dpdk_conf.set('RTE_ARCH', 'armv8')
447 if not meson.is_cross_build()
448 # for backwards compatibility:
449 # machine=native is the same behavior as soc=native
450 # machine=generic/default is the same as soc=generic
451 # cpu_instruction_set holds the proper value - native, generic or cpu
452 # the old behavior only distinguished between generic and native build
454 if cpu_instruction_set == 'generic'
464 # The script returns ['Implementer', 'Variant', 'Architecture',
465 # 'Primary Part number', 'Revision']
466 detect_vendor = find_program(join_paths(meson.current_source_dir(),
468 cmd = run_command(detect_vendor.path(), check: false)
469 if cmd.returncode() == 0
470 cmd_output = cmd.stdout().to_lower().strip().split(' ')
471 implementer_id = cmd_output[0]
472 part_number = cmd_output[3]
474 error('Error when getting Arm Implementer ID and part number.')
478 soc_config = socs.get(soc, {'not_supported': true})
482 soc = meson.get_cross_property('platform', '')
484 error('Arm SoC must be specified in the cross file.')
486 soc_config = socs.get(soc, {'not_supported': true})
491 if soc_config.has_key('not_supported')
492 error('SoC @0@ not supported.'.format(soc))
493 elif soc_config != {}
494 implementer_id = soc_config['implementer']
495 implementer_config = implementers[implementer_id]
496 part_number = soc_config['part_number']
497 soc_flags = soc_config.get('flags', [])
498 if not soc_config.get('numa', true)
502 disable_drivers += ',' + soc_config.get('disable_drivers', '')
503 enable_drivers += ',' + soc_config.get('enable_drivers', '')
506 if implementers.has_key(implementer_id)
507 implementer_config = implementers[implementer_id]
509 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
510 'Please add support for it or use the generic ' +
511 '(-Dplatform=generic) build.')
514 message('Arm implementer: ' + implementer_config['description'])
515 message('Arm part number: ' + part_number)
517 part_number_config = implementer_config['part_number_config']
518 if part_number_config.has_key(part_number)
519 # use the specified part_number machine args if found
520 part_number_config = part_number_config[part_number]
522 # unknown part number
523 error('Unsupported part number @0@ of implementer @1@. '
524 .format(part_number, implementer_id) +
525 'Please add support for it or use the generic ' +
526 '(-Dplatform=generic) build.')
529 # add/overwrite flags in the proper order
530 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
532 machine_args = [] # Clear previous machine args
534 # probe supported archs and their features
536 if part_number_config.has_key('march')
537 supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a',
538 'armv8.2-a', 'armv8.1-a', 'armv8-a']
539 check_compiler_support = false
540 foreach supported_march: supported_marchs
541 if supported_march == part_number_config['march']
542 # start checking from this version downwards
543 check_compiler_support = true
545 if (check_compiler_support and
546 cc.has_argument('-march=' + supported_march))
547 candidate_march = supported_march
548 # highest supported march version found
552 if candidate_march == ''
553 error('No suitable armv8 march version found.')
555 if candidate_march != part_number_config['march']
556 warning('Configuration march version is ' +
557 '@0@, but the compiler supports only @1@.'
558 .format(part_number_config['march'], candidate_march))
560 candidate_march = '-march=' + candidate_march
563 if part_number_config.has_key('march_features')
564 march_features += part_number_config['march_features']
566 if soc_config.has_key('extra_march_features')
567 march_features += soc_config['extra_march_features']
569 foreach feature: march_features
570 if cc.has_argument('+'.join([candidate_march, feature]))
571 candidate_march = '+'.join([candidate_march, feature])
573 warning('The compiler does not support feature @0@'
577 machine_args += candidate_march
580 # apply supported compiler options
581 if part_number_config.has_key('compiler_options')
582 foreach flag: part_number_config['compiler_options']
583 if cc.has_argument(flag)
586 warning('Configuration compiler option ' +
587 '@0@ isn\'t supported.'.format(flag))
593 foreach flag: dpdk_flags
595 dpdk_conf.set(flag[0], flag[1])
599 message('Using machine args: @0@'.format(machine_args))
601 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
602 cc.get_define('__aarch64__', args: machine_args) != '')
603 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
606 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
607 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
608 if (cc.check_header('arm_sve.h'))
609 dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
613 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
614 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
617 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
618 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
619 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']