3 # Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 # Copyright (c) 2016 NXP. All rights reserved.
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions
10 # * Redistributions of source code must retain the above copyright
11 # notice, this list of conditions and the following disclaimer.
12 # * Redistributions in binary form must reproduce the above copyright
13 # notice, this list of conditions and the following disclaimer in
14 # the documentation and/or other materials provided with the
16 # * Neither the name of Freescale Semiconductor nor the names of its
17 # contributors may be used to endorse or promote products derived
18 # from this software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "defconfig_arm64-armv8a-linuxapp-gcc"
35 # NXP (Freescale) - Soc Architecture with WRIOP and QBMAN support
36 CONFIG_RTE_MACHINE="dpaa2"
37 CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72"
40 # Compile Environment Abstraction Layer
42 CONFIG_RTE_MAX_LCORE=8
43 CONFIG_RTE_MAX_NUMA_NODES=1
44 CONFIG_RTE_CACHE_LINE_SIZE=64
46 CONFIG_RTE_PKTMBUF_HEADROOM=256
48 # Doesn't support NUMA
49 CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
50 CONFIG_RTE_LIBRTE_VHOST_NUMA=n
53 # Compile Support Libraries for DPAA2
55 CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
56 CONFIG_RTE_MBUF_DEFAULT_MEMPOOL_OPS="dpaa2"
57 CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=y
60 # Compile NXP DPAA2 FSL-MC Bus
62 CONFIG_RTE_LIBRTE_FSLMC_BUS=y
65 # Compile burst-oriented NXP DPAA2 PMD driver
67 CONFIG_RTE_LIBRTE_DPAA2_PMD=y
68 CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT=n
69 CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n
70 CONFIG_RTE_LIBRTE_DPAA2_DEBUG_RX=n
71 CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX=n
72 CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX_FREE=n
75 # Compile NXP DPAA2 crypto sec driver for CAAM HW
77 CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
78 CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n
79 CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n
80 CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n
83 # Number of sessions to create in the session memory pool
84 # on a single DPAA2 SEC device.
86 CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048