1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
6 * @file Header file containing DPDK compilation parameters
8 * Header file containing DPDK compilation parameters. Also include the
9 * meson-generated header file containing the detected parameters that
10 * are variable across builds or build environments.
12 * NOTE: This file is only used for meson+ninja builds. For builds done
13 * using make/gmake, the rte_config.h file is autogenerated from the
14 * defconfig_* files in the config directory.
16 #ifndef _RTE_CONFIG_H_
17 #define _RTE_CONFIG_H_
19 #include <rte_build_config.h>
21 /****** library defines ********/
24 #define RTE_BUILD_SHARED_LIB
27 #define RTE_MAX_HEAPS 32
28 #define RTE_MAX_MEMSEG_LISTS 128
29 #define RTE_MAX_MEMSEG_PER_LIST 8192
30 #define RTE_MAX_MEM_MB_PER_LIST 32768
31 #define RTE_MAX_MEMSEG_PER_TYPE 32768
32 #define RTE_MAX_MEM_MB_PER_TYPE 65536
33 #define RTE_MAX_MEM_MB 524288
34 #define RTE_MAX_MEMZONE 2560
35 #define RTE_MAX_TAILQ 32
36 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO
37 #define RTE_BACKTRACE 1
38 #define RTE_MAX_VFIO_CONTAINERS 64
40 /* bsd module defines */
41 #define RTE_CONTIGMEM_MAX_NUM_BUFS 64
42 #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1
43 #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)
46 #define RTE_MEMPOOL_CACHE_MAX_SIZE 512
49 #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
50 #define RTE_MBUF_REFCNT_ATOMIC 1
51 #define RTE_PKTMBUF_HEADROOM 128
54 #define RTE_MAX_QUEUES_PER_PORT 1024
55 #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16
56 #define RTE_ETHDEV_RXTX_CALLBACKS 1
58 /* cryptodev defines */
59 #define RTE_CRYPTO_MAX_DEVS 64
60 #define RTE_CRYPTODEV_NAME_LEN 64
62 /* compressdev defines */
63 #define RTE_COMPRESS_MAX_DEVS 64
65 /* eventdev defines */
66 #define RTE_EVENT_MAX_DEVS 16
67 #define RTE_EVENT_MAX_QUEUES_PER_DEV 64
68 #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32
69 #define RTE_EVENT_ETH_INTR_RING_SIZE 1024
70 #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32
71 #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32
74 #define RTE_RAWDEV_MAX_DEVS 10
76 /* ip_fragmentation defines */
77 #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
78 #undef RTE_LIBRTE_IP_FRAG_TBL_STAT
80 /* rte_power defines */
81 #define RTE_MAX_LCORE_FREQS 64
83 /* rte_sched defines */
85 #undef RTE_SCHED_COLLECT_STATS
86 #undef RTE_SCHED_SUBPORT_TC_OV
87 #define RTE_SCHED_PORT_N_GRINDERS 8
88 #undef RTE_SCHED_VECTOR
90 /****** driver defines ********/
92 /* QuickAssist device */
93 /* Max. number of QuickAssist devices which can be attached */
94 #define RTE_PMD_QAT_MAX_PCI_DEVICES 48
95 #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
96 #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
98 /* virtio crypto defines */
99 #define RTE_MAX_VIRTIO_CRYPTO 32
101 /* DPAA SEC max cryptodev devices*/
102 #define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
105 #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
108 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
109 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
110 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64
111 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
112 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4
114 /* Ring net PMD settings */
115 #define RTE_PMD_RING_MAX_RX_RINGS 16
116 #define RTE_PMD_RING_MAX_TX_RINGS 16
118 /* QEDE PMD defines */
119 #define RTE_LIBRTE_QEDE_FW ""
121 #endif /* _RTE_CONFIG_H_ */