1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
6 * @file Header file containing DPDK compilation parameters
8 * Header file containing DPDK compilation parameters. Also include the
9 * meson-generated header file containing the detected parameters that
10 * are variable across builds or build environments.
12 * NOTE: This file is only used for meson+ninja builds. For builds done
13 * using make/gmake, the rte_config.h file is autogenerated from the
14 * defconfig_* files in the config directory.
16 #ifndef _RTE_CONFIG_H_
17 #define _RTE_CONFIG_H_
19 #include <rte_build_config.h>
22 #ifdef RTE_EXEC_ENV_LINUX
23 #define RTE_EXEC_ENV_LINUXAPP 1
26 /****** library defines ********/
29 #define RTE_BUILD_SHARED_LIB
32 #define RTE_MAX_HEAPS 32
33 #define RTE_MAX_MEMSEG_LISTS 128
34 #define RTE_MAX_MEMSEG_PER_LIST 8192
35 #define RTE_MAX_MEM_MB_PER_LIST 32768
36 #define RTE_MAX_MEMSEG_PER_TYPE 32768
37 #define RTE_MAX_MEM_MB_PER_TYPE 65536
38 #define RTE_MAX_MEM_MB 524288
39 #define RTE_MAX_MEMZONE 2560
40 #define RTE_MAX_TAILQ 32
41 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO
42 #define RTE_BACKTRACE 1
43 #define RTE_MAX_VFIO_CONTAINERS 64
45 /* bsd module defines */
46 #define RTE_CONTIGMEM_MAX_NUM_BUFS 64
47 #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1
48 #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)
51 #define RTE_MEMPOOL_CACHE_MAX_SIZE 512
54 #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
55 #define RTE_MBUF_REFCNT_ATOMIC 1
56 #define RTE_PKTMBUF_HEADROOM 128
59 #define RTE_MAX_QUEUES_PER_PORT 1024
60 #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16
61 #define RTE_ETHDEV_RXTX_CALLBACKS 1
63 /* cryptodev defines */
64 #define RTE_CRYPTO_MAX_DEVS 64
65 #define RTE_CRYPTODEV_NAME_LEN 64
67 /* compressdev defines */
68 #define RTE_COMPRESS_MAX_DEVS 64
70 /* eventdev defines */
71 #define RTE_EVENT_MAX_DEVS 16
72 #define RTE_EVENT_MAX_QUEUES_PER_DEV 64
73 #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32
74 #define RTE_EVENT_ETH_INTR_RING_SIZE 1024
75 #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32
76 #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32
79 #define RTE_RAWDEV_MAX_DEVS 10
81 /* ip_fragmentation defines */
82 #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
83 #undef RTE_LIBRTE_IP_FRAG_TBL_STAT
85 /* rte_power defines */
86 #define RTE_MAX_LCORE_FREQS 64
88 /* rte_sched defines */
90 #undef RTE_SCHED_COLLECT_STATS
91 #undef RTE_SCHED_SUBPORT_TC_OV
92 #define RTE_SCHED_PORT_N_GRINDERS 8
93 #undef RTE_SCHED_VECTOR
95 /****** driver defines ********/
97 /* QuickAssist device */
98 /* Max. number of QuickAssist devices which can be attached */
99 #define RTE_PMD_QAT_MAX_PCI_DEVICES 48
100 #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
101 #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
103 /* virtio crypto defines */
104 #define RTE_MAX_VIRTIO_CRYPTO 32
106 /* DPAA SEC max cryptodev devices*/
107 #define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
110 #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
113 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
114 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
115 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64
116 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
117 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4
119 /* Ring net PMD settings */
120 #define RTE_PMD_RING_MAX_RX_RINGS 16
121 #define RTE_PMD_RING_MAX_TX_RINGS 16
123 /* QEDE PMD defines */
124 #define RTE_LIBRTE_QEDE_FW ""
126 #endif /* _RTE_CONFIG_H_ */