1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
6 * @file Header file containing DPDK compilation parameters
8 * Header file containing DPDK compilation parameters. Also include the
9 * meson-generated header file containing the detected parameters that
10 * are variable across builds or build environments.
12 * NOTE: This file is only used for meson+ninja builds. For builds done
13 * using make/gmake, the rte_config.h file is autogenerated from the
14 * defconfig_* files in the config directory.
16 #ifndef _RTE_CONFIG_H_
17 #define _RTE_CONFIG_H_
19 #include <rte_build_config.h>
21 /****** library defines ********/
24 #define RTE_MAX_MEMSEG_LISTS 128
25 #define RTE_MAX_MEMSEG_PER_LIST 8192
26 #define RTE_MAX_MEM_MB_PER_LIST 32768
27 #define RTE_MAX_MEMSEG_PER_TYPE 32768
28 #define RTE_MAX_MEM_MB_PER_TYPE 65536
29 #define RTE_MAX_MEM_MB 524288
30 #define RTE_MAX_MEMZONE 2560
31 #define RTE_MAX_TAILQ 32
32 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO
33 #define RTE_BACKTRACE 1
34 #define RTE_EAL_VFIO 1
36 /* bsd module defines */
37 #define RTE_CONTIGMEM_MAX_NUM_BUFS 64
38 #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1
39 #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)
42 #define RTE_MEMPOOL_CACHE_MAX_SIZE 512
45 #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
46 #define RTE_MBUF_REFCNT_ATOMIC 1
47 #define RTE_PKTMBUF_HEADROOM 128
50 #define RTE_MAX_ETHPORTS 32
51 #define RTE_MAX_QUEUES_PER_PORT 1024
52 #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16
53 #define RTE_ETHDEV_RXTX_CALLBACKS 1
55 /* cryptodev defines */
56 #define RTE_CRYPTO_MAX_DEVS 64
57 #define RTE_CRYPTODEV_NAME_LEN 64
59 /* eventdev defines */
60 #define RTE_EVENT_MAX_DEVS 16
61 #define RTE_EVENT_MAX_QUEUES_PER_DEV 64
63 /* ip_fragmentation defines */
64 #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
65 #undef RTE_LIBRTE_IP_FRAG_TBL_STAT
67 /* rte_power defines */
68 #define RTE_MAX_LCORE_FREQS 64
70 /* rte_sched defines */
72 #undef RTE_SCHED_COLLECT_STATS
73 #undef RTE_SCHED_SUBPORT_TC_OV
74 #define RTE_SCHED_PORT_N_GRINDERS 8
75 #undef RTE_SCHED_VECTOR
77 /****** driver defines ********/
80 * Number of sessions to create in the session memory pool
81 * on a single instance of crypto HW device.
83 /* QuickAssist device */
84 #define RTE_QAT_PMD_MAX_NB_SESSIONS 2048
87 #define RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS 2048
90 #define RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS 2048
92 /* DPAA SEC max cryptodev devices*/
93 #define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
96 #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
99 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
100 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
101 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64
102 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
103 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4
104 /* interval up to 8160 us, aligned to 2 (or default value) */
105 #define RTE_LIBRTE_I40E_ITR_INTERVAL -1
107 /* Ring net PMD settings */
108 #define RTE_PMD_RING_MAX_RX_RINGS 16
109 #define RTE_PMD_RING_MAX_TX_RINGS 16
111 #endif /* _RTE_CONFIG_H_ */