3 # Copyright(c) 2017 Intel Corporation.
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions
10 # * Redistributions of source code must retain the above copyright
11 # notice, this list of conditions and the following disclaimer.
12 # * Redistributions in binary form must reproduce the above copyright
13 # notice, this list of conditions and the following disclaimer in
14 # the documentation and/or other materials provided with the
16 # * Neither the name of Intel Corporation nor the names of its
17 # contributors may be used to endorse or promote products derived
18 # from this software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 # for checking defines we need to use the correct compiler flags
33 march_opt = '-march=@0@'.format(machine)
35 # we require SSE4.2 for DPDK
36 sse_errormsg = '''SSE4.2 instruction set is required for DPDK.
37 Please set the machine type to "nehalem" or "corei7" or higher value'''
39 if cc.get_define('__SSE4_2__', args: march_opt) == ''
43 base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2']
45 dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1)
46 compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
49 dpdk_conf.set('RTE_ARCH_X86', 1)
50 if (host_machine.cpu_family() == 'x86_64')
51 dpdk_conf.set('RTE_ARCH_X86_64', 1)
52 dpdk_conf.set('RTE_ARCH', 'x86_64')
53 dpdk_conf.set('RTE_ARCH_64', 1)
55 dpdk_conf.set('RTE_ARCH_I686', 1)
56 dpdk_conf.set('RTE_ARCH', 'i686')
59 if cc.get_define('__AES__', args: march_opt) != ''
60 dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
61 compile_time_cpuflags += ['RTE_CPUFLAG_AES']
63 if cc.get_define('__PCLMUL__', args: march_opt) != ''
64 dpdk_conf.set('RTE_MACHINE_CPUFLAG_PCLMULQDQ', 1)
65 compile_time_cpuflags += ['RTE_CPUFLAG_PCLMULQDQ']
67 if cc.get_define('__AVX__', args: march_opt) != ''
68 dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX', 1)
69 compile_time_cpuflags += ['RTE_CPUFLAG_AVX']
71 if cc.get_define('__AVX2__', args: march_opt) != ''
72 dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1)
73 compile_time_cpuflags += ['RTE_CPUFLAG_AVX2']
75 if cc.get_define('__AVX512F__', args: march_opt) != ''
76 dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1)
77 compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F']
80 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)