4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include <rte_byteorder.h>
56 #include "t4_regs_values.h"
57 #include "t4fw_interface.h"
59 static void init_link_config(struct link_config *lc, unsigned int pcaps,
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
68 * Reads the HW path MTU table.
70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
75 for (i = 0; i < NMTUS; ++i) {
76 t4_write_reg(adap, A_TP_MTU_TABLE,
77 V_MTUINDEX(0xff) | V_MTUVALUE(i));
78 v = t4_read_reg(adap, A_TP_MTU_TABLE);
79 mtus[i] = G_MTUVALUE(v);
81 mtu_log[i] = G_MTUWIDTH(v);
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
92 * Sets a field of an indirect TP register to the given value.
94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95 unsigned int mask, unsigned int val)
97 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99 t4_write_reg(adap, A_TP_PIO_DATA, val);
102 /* The minimum additive increment value for the congestion control table */
103 #define CC_MIN_INCR 2U
106 * t4_load_mtus - write the MTU and congestion control HW tables
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118 const unsigned short *alpha, const unsigned short *beta)
120 static const unsigned int avg_pkts[NCCTRL_WIN] = {
121 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123 28672, 40960, 57344, 81920, 114688, 163840, 229376
128 for (i = 0; i < NMTUS; ++i) {
129 unsigned int mtu = mtus[i];
130 unsigned int log2 = cxgbe_fls(mtu);
132 if (!(mtu & ((1 << log2) >> 2))) /* round */
134 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
137 for (w = 0; w < NCCTRL_WIN; ++w) {
140 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
143 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144 (w << 16) | (beta[w] << 13) | inc);
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times. If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there. Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165 int polarity, int attempts, int delay, u32 *valp)
168 u32 val = t4_read_reg(adapter, reg);
170 if (!!(val & mask) == polarity) {
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
189 * Sets a register field specified by the supplied mask to the
192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
195 u32 v = t4_read_reg(adapter, addr) & ~mask;
197 t4_write_reg(adapter, addr, v | val);
198 (void)t4_read_reg(adapter, addr); /* flush */
202 * t4_read_indirect - read indirectly addressed registers
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
210 * Reads registers that are accessed indirectly through an address/data
213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214 unsigned int data_reg, u32 *vals, unsigned int nregs,
215 unsigned int start_idx)
218 t4_write_reg(adap, addr_reg, start_idx);
219 *vals++ = t4_read_reg(adap, data_reg);
225 * t4_write_indirect - write indirectly addressed registers
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237 unsigned int data_reg, const u32 *vals,
238 unsigned int nregs, unsigned int start_idx)
241 t4_write_reg(adap, addr_reg, start_idx++);
242 t4_write_reg(adap, data_reg, *vals++);
247 * t4_report_fw_error - report firmware error
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
254 static void t4_report_fw_error(struct adapter *adap)
256 static const char * const reason[] = {
257 "Crash", /* PCIE_FW_EVAL_CRASH */
258 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
259 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
260 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
261 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
263 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
264 "Reserved", /* reserved */
268 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269 if (pcie_fw & F_PCIE_FW_ERR)
270 pr_err("%s: Firmware reports adapter error: %s\n",
271 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
280 for ( ; nflit; nflit--, mbox_addr += 8)
281 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
285 * Handle a FW assertion reported in a mailbox.
287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
289 struct fw_debug_cmd asrt;
291 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
303 /* makes single-statement usage a bit cleaner ... */
304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
305 #define T4_OS_MBOX_LOCKING(x) x
307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 * (negative implies @sleep_ok=false)
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command. If @rpl is not %NULL it is used to
323 * store the FW's reply to the command. The command and its optional
324 * reply are of the same length. Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false. This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
332 * Returns 0 on success or a negative errno on failure. A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error. In the latter case
335 * the return value is the error code indicated by FW (negated).
337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338 const void __attribute__((__may_alias__)) *cmd,
339 int size, void *rpl, bool sleep_ok, int timeout)
342 * We delay in small increments at first in an effort to maintain
343 * responsiveness for simple, fast executing commands but then back
344 * off to larger delays to a maximum retry delay.
346 static const int delay[] = {
347 1, 1, 3, 5, 10, 10, 20, 50, 100
353 unsigned int delay_idx;
354 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
356 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
359 struct mbox_entry entry;
365 if ((size & 15) || size > MBOX_LEN) {
371 memcpy(p, (const __be64 *)cmd, size);
374 * If we have a negative timeout, that implies that we can't sleep.
381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
383 * Queue ourselves onto the mailbox access list. When our entry is at
384 * the front of the list, we have rights to access the mailbox. So we
385 * wait [for a while] till we're at the front [or bail out with an
388 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
393 for (i = 0; ; i += ms) {
395 * If we've waited too long, return a busy indication. This
396 * really ought to be based on our initial position in the
397 * mailbox access list but this is a start. We very rarely
398 * contend on access to the mailbox ... Also check for a
399 * firmware error which we'll report as a device error.
401 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
402 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
403 t4_os_atomic_list_del(&entry, &adap->mbox_list,
405 t4_report_fw_error(adap);
406 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
410 * If we're at the head, break out and start the mailbox
413 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
417 * Delay for a bit before checking again ...
420 ms = delay[delay_idx]; /* last element may repeat */
421 if (delay_idx < ARRAY_SIZE(delay) - 1)
428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
431 * Attempt to gain access to the mailbox.
433 for (i = 0; i < 4; i++) {
434 ctl = t4_read_reg(adap, ctl_reg);
436 if (v != X_MBOWNER_NONE)
441 * If we were unable to gain access, dequeue ourselves from the
442 * mailbox atomic access list and report the error to our caller.
444 if (v != X_MBOWNER_PL) {
445 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
448 t4_report_fw_error(adap);
449 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
453 * If we gain ownership of the mailbox and there's a "valid" message
454 * in it, this is likely an asynchronous error message from the
455 * firmware. So we'll report that and then proceed on with attempting
456 * to issue our own command ... which may well fail if the error
457 * presaged the firmware crashing ...
459 if (ctl & F_MBMSGVALID) {
460 dev_err(adap, "found VALID command in mbox %u: "
461 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
462 (unsigned long long)t4_read_reg64(adap, data_reg),
463 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
473 * Copy in the new mailbox command and send it on its way ...
475 for (i = 0; i < size; i += 8, p++)
476 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
478 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
479 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
480 (unsigned long long)t4_read_reg64(adap, data_reg),
481 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
489 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
490 t4_read_reg(adap, ctl_reg); /* flush write */
496 * Loop waiting for the reply; bail out if we time out or the firmware
499 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
500 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
502 ms = delay[delay_idx]; /* last element may repeat */
503 if (delay_idx < ARRAY_SIZE(delay) - 1)
510 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
511 v = t4_read_reg(adap, ctl_reg);
512 if (v == X_CIM_PF_NOACCESS)
514 if (G_MBOWNER(v) == X_MBOWNER_PL) {
515 if (!(v & F_MBMSGVALID)) {
516 t4_write_reg(adap, ctl_reg,
517 V_MBOWNER(X_MBOWNER_NONE));
521 CXGBE_DEBUG_MBOX(adap,
522 "%s: mbox %u: %016llx %016llx %016llx %016llx "
523 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
524 (unsigned long long)t4_read_reg64(adap, data_reg),
525 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
533 CXGBE_DEBUG_MBOX(adap,
534 "command %#x completed in %d ms (%ssleeping)\n",
536 i + ms, sleep_ok ? "" : "non-");
538 res = t4_read_reg64(adap, data_reg);
539 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
540 fw_asrt(adap, data_reg);
541 res = V_FW_CMD_RETVAL(EIO);
543 get_mbox_rpl(adap, rpl, size / 8, data_reg);
545 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
547 t4_os_atomic_list_del(&entry, &adap->mbox_list,
549 return -G_FW_CMD_RETVAL((int)res);
554 * We timed out waiting for a reply to our mailbox command. Report
555 * the error and also check to see if the firmware reported any
558 dev_err(adap, "command %#x in mailbox %d timed out\n",
559 *(const u8 *)cmd, mbox);
560 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
563 t4_report_fw_error(adap);
565 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
568 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
569 void *rpl, bool sleep_ok)
571 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
576 * t4_get_regs_len - return the size of the chips register set
577 * @adapter: the adapter
579 * Returns the size of the chip's BAR0 register space.
581 unsigned int t4_get_regs_len(struct adapter *adapter)
583 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
585 switch (chip_version) {
588 return T5_REGMAP_SIZE;
592 "Unsupported chip version %d\n", chip_version);
597 * t4_get_regs - read chip registers into provided buffer
599 * @buf: register buffer
600 * @buf_size: size (in bytes) of register buffer
602 * If the provided register buffer isn't large enough for the chip's
603 * full register range, the register dump will be truncated to the
604 * register buffer's size.
606 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
608 static const unsigned int t5_reg_ranges[] = {
1383 static const unsigned int t6_reg_ranges[] = {
1944 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1945 const unsigned int *reg_ranges;
1946 int reg_ranges_size, range;
1947 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1949 /* Select the right set of register ranges to dump depending on the
1950 * adapter chip type.
1952 switch (chip_version) {
1954 reg_ranges = t5_reg_ranges;
1955 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1959 reg_ranges = t6_reg_ranges;
1960 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1965 "Unsupported chip version %d\n", chip_version);
1969 /* Clear the register buffer and insert the appropriate register
1970 * values selected by the above register ranges.
1972 memset(buf, 0, buf_size);
1973 for (range = 0; range < reg_ranges_size; range += 2) {
1974 unsigned int reg = reg_ranges[range];
1975 unsigned int last_reg = reg_ranges[range + 1];
1976 u32 *bufp = (u32 *)((char *)buf + reg);
1978 /* Iterate across the register range filling in the register
1979 * buffer but don't write past the end of the register buffer.
1981 while (reg <= last_reg && bufp < buf_end) {
1982 *bufp++ = t4_read_reg(adap, reg);
1988 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1989 #define EEPROM_DELAY 10 /* 10us per poll spin */
1990 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1992 #define EEPROM_STAT_ADDR 0x7bfc
1995 * Small utility function to wait till any outstanding VPD Access is complete.
1996 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1997 * VPD Access in flight. This allows us to handle the problem of having a
1998 * previous VPD Access time out and prevent an attempt to inject a new VPD
1999 * Request before any in-flight VPD request has completed.
2001 static int t4_seeprom_wait(struct adapter *adapter)
2003 unsigned int base = adapter->params.pci.vpd_cap_addr;
2006 /* If no VPD Access is in flight, we can just return success right
2009 if (!adapter->vpd_busy)
2012 /* Poll the VPD Capability Address/Flag register waiting for it
2013 * to indicate that the operation is complete.
2015 max_poll = EEPROM_MAX_POLL;
2019 udelay(EEPROM_DELAY);
2020 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2022 /* If the operation is complete, mark the VPD as no longer
2023 * busy and return success.
2025 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2026 adapter->vpd_busy = 0;
2029 } while (--max_poll);
2031 /* Failure! Note that we leave the VPD Busy status set in order to
2032 * avoid pushing a new VPD Access request into the VPD Capability till
2033 * the current operation eventually succeeds. It's a bug to issue a
2034 * new request when an existing request is in flight and will result
2035 * in corrupt hardware state.
2041 * t4_seeprom_read - read a serial EEPROM location
2042 * @adapter: adapter to read
2043 * @addr: EEPROM virtual address
2044 * @data: where to store the read data
2046 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2047 * VPD capability. Note that this function must be called with a virtual
2050 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2052 unsigned int base = adapter->params.pci.vpd_cap_addr;
2055 /* VPD Accesses must alway be 4-byte aligned!
2057 if (addr >= EEPROMVSIZE || (addr & 3))
2060 /* Wait for any previous operation which may still be in flight to
2063 ret = t4_seeprom_wait(adapter);
2065 dev_err(adapter, "VPD still busy from previous operation\n");
2069 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2070 * for our request to complete. If it doesn't complete, note the
2071 * error and return it to our caller. Note that we do not reset the
2074 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2075 adapter->vpd_busy = 1;
2076 adapter->vpd_flag = PCI_VPD_ADDR_F;
2077 ret = t4_seeprom_wait(adapter);
2079 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2083 /* Grab the returned data, swizzle it into our endianness and
2086 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2087 *data = le32_to_cpu(*data);
2092 * t4_seeprom_write - write a serial EEPROM location
2093 * @adapter: adapter to write
2094 * @addr: virtual EEPROM address
2095 * @data: value to write
2097 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2098 * VPD capability. Note that this function must be called with a virtual
2101 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2103 unsigned int base = adapter->params.pci.vpd_cap_addr;
2108 /* VPD Accesses must alway be 4-byte aligned!
2110 if (addr >= EEPROMVSIZE || (addr & 3))
2113 /* Wait for any previous operation which may still be in flight to
2116 ret = t4_seeprom_wait(adapter);
2118 dev_err(adapter, "VPD still busy from previous operation\n");
2122 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2123 * for our request to complete. If it doesn't complete, note the
2124 * error and return it to our caller. Note that we do not reset the
2127 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2129 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2130 (u16)addr | PCI_VPD_ADDR_F);
2131 adapter->vpd_busy = 1;
2132 adapter->vpd_flag = 0;
2133 ret = t4_seeprom_wait(adapter);
2135 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2139 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2140 * request to complete. If it doesn't complete, return error.
2142 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2143 max_poll = EEPROM_MAX_POLL;
2145 udelay(EEPROM_DELAY);
2146 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2147 } while ((stats_reg & 0x1) && --max_poll);
2151 /* Return success! */
2156 * t4_seeprom_wp - enable/disable EEPROM write protection
2157 * @adapter: the adapter
2158 * @enable: whether to enable or disable write protection
2160 * Enables or disables write protection on the serial EEPROM.
2162 int t4_seeprom_wp(struct adapter *adapter, int enable)
2164 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2168 * t4_config_rss_range - configure a portion of the RSS mapping table
2169 * @adapter: the adapter
2170 * @mbox: mbox to use for the FW command
2171 * @viid: virtual interface whose RSS subtable is to be written
2172 * @start: start entry in the table to write
2173 * @n: how many table entries to write
2174 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2175 * @nrspq: number of values in @rspq
2177 * Programs the selected part of the VI's RSS mapping table with the
2178 * provided values. If @nrspq < @n the supplied values are used repeatedly
2179 * until the full table range is populated.
2181 * The caller must ensure the values in @rspq are in the range allowed for
2184 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2185 int start, int n, const u16 *rspq, unsigned int nrspq)
2188 const u16 *rsp = rspq;
2189 const u16 *rsp_end = rspq + nrspq;
2190 struct fw_rss_ind_tbl_cmd cmd;
2192 memset(&cmd, 0, sizeof(cmd));
2193 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2194 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2195 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2196 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2199 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2200 * Queue Identifiers. These Ingress Queue IDs are packed three to
2201 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2205 int nq = min(n, 32);
2207 __be32 *qp = &cmd.iq0_to_iq2;
2210 * Set up the firmware RSS command header to send the next
2211 * "nq" Ingress Queue IDs to the firmware.
2213 cmd.niqid = cpu_to_be16(nq);
2214 cmd.startidx = cpu_to_be16(start);
2217 * "nq" more done for the start of the next loop.
2223 * While there are still Ingress Queue IDs to stuff into the
2224 * current firmware RSS command, retrieve them from the
2225 * Ingress Queue ID array and insert them into the command.
2229 * Grab up to the next 3 Ingress Queue IDs (wrapping
2230 * around the Ingress Queue ID array if necessary) and
2231 * insert them into the firmware RSS command at the
2232 * current 3-tuple position within the commad.
2236 int nqbuf = min(3, nq);
2242 while (nqbuf && nq_packed < 32) {
2249 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2250 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2251 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2255 * Send this portion of the RRS table update to the firmware;
2256 * bail out on any errors.
2258 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2267 * t4_config_vi_rss - configure per VI RSS settings
2268 * @adapter: the adapter
2269 * @mbox: mbox to use for the FW command
2272 * @defq: id of the default RSS queue for the VI.
2274 * Configures VI-specific RSS properties.
2276 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2277 unsigned int flags, unsigned int defq)
2279 struct fw_rss_vi_config_cmd c;
2281 memset(&c, 0, sizeof(c));
2282 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2283 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2284 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2285 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2286 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2287 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2288 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2292 * init_cong_ctrl - initialize congestion control parameters
2293 * @a: the alpha values for congestion control
2294 * @b: the beta values for congestion control
2296 * Initialize the congestion control parameters.
2298 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2302 for (i = 0; i < 9; i++) {
2356 #define INIT_CMD(var, cmd, rd_wr) do { \
2357 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2358 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2359 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2362 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2364 u32 cclk_param, cclk_val;
2368 * Ask firmware for the Core Clock since it knows how to translate the
2369 * Reference Clock ('V2') VPD field into a Core Clock value ...
2371 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2372 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2373 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2374 1, &cclk_param, &cclk_val);
2376 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2382 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2386 /* serial flash and firmware constants and flash config file constants */
2388 SF_ATTEMPTS = 10, /* max retries for SF operations */
2390 /* flash command opcodes */
2391 SF_PROG_PAGE = 2, /* program page */
2392 SF_WR_DISABLE = 4, /* disable writes */
2393 SF_RD_STATUS = 5, /* read status register */
2394 SF_WR_ENABLE = 6, /* enable writes */
2395 SF_RD_DATA_FAST = 0xb, /* read flash */
2396 SF_RD_ID = 0x9f, /* read ID */
2397 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2401 * sf1_read - read data from the serial flash
2402 * @adapter: the adapter
2403 * @byte_cnt: number of bytes to read
2404 * @cont: whether another operation will be chained
2405 * @lock: whether to lock SF for PL access only
2406 * @valp: where to store the read data
2408 * Reads up to 4 bytes of data from the serial flash. The location of
2409 * the read needs to be specified prior to calling this by issuing the
2410 * appropriate commands to the serial flash.
2412 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2413 int lock, u32 *valp)
2417 if (!byte_cnt || byte_cnt > 4)
2419 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2421 t4_write_reg(adapter, A_SF_OP,
2422 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2423 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2425 *valp = t4_read_reg(adapter, A_SF_DATA);
2430 * sf1_write - write data to the serial flash
2431 * @adapter: the adapter
2432 * @byte_cnt: number of bytes to write
2433 * @cont: whether another operation will be chained
2434 * @lock: whether to lock SF for PL access only
2435 * @val: value to write
2437 * Writes up to 4 bytes of data to the serial flash. The location of
2438 * the write needs to be specified prior to calling this by issuing the
2439 * appropriate commands to the serial flash.
2441 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2444 if (!byte_cnt || byte_cnt > 4)
2446 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2448 t4_write_reg(adapter, A_SF_DATA, val);
2449 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2450 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2451 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2455 * t4_read_flash - read words from serial flash
2456 * @adapter: the adapter
2457 * @addr: the start address for the read
2458 * @nwords: how many 32-bit words to read
2459 * @data: where to store the read data
2460 * @byte_oriented: whether to store data as bytes or as words
2462 * Read the specified number of 32-bit words from the serial flash.
2463 * If @byte_oriented is set the read data is stored as a byte array
2464 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2465 * natural endianness.
2467 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2468 unsigned int nwords, u32 *data, int byte_oriented)
2472 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2476 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2478 ret = sf1_write(adapter, 4, 1, 0, addr);
2482 ret = sf1_read(adapter, 1, 1, 0, data);
2486 for ( ; nwords; nwords--, data++) {
2487 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2489 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2493 *data = cpu_to_be32(*data);
2499 * t4_get_exprom_version - return the Expansion ROM version (if any)
2500 * @adapter: the adapter
2501 * @vers: where to place the version
2503 * Reads the Expansion ROM header from FLASH and returns the version
2504 * number (if present) through the @vers return value pointer. We return
2505 * this in the Firmware Version Format since it's convenient. Return
2506 * 0 on success, -ENOENT if no Expansion ROM is present.
2508 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2510 struct exprom_header {
2511 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2512 unsigned char hdr_ver[4]; /* Expansion ROM version */
2514 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2518 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2519 ARRAY_SIZE(exprom_header_buf),
2520 exprom_header_buf, 0);
2524 hdr = (struct exprom_header *)exprom_header_buf;
2525 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2528 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2529 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2530 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2531 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2536 * t4_get_fw_version - read the firmware version
2537 * @adapter: the adapter
2538 * @vers: where to place the version
2540 * Reads the FW version from flash.
2542 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2544 return t4_read_flash(adapter, FLASH_FW_START +
2545 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2549 * t4_get_bs_version - read the firmware bootstrap version
2550 * @adapter: the adapter
2551 * @vers: where to place the version
2553 * Reads the FW Bootstrap version from flash.
2555 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2557 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2558 offsetof(struct fw_hdr, fw_ver), 1,
2563 * t4_get_tp_version - read the TP microcode version
2564 * @adapter: the adapter
2565 * @vers: where to place the version
2567 * Reads the TP microcode version from flash.
2569 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2571 return t4_read_flash(adapter, FLASH_FW_START +
2572 offsetof(struct fw_hdr, tp_microcode_ver),
2577 * t4_get_version_info - extract various chip/firmware version information
2578 * @adapter: the adapter
2580 * Reads various chip/firmware version numbers and stores them into the
2581 * adapter Adapter Parameters structure. If any of the efforts fails
2582 * the first failure will be returned, but all of the version numbers
2585 int t4_get_version_info(struct adapter *adapter)
2589 #define FIRST_RET(__getvinfo) \
2591 int __ret = __getvinfo; \
2592 if (__ret && !ret) \
2596 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2597 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2598 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2599 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2607 * t4_dump_version_info - dump all of the adapter configuration IDs
2608 * @adapter: the adapter
2610 * Dumps all of the various bits of adapter configuration version/revision
2611 * IDs information. This is typically called at some point after
2612 * t4_get_version_info() has been called.
2614 void t4_dump_version_info(struct adapter *adapter)
2617 * Device information.
2619 dev_info(adapter, "Chelsio rev %d\n",
2620 CHELSIO_CHIP_RELEASE(adapter->params.chip));
2625 if (!adapter->params.fw_vers)
2626 dev_warn(adapter, "No firmware loaded\n");
2628 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2629 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2630 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2631 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2632 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2635 * Bootstrap Firmware Version.
2637 if (!adapter->params.bs_vers)
2638 dev_warn(adapter, "No bootstrap loaded\n");
2640 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2641 G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2642 G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2643 G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2644 G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2647 * TP Microcode Version.
2649 if (!adapter->params.tp_vers)
2650 dev_warn(adapter, "No TP Microcode loaded\n");
2652 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2653 G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2654 G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2655 G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2656 G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2659 * Expansion ROM version.
2661 if (!adapter->params.er_vers)
2662 dev_info(adapter, "No Expansion ROM loaded\n");
2664 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2665 G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2666 G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2667 G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2668 G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2671 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2675 * t4_link_l1cfg - apply link configuration to MAC/PHY
2676 * @phy: the PHY to setup
2677 * @mac: the MAC to setup
2678 * @lc: the requested link configuration
2680 * Set up a port's MAC and PHY according to a desired link configuration.
2681 * - If the PHY can auto-negotiate first decide what to advertise, then
2682 * enable/disable auto-negotiation as desired, and reset.
2683 * - If the PHY does not auto-negotiate just reset it.
2684 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2685 * otherwise do it later based on the outcome of auto-negotiation.
2687 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2688 struct link_config *lc)
2690 struct fw_port_cmd c;
2691 unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2692 unsigned int fc, fec;
2696 if (lc->requested_fc & PAUSE_RX)
2697 fc |= FW_PORT_CAP_FC_RX;
2698 if (lc->requested_fc & PAUSE_TX)
2699 fc |= FW_PORT_CAP_FC_TX;
2702 if (lc->requested_fec & FEC_RS)
2703 fec |= FW_PORT_CAP_FEC_RS;
2704 if (lc->requested_fec & FEC_BASER_RS)
2705 fec |= FW_PORT_CAP_FEC_BASER_RS;
2706 if (lc->requested_fec & FEC_RESERVED)
2707 fec |= FW_PORT_CAP_FEC_RESERVED;
2709 memset(&c, 0, sizeof(c));
2710 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2711 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2712 V_FW_PORT_CMD_PORTID(port));
2714 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2717 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2718 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2720 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2721 lc->fec = lc->requested_fec;
2722 } else if (lc->autoneg == AUTONEG_DISABLE) {
2723 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2725 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2726 lc->fec = lc->requested_fec;
2728 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2731 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2735 * t4_flash_cfg_addr - return the address of the flash configuration file
2736 * @adapter: the adapter
2738 * Return the address within the flash where the Firmware Configuration
2739 * File is stored, or an error if the device FLASH is too small to contain
2740 * a Firmware Configuration File.
2742 int t4_flash_cfg_addr(struct adapter *adapter)
2745 * If the device FLASH isn't large enough to hold a Firmware
2746 * Configuration File, return an error.
2748 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2751 return FLASH_CFG_START;
2754 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2757 * t4_intr_enable - enable interrupts
2758 * @adapter: the adapter whose interrupts should be enabled
2760 * Enable PF-specific interrupts for the calling function and the top-level
2761 * interrupt concentrator for global interrupts. Interrupts are already
2762 * enabled at each module, here we just enable the roots of the interrupt
2765 * Note: this function should be called only when the driver manages
2766 * non PF-specific interrupts from the various HW modules. Only one PCI
2767 * function at a time should be doing this.
2769 void t4_intr_enable(struct adapter *adapter)
2772 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2773 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2774 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2776 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2777 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2778 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2779 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2780 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2781 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2782 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2783 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2784 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2785 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2786 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2790 * t4_intr_disable - disable interrupts
2791 * @adapter: the adapter whose interrupts should be disabled
2793 * Disable interrupts. We only disable the top-level interrupt
2794 * concentrators. The caller must be a PCI function managing global
2797 void t4_intr_disable(struct adapter *adapter)
2799 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2800 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2801 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2803 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2804 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2808 * t4_get_port_type_description - return Port Type string description
2809 * @port_type: firmware Port Type enumeration
2811 const char *t4_get_port_type_description(enum fw_port_type port_type)
2813 static const char * const port_type_description[] = {
2838 if (port_type < ARRAY_SIZE(port_type_description))
2839 return port_type_description[port_type];
2844 * t4_get_mps_bg_map - return the buffer groups associated with a port
2845 * @adap: the adapter
2846 * @pidx: the port index
2848 * Returns a bitmap indicating which MPS buffer groups are associated
2849 * with the given port. Bit i is set if buffer group i is used by the
2852 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2854 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2855 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2858 if (pidx >= nports) {
2859 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2864 switch (chip_version) {
2869 case 2: return 3 << (2 * pidx);
2870 case 4: return 1 << pidx;
2876 case 2: return 1 << (2 * pidx);
2881 dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2882 chip_version, nports);
2887 * t4_get_tp_ch_map - return TP ingress channels associated with a port
2888 * @adapter: the adapter
2889 * @pidx: the port index
2891 * Returns a bitmap indicating which TP Ingress Channels are associated with
2892 * a given Port. Bit i is set if TP Ingress Channel i is used by the Port.
2894 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2896 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2897 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2900 if (pidx >= nports) {
2901 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2906 switch (chip_version) {
2909 /* Note that this happens to be the same values as the MPS
2910 * Buffer Group Map for these Chips. But we replicate the code
2911 * here because they're really separate concepts.
2915 case 2: return 3 << (2 * pidx);
2916 case 4: return 1 << pidx;
2922 case 2: return 1 << pidx;
2927 dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
2928 chip_version, nports);
2933 * t4_get_port_stats - collect port statistics
2934 * @adap: the adapter
2935 * @idx: the port index
2936 * @p: the stats structure to fill
2938 * Collect statistics related to the given port from HW.
2940 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2942 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2943 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
2945 #define GET_STAT(name) \
2946 t4_read_reg64(adap, \
2947 (is_t4(adap->params.chip) ? \
2948 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2949 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2950 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2952 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2953 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2954 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2955 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2956 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2957 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2958 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2959 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2960 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2961 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2962 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2963 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2964 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2965 p->tx_drop = GET_STAT(TX_PORT_DROP);
2966 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2967 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2968 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2969 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2970 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2971 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2972 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2973 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2974 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2976 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2977 if (stat_ctl & F_COUNTPAUSESTATTX) {
2978 p->tx_frames -= p->tx_pause;
2979 p->tx_octets -= p->tx_pause * 64;
2981 if (stat_ctl & F_COUNTPAUSEMCTX)
2982 p->tx_mcast_frames -= p->tx_pause;
2985 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2986 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2987 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2988 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2989 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2990 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2991 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2992 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2993 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2994 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2995 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2996 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2997 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2998 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2999 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
3000 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
3001 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3002 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
3003 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
3004 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
3005 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
3006 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
3007 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
3008 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
3009 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
3010 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
3011 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
3013 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3014 if (stat_ctl & F_COUNTPAUSESTATRX) {
3015 p->rx_frames -= p->rx_pause;
3016 p->rx_octets -= p->rx_pause * 64;
3018 if (stat_ctl & F_COUNTPAUSEMCRX)
3019 p->rx_mcast_frames -= p->rx_pause;
3022 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3023 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3024 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3025 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3026 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3027 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3028 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3029 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3036 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3037 * @adap: The adapter
3039 * @stats: Current stats to fill
3040 * @offset: Previous stats snapshot
3042 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3043 struct port_stats *stats,
3044 struct port_stats *offset)
3049 t4_get_port_stats(adap, idx, stats);
3050 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3051 i < (sizeof(struct port_stats) / sizeof(u64));
3057 * t4_clr_port_stats - clear port statistics
3058 * @adap: the adapter
3059 * @idx: the port index
3061 * Clear HW statistics for the given port.
3063 void t4_clr_port_stats(struct adapter *adap, int idx)
3066 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3069 if (is_t4(adap->params.chip))
3070 port_base_addr = PORT_BASE(idx);
3072 port_base_addr = T5_PORT_BASE(idx);
3074 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3075 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3076 t4_write_reg(adap, port_base_addr + i, 0);
3077 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3078 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3079 t4_write_reg(adap, port_base_addr + i, 0);
3080 for (i = 0; i < 4; i++)
3081 if (bgmap & (1 << i)) {
3083 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3086 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3092 * t4_fw_hello - establish communication with FW
3093 * @adap: the adapter
3094 * @mbox: mailbox to use for the FW command
3095 * @evt_mbox: mailbox to receive async FW events
3096 * @master: specifies the caller's willingness to be the device master
3097 * @state: returns the current device state (if non-NULL)
3099 * Issues a command to establish communication with FW. Returns either
3100 * an error (negative integer) or the mailbox of the Master PF.
3102 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3103 enum dev_master master, enum dev_state *state)
3106 struct fw_hello_cmd c;
3108 unsigned int master_mbox;
3109 int retries = FW_CMD_HELLO_RETRIES;
3112 memset(&c, 0, sizeof(c));
3113 INIT_CMD(c, HELLO, WRITE);
3114 c.err_to_clearinit = cpu_to_be32(
3115 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3116 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3117 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3118 M_FW_HELLO_CMD_MBMASTER) |
3119 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3120 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3121 F_FW_HELLO_CMD_CLEARINIT);
3124 * Issue the HELLO command to the firmware. If it's not successful
3125 * but indicates that we got a "busy" or "timeout" condition, retry
3126 * the HELLO until we exhaust our retry limit. If we do exceed our
3127 * retry limit, check to see if the firmware left us any error
3128 * information and report that if so ...
3130 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3131 if (ret != FW_SUCCESS) {
3132 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3134 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3135 t4_report_fw_error(adap);
3139 v = be32_to_cpu(c.err_to_clearinit);
3140 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3142 if (v & F_FW_HELLO_CMD_ERR)
3143 *state = DEV_STATE_ERR;
3144 else if (v & F_FW_HELLO_CMD_INIT)
3145 *state = DEV_STATE_INIT;
3147 *state = DEV_STATE_UNINIT;
3151 * If we're not the Master PF then we need to wait around for the
3152 * Master PF Driver to finish setting up the adapter.
3154 * Note that we also do this wait if we're a non-Master-capable PF and
3155 * there is no current Master PF; a Master PF may show up momentarily
3156 * and we wouldn't want to fail pointlessly. (This can happen when an
3157 * OS loads lots of different drivers rapidly at the same time). In
3158 * this case, the Master PF returned by the firmware will be
3159 * M_PCIE_FW_MASTER so the test below will work ...
3161 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3162 master_mbox != mbox) {
3163 int waiting = FW_CMD_HELLO_TIMEOUT;
3166 * Wait for the firmware to either indicate an error or
3167 * initialized state. If we see either of these we bail out
3168 * and report the issue to the caller. If we exhaust the
3169 * "hello timeout" and we haven't exhausted our retries, try
3170 * again. Otherwise bail with a timeout error.
3179 * If neither Error nor Initialialized are indicated
3180 * by the firmware keep waiting till we exaust our
3181 * timeout ... and then retry if we haven't exhausted
3184 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3185 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3196 * We either have an Error or Initialized condition
3197 * report errors preferentially.
3200 if (pcie_fw & F_PCIE_FW_ERR)
3201 *state = DEV_STATE_ERR;
3202 else if (pcie_fw & F_PCIE_FW_INIT)
3203 *state = DEV_STATE_INIT;
3207 * If we arrived before a Master PF was selected and
3208 * there's not a valid Master PF, grab its identity
3211 if (master_mbox == M_PCIE_FW_MASTER &&
3212 (pcie_fw & F_PCIE_FW_MASTER_VLD))
3213 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3222 * t4_fw_bye - end communication with FW
3223 * @adap: the adapter
3224 * @mbox: mailbox to use for the FW command
3226 * Issues a command to terminate communication with FW.
3228 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3230 struct fw_bye_cmd c;
3232 memset(&c, 0, sizeof(c));
3233 INIT_CMD(c, BYE, WRITE);
3234 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3238 * t4_fw_reset - issue a reset to FW
3239 * @adap: the adapter
3240 * @mbox: mailbox to use for the FW command
3241 * @reset: specifies the type of reset to perform
3243 * Issues a reset command of the specified type to FW.
3245 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3247 struct fw_reset_cmd c;
3249 memset(&c, 0, sizeof(c));
3250 INIT_CMD(c, RESET, WRITE);
3251 c.val = cpu_to_be32(reset);
3252 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3256 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3257 * @adap: the adapter
3258 * @mbox: mailbox to use for the FW RESET command (if desired)
3259 * @force: force uP into RESET even if FW RESET command fails
3261 * Issues a RESET command to firmware (if desired) with a HALT indication
3262 * and then puts the microprocessor into RESET state. The RESET command
3263 * will only be issued if a legitimate mailbox is provided (mbox <=
3264 * M_PCIE_FW_MASTER).
3266 * This is generally used in order for the host to safely manipulate the
3267 * adapter without fear of conflicting with whatever the firmware might
3268 * be doing. The only way out of this state is to RESTART the firmware
3271 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3276 * If a legitimate mailbox is provided, issue a RESET command
3277 * with a HALT indication.
3279 if (mbox <= M_PCIE_FW_MASTER) {
3280 struct fw_reset_cmd c;
3282 memset(&c, 0, sizeof(c));
3283 INIT_CMD(c, RESET, WRITE);
3284 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3285 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3286 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3290 * Normally we won't complete the operation if the firmware RESET
3291 * command fails but if our caller insists we'll go ahead and put the
3292 * uP into RESET. This can be useful if the firmware is hung or even
3293 * missing ... We'll have to take the risk of putting the uP into
3294 * RESET without the cooperation of firmware in that case.
3296 * We also force the firmware's HALT flag to be on in case we bypassed
3297 * the firmware RESET command above or we're dealing with old firmware
3298 * which doesn't have the HALT capability. This will serve as a flag
3299 * for the incoming firmware to know that it's coming out of a HALT
3300 * rather than a RESET ... if it's new enough to understand that ...
3302 if (ret == 0 || force) {
3303 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3304 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3309 * And we always return the result of the firmware RESET command
3310 * even when we force the uP into RESET ...
3316 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3317 * @adap: the adapter
3318 * @mbox: mailbox to use for the FW RESET command (if desired)
3319 * @reset: if we want to do a RESET to restart things
3321 * Restart firmware previously halted by t4_fw_halt(). On successful
3322 * return the previous PF Master remains as the new PF Master and there
3323 * is no need to issue a new HELLO command, etc.
3325 * We do this in two ways:
3327 * 1. If we're dealing with newer firmware we'll simply want to take
3328 * the chip's microprocessor out of RESET. This will cause the
3329 * firmware to start up from its start vector. And then we'll loop
3330 * until the firmware indicates it's started again (PCIE_FW.HALT
3331 * reset to 0) or we timeout.
3333 * 2. If we're dealing with older firmware then we'll need to RESET
3334 * the chip since older firmware won't recognize the PCIE_FW.HALT
3335 * flag and automatically RESET itself on startup.
3337 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3341 * Since we're directing the RESET instead of the firmware
3342 * doing it automatically, we need to clear the PCIE_FW.HALT
3345 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3348 * If we've been given a valid mailbox, first try to get the
3349 * firmware to do the RESET. If that works, great and we can
3350 * return success. Otherwise, if we haven't been given a
3351 * valid mailbox or the RESET command failed, fall back to
3352 * hitting the chip with a hammer.
3354 if (mbox <= M_PCIE_FW_MASTER) {
3355 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3357 if (t4_fw_reset(adap, mbox,
3358 F_PIORST | F_PIORSTMODE) == 0)
3362 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3367 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3368 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3369 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3380 * t4_fl_pkt_align - return the fl packet alignment
3381 * @adap: the adapter
3383 * T4 has a single field to specify the packing and padding boundary.
3384 * T5 onwards has separate fields for this and hence the alignment for
3385 * next packet offset is maximum of these two.
3387 int t4_fl_pkt_align(struct adapter *adap)
3389 u32 sge_control, sge_control2;
3390 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3392 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3394 /* T4 uses a single control field to specify both the PCIe Padding and
3395 * Packing Boundary. T5 introduced the ability to specify these
3396 * separately. The actual Ingress Packet Data alignment boundary
3397 * within Packed Buffer Mode is the maximum of these two
3400 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3401 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3403 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3405 ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3407 fl_align = ingpadboundary;
3408 if (!is_t4(adap->params.chip)) {
3409 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3410 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3411 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3412 ingpackboundary = 16;
3414 ingpackboundary = 1 << (ingpackboundary +
3415 X_INGPACKBOUNDARY_SHIFT);
3417 fl_align = max(ingpadboundary, ingpackboundary);
3423 * t4_fixup_host_params_compat - fix up host-dependent parameters
3424 * @adap: the adapter
3425 * @page_size: the host's Base Page Size
3426 * @cache_line_size: the host's Cache Line Size
3427 * @chip_compat: maintain compatibility with designated chip
3429 * Various registers in the chip contain values which are dependent on the
3430 * host's Base Page and Cache Line Sizes. This function will fix all of
3431 * those registers with the appropriate values as passed in ...
3433 * @chip_compat is used to limit the set of changes that are made
3434 * to be compatible with the indicated chip release. This is used by
3435 * drivers to maintain compatibility with chip register settings when
3436 * the drivers haven't [yet] been updated with new chip support.
3438 int t4_fixup_host_params_compat(struct adapter *adap,
3439 unsigned int page_size,
3440 unsigned int cache_line_size,
3441 enum chip_type chip_compat)
3443 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3444 unsigned int sge_hps = page_shift - 10;
3445 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3446 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3447 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3449 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3450 V_HOSTPAGESIZEPF0(sge_hps) |
3451 V_HOSTPAGESIZEPF1(sge_hps) |
3452 V_HOSTPAGESIZEPF2(sge_hps) |
3453 V_HOSTPAGESIZEPF3(sge_hps) |
3454 V_HOSTPAGESIZEPF4(sge_hps) |
3455 V_HOSTPAGESIZEPF5(sge_hps) |
3456 V_HOSTPAGESIZEPF6(sge_hps) |
3457 V_HOSTPAGESIZEPF7(sge_hps));
3459 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3460 t4_set_reg_field(adap, A_SGE_CONTROL,
3461 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3462 F_EGRSTATUSPAGESIZE,
3463 V_INGPADBOUNDARY(fl_align_log -
3464 X_INGPADBOUNDARY_SHIFT) |
3465 V_EGRSTATUSPAGESIZE(stat_len != 64));
3467 unsigned int pack_align;
3468 unsigned int ingpad, ingpack;
3469 unsigned int pcie_cap;
3472 * T5 introduced the separation of the Free List Padding and
3473 * Packing Boundaries. Thus, we can select a smaller Padding
3474 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3475 * Bandwidth, and use a Packing Boundary which is large enough
3476 * to avoid false sharing between CPUs, etc.
3478 * For the PCI Link, the smaller the Padding Boundary the
3479 * better. For the Memory Controller, a smaller Padding
3480 * Boundary is better until we cross under the Memory Line
3481 * Size (the minimum unit of transfer to/from Memory). If we
3482 * have a Padding Boundary which is smaller than the Memory
3483 * Line Size, that'll involve a Read-Modify-Write cycle on the
3484 * Memory Controller which is never good.
3487 /* We want the Packing Boundary to be based on the Cache Line
3488 * Size in order to help avoid False Sharing performance
3489 * issues between CPUs, etc. We also want the Packing
3490 * Boundary to incorporate the PCI-E Maximum Payload Size. We
3491 * get best performance when the Packing Boundary is a
3492 * multiple of the Maximum Payload Size.
3494 pack_align = fl_align;
3495 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3497 unsigned int mps, mps_log;
3500 /* The PCIe Device Control Maximum Payload Size field
3501 * [bits 7:5] encodes sizes as powers of 2 starting at
3504 t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3506 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3508 if (mps > pack_align)
3513 * N.B. T5 has a different interpretation of the "0" value for
3514 * the Packing Boundary. This corresponds to 16 bytes instead
3515 * of the expected 32 bytes. We never have a Packing Boundary
3516 * less than 32 bytes so we can't use that special value but
3517 * on the other hand, if we wanted 32 bytes, the best we can
3518 * really do is 64 bytes ...
3520 if (pack_align <= 16) {
3521 ingpack = X_INGPACKBOUNDARY_16B;
3523 } else if (pack_align == 32) {
3524 ingpack = X_INGPACKBOUNDARY_64B;
3527 unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3529 ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3530 fl_align = pack_align;
3533 /* Use the smallest Ingress Padding which isn't smaller than
3534 * the Memory Controller Read/Write Size. We'll take that as
3535 * being 8 bytes since we don't know of any system with a
3536 * wider Memory Controller Bus Width.
3538 if (is_t5(adap->params.chip))
3539 ingpad = X_INGPADBOUNDARY_32B;
3541 ingpad = X_T6_INGPADBOUNDARY_8B;
3542 t4_set_reg_field(adap, A_SGE_CONTROL,
3543 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3544 F_EGRSTATUSPAGESIZE,
3545 V_INGPADBOUNDARY(ingpad) |
3546 V_EGRSTATUSPAGESIZE(stat_len != 64));
3547 t4_set_reg_field(adap, A_SGE_CONTROL2,
3548 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3549 V_INGPACKBOUNDARY(ingpack));
3553 * Adjust various SGE Free List Host Buffer Sizes.
3555 * The first four entries are:
3559 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3560 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3562 * For the single-MTU buffers in unpacked mode we need to include
3563 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3564 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3565 * Padding boundary. All of these are accommodated in the Factory
3566 * Default Firmware Configuration File but we need to adjust it for
3567 * this host's cache line size.
3569 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3570 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3571 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3573 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3574 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3577 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3583 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3584 * @adap: the adapter
3585 * @page_size: the host's Base Page Size
3586 * @cache_line_size: the host's Cache Line Size
3588 * Various registers in T4 contain values which are dependent on the
3589 * host's Base Page and Cache Line Sizes. This function will fix all of
3590 * those registers with the appropriate values as passed in ...
3592 * This routine makes changes which are compatible with T4 chips.
3594 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3595 unsigned int cache_line_size)
3597 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3602 * t4_fw_initialize - ask FW to initialize the device
3603 * @adap: the adapter
3604 * @mbox: mailbox to use for the FW command
3606 * Issues a command to FW to partially initialize the device. This
3607 * performs initialization that generally doesn't depend on user input.
3609 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3611 struct fw_initialize_cmd c;
3613 memset(&c, 0, sizeof(c));
3614 INIT_CMD(c, INITIALIZE, WRITE);
3615 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3619 * t4_query_params_rw - query FW or device parameters
3620 * @adap: the adapter
3621 * @mbox: mailbox to use for the FW command
3624 * @nparams: the number of parameters
3625 * @params: the parameter names
3626 * @val: the parameter values
3627 * @rw: Write and read flag
3629 * Reads the value of FW or device parameters. Up to 7 parameters can be
3632 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3633 unsigned int pf, unsigned int vf,
3634 unsigned int nparams, const u32 *params,
3639 struct fw_params_cmd c;
3640 __be32 *p = &c.param[0].mnem;
3645 memset(&c, 0, sizeof(c));
3646 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3647 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3648 V_FW_PARAMS_CMD_PFN(pf) |
3649 V_FW_PARAMS_CMD_VFN(vf));
3650 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3652 for (i = 0; i < nparams; i++) {
3653 *p++ = cpu_to_be32(*params++);
3655 *p = cpu_to_be32(*(val + i));
3659 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3661 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3662 *val++ = be32_to_cpu(*p);
3666 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3667 unsigned int vf, unsigned int nparams, const u32 *params,
3670 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3674 * t4_set_params_timeout - sets FW or device parameters
3675 * @adap: the adapter
3676 * @mbox: mailbox to use for the FW command
3679 * @nparams: the number of parameters
3680 * @params: the parameter names
3681 * @val: the parameter values
3682 * @timeout: the timeout time
3684 * Sets the value of FW or device parameters. Up to 7 parameters can be
3685 * specified at once.
3687 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3688 unsigned int pf, unsigned int vf,
3689 unsigned int nparams, const u32 *params,
3690 const u32 *val, int timeout)
3692 struct fw_params_cmd c;
3693 __be32 *p = &c.param[0].mnem;
3698 memset(&c, 0, sizeof(c));
3699 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3700 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3701 V_FW_PARAMS_CMD_PFN(pf) |
3702 V_FW_PARAMS_CMD_VFN(vf));
3703 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3706 *p++ = cpu_to_be32(*params++);
3707 *p++ = cpu_to_be32(*val++);
3710 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3713 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3714 unsigned int vf, unsigned int nparams, const u32 *params,
3717 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3718 FW_CMD_MAX_TIMEOUT);
3722 * t4_alloc_vi_func - allocate a virtual interface
3723 * @adap: the adapter
3724 * @mbox: mailbox to use for the FW command
3725 * @port: physical port associated with the VI
3726 * @pf: the PF owning the VI
3727 * @vf: the VF owning the VI
3728 * @nmac: number of MAC addresses needed (1 to 5)
3729 * @mac: the MAC addresses of the VI
3730 * @rss_size: size of RSS table slice associated with this VI
3731 * @portfunc: which Port Application Function MAC Address is desired
3732 * @idstype: Intrusion Detection Type
3734 * Allocates a virtual interface for the given physical port. If @mac is
3735 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3736 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3737 * stored consecutively so the space needed is @nmac * 6 bytes.
3738 * Returns a negative error number or the non-negative VI id.
3740 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3741 unsigned int port, unsigned int pf, unsigned int vf,
3742 unsigned int nmac, u8 *mac, unsigned int *rss_size,
3743 unsigned int portfunc, unsigned int idstype)
3748 memset(&c, 0, sizeof(c));
3749 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3750 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3751 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3752 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3753 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3754 V_FW_VI_CMD_FUNC(portfunc));
3755 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3758 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3763 memcpy(mac, c.mac, sizeof(c.mac));
3766 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3769 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3772 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3775 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3780 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3781 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3785 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3786 * @adap: the adapter
3787 * @mbox: mailbox to use for the FW command
3788 * @port: physical port associated with the VI
3789 * @pf: the PF owning the VI
3790 * @vf: the VF owning the VI
3791 * @nmac: number of MAC addresses needed (1 to 5)
3792 * @mac: the MAC addresses of the VI
3793 * @rss_size: size of RSS table slice associated with this VI
3795 * Backwards compatible and convieniance routine to allocate a Virtual
3796 * Interface with a Ethernet Port Application Function and Intrustion
3797 * Detection System disabled.
3799 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3800 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3801 unsigned int *rss_size)
3803 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3808 * t4_free_vi - free a virtual interface
3809 * @adap: the adapter
3810 * @mbox: mailbox to use for the FW command
3811 * @pf: the PF owning the VI
3812 * @vf: the VF owning the VI
3813 * @viid: virtual interface identifiler
3815 * Free a previously allocated virtual interface.
3817 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3818 unsigned int vf, unsigned int viid)
3822 memset(&c, 0, sizeof(c));
3823 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3824 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3825 V_FW_VI_CMD_VFN(vf));
3826 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3827 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3829 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3833 * t4_set_rxmode - set Rx properties of a virtual interface
3834 * @adap: the adapter
3835 * @mbox: mailbox to use for the FW command
3837 * @mtu: the new MTU or -1
3838 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3839 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3840 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3841 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3843 * @sleep_ok: if true we may sleep while awaiting command completion
3845 * Sets Rx properties of a virtual interface.
3847 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3848 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3851 struct fw_vi_rxmode_cmd c;
3853 /* convert to FW values */
3855 mtu = M_FW_VI_RXMODE_CMD_MTU;
3857 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3859 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3861 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3863 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3865 memset(&c, 0, sizeof(c));
3866 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3867 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3868 V_FW_VI_RXMODE_CMD_VIID(viid));
3869 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3870 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3871 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3872 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3873 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3874 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3875 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3879 * t4_change_mac - modifies the exact-match filter for a MAC address
3880 * @adap: the adapter
3881 * @mbox: mailbox to use for the FW command
3883 * @idx: index of existing filter for old value of MAC address, or -1
3884 * @addr: the new MAC address value
3885 * @persist: whether a new MAC allocation should be persistent
3886 * @add_smt: if true also add the address to the HW SMT
3888 * Modifies an exact-match filter and sets it to the new MAC address if
3889 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
3890 * latter case the address is added persistently if @persist is %true.
3892 * Note that in general it is not possible to modify the value of a given
3893 * filter so the generic way to modify an address filter is to free the one
3894 * being used by the old address value and allocate a new filter for the
3895 * new address value.
3897 * Returns a negative error number or the index of the filter with the new
3898 * MAC value. Note that this index may differ from @idx.
3900 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3901 int idx, const u8 *addr, bool persist, bool add_smt)
3904 struct fw_vi_mac_cmd c;
3905 struct fw_vi_mac_exact *p = c.u.exact;
3906 int max_mac_addr = adap->params.arch.mps_tcam_size;
3908 if (idx < 0) /* new allocation */
3909 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3910 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3912 memset(&c, 0, sizeof(c));
3913 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3914 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3915 V_FW_VI_MAC_CMD_VIID(viid));
3916 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3917 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3918 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3919 V_FW_VI_MAC_CMD_IDX(idx));
3920 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3922 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3924 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3925 if (ret >= max_mac_addr)
3932 * t4_enable_vi_params - enable/disable a virtual interface
3933 * @adap: the adapter
3934 * @mbox: mailbox to use for the FW command
3936 * @rx_en: 1=enable Rx, 0=disable Rx
3937 * @tx_en: 1=enable Tx, 0=disable Tx
3938 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3940 * Enables/disables a virtual interface. Note that setting DCB Enable
3941 * only makes sense when enabling a Virtual Interface ...
3943 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3944 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3946 struct fw_vi_enable_cmd c;
3948 memset(&c, 0, sizeof(c));
3949 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3950 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3951 V_FW_VI_ENABLE_CMD_VIID(viid));
3952 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3953 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3954 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3956 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3960 * t4_enable_vi - enable/disable a virtual interface
3961 * @adap: the adapter
3962 * @mbox: mailbox to use for the FW command
3964 * @rx_en: 1=enable Rx, 0=disable Rx
3965 * @tx_en: 1=enable Tx, 0=disable Tx
3967 * Enables/disables a virtual interface. Note that setting DCB Enable
3968 * only makes sense when enabling a Virtual Interface ...
3970 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3971 bool rx_en, bool tx_en)
3973 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3977 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3978 * @adap: the adapter
3979 * @mbox: mailbox to use for the FW command
3980 * @start: %true to enable the queues, %false to disable them
3981 * @pf: the PF owning the queues
3982 * @vf: the VF owning the queues
3983 * @iqid: ingress queue id
3984 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3985 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3987 * Starts or stops an ingress queue and its associated FLs, if any.
3989 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3990 unsigned int pf, unsigned int vf, unsigned int iqid,
3991 unsigned int fl0id, unsigned int fl1id)
3995 memset(&c, 0, sizeof(c));
3996 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3997 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3998 V_FW_IQ_CMD_VFN(vf));
3999 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4000 V_FW_IQ_CMD_IQSTOP(!start) |
4002 c.iqid = cpu_to_be16(iqid);
4003 c.fl0id = cpu_to_be16(fl0id);
4004 c.fl1id = cpu_to_be16(fl1id);
4005 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4009 * t4_iq_free - free an ingress queue and its FLs
4010 * @adap: the adapter
4011 * @mbox: mailbox to use for the FW command
4012 * @pf: the PF owning the queues
4013 * @vf: the VF owning the queues
4014 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4015 * @iqid: ingress queue id
4016 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4017 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4019 * Frees an ingress queue and its associated FLs, if any.
4021 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4022 unsigned int vf, unsigned int iqtype, unsigned int iqid,
4023 unsigned int fl0id, unsigned int fl1id)
4027 memset(&c, 0, sizeof(c));
4028 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4029 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4030 V_FW_IQ_CMD_VFN(vf));
4031 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4032 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4033 c.iqid = cpu_to_be16(iqid);
4034 c.fl0id = cpu_to_be16(fl0id);
4035 c.fl1id = cpu_to_be16(fl1id);
4036 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4040 * t4_eth_eq_free - free an Ethernet egress queue
4041 * @adap: the adapter
4042 * @mbox: mailbox to use for the FW command
4043 * @pf: the PF owning the queue
4044 * @vf: the VF owning the queue
4045 * @eqid: egress queue id
4047 * Frees an Ethernet egress queue.
4049 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4050 unsigned int vf, unsigned int eqid)
4052 struct fw_eq_eth_cmd c;
4054 memset(&c, 0, sizeof(c));
4055 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4056 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4057 V_FW_EQ_ETH_CMD_PFN(pf) |
4058 V_FW_EQ_ETH_CMD_VFN(vf));
4059 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4060 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4061 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4065 * t4_handle_fw_rpl - process a FW reply message
4066 * @adap: the adapter
4067 * @rpl: start of the FW message
4069 * Processes a FW message, such as link state change messages.
4071 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4073 u8 opcode = *(const u8 *)rpl;
4076 * This might be a port command ... this simplifies the following
4077 * conditionals ... We can get away with pre-dereferencing
4078 * action_to_len16 because it's in the first 16 bytes and all messages
4079 * will be at least that long.
4081 const struct fw_port_cmd *p = (const void *)rpl;
4082 unsigned int action =
4083 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4085 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4086 /* link/module state change message */
4087 unsigned int speed = 0, fc = 0, i;
4088 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4089 struct port_info *pi = NULL;
4090 struct link_config *lc;
4091 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4092 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4093 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4095 if (stat & F_FW_PORT_CMD_RXPAUSE)
4097 if (stat & F_FW_PORT_CMD_TXPAUSE)
4099 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4100 speed = ETH_SPEED_NUM_100M;
4101 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4102 speed = ETH_SPEED_NUM_1G;
4103 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4104 speed = ETH_SPEED_NUM_10G;
4105 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4106 speed = ETH_SPEED_NUM_25G;
4107 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4108 speed = ETH_SPEED_NUM_40G;
4109 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4110 speed = ETH_SPEED_NUM_100G;
4112 for_each_port(adap, i) {
4113 pi = adap2pinfo(adap, i);
4114 if (pi->tx_chan == chan)
4119 if (mod != pi->mod_type) {
4121 t4_os_portmod_changed(adap, i);
4123 if (link_ok != lc->link_ok || speed != lc->speed ||
4124 fc != lc->fc) { /* something changed */
4125 if (!link_ok && lc->link_ok) {
4126 static const char * const reason[] = {
4129 "Auto-negotiation Failure",
4131 "Insufficient Airflow",
4132 "Unable To Determine Reason",
4133 "No RX Signal Detected",
4136 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4138 dev_warn(adap, "Port %d link down, reason: %s\n",
4141 lc->link_ok = link_ok;
4144 lc->supported = be16_to_cpu(p->u.info.pcap);
4147 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4153 void t4_reset_link_config(struct adapter *adap, int idx)
4155 struct port_info *pi = adap2pinfo(adap, idx);
4156 struct link_config *lc = &pi->link_cfg;
4159 lc->requested_speed = 0;
4160 lc->requested_fc = 0;
4166 * init_link_config - initialize a link's SW state
4167 * @lc: structure holding the link state
4168 * @pcaps: link Port Capabilities
4169 * @acaps: link current Advertised Port Capabilities
4171 * Initializes the SW state maintained for each link, including the link's
4172 * capabilities and default speed/flow-control/autonegotiation settings.
4174 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4179 lc->supported = pcaps;
4180 lc->requested_speed = 0;
4182 lc->requested_fc = 0;
4186 * For Forward Error Control, we default to whatever the Firmware
4187 * tells us the Link is currently advertising.
4190 if (acaps & FW_PORT_CAP_FEC_RS)
4192 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4193 fec |= FEC_BASER_RS;
4194 if (acaps & FW_PORT_CAP_FEC_RESERVED)
4195 fec |= FEC_RESERVED;
4196 lc->requested_fec = fec;
4199 if (lc->supported & FW_PORT_CAP_ANEG) {
4200 lc->advertising = lc->supported & ADVERT_MASK;
4201 lc->autoneg = AUTONEG_ENABLE;
4203 lc->advertising = 0;
4204 lc->autoneg = AUTONEG_DISABLE;
4209 * t4_wait_dev_ready - wait till to reads of registers work
4211 * Right after the device is RESET is can take a small amount of time
4212 * for it to respond to register reads. Until then, all reads will
4213 * return either 0xff...ff or 0xee...ee. Return an error if reads
4214 * don't work within a reasonable time frame.
4216 static int t4_wait_dev_ready(struct adapter *adapter)
4220 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4222 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4226 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4227 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4230 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4236 u32 vendor_and_model_id;
4240 int t4_get_flash_params(struct adapter *adapter)
4243 * Table for non-Numonix supported flash parts. Numonix parts are left
4244 * to the preexisting well-tested code. All flash parts have 64KB
4247 static struct flash_desc supported_flash[] = {
4248 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
4253 unsigned int part, manufacturer;
4254 unsigned int density, size;
4257 * Issue a Read ID Command to the Flash part. We decode supported
4258 * Flash parts and their sizes from this. There's a newer Query
4259 * Command which can retrieve detailed geometry information but
4260 * many Flash parts don't support it.
4262 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4264 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4265 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4269 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4270 if (supported_flash[part].vendor_and_model_id == flashid) {
4271 adapter->params.sf_size =
4272 supported_flash[part].size_mb;
4273 adapter->params.sf_nsec =
4274 adapter->params.sf_size / SF_SEC_SIZE;
4279 manufacturer = flashid & 0xff;
4280 switch (manufacturer) {
4281 case 0x20: { /* Micron/Numonix */
4283 * This Density -> Size decoding table is taken from Micron
4286 density = (flashid >> 16) & 0xff;
4289 size = 1 << 20; /* 1MB */
4292 size = 1 << 21; /* 2MB */
4295 size = 1 << 22; /* 4MB */
4298 size = 1 << 23; /* 8MB */
4301 size = 1 << 24; /* 16MB */
4304 size = 1 << 25; /* 32MB */
4307 size = 1 << 26; /* 64MB */
4310 size = 1 << 27; /* 128MB */
4313 size = 1 << 28; /* 256MB */
4316 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4321 adapter->params.sf_size = size;
4322 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4326 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4332 * We should reject adapters with FLASHes which are too small. So, emit
4335 if (adapter->params.sf_size < FLASH_MIN_SIZE)
4336 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4337 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4342 static void set_pcie_completion_timeout(struct adapter *adapter,
4348 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4350 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4353 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4358 * t4_get_chip_type - Determine chip type from device ID
4359 * @adap: the adapter
4360 * @ver: adapter version
4362 int t4_get_chip_type(struct adapter *adap, int ver)
4364 enum chip_type chip = 0;
4365 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4367 /* Retrieve adapter's device ID */
4370 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4373 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4376 dev_err(adap, "Device %d is not supported\n",
4377 adap->params.pci.device_id);
4385 * t4_prep_adapter - prepare SW and HW for operation
4386 * @adapter: the adapter
4388 * Initialize adapter SW state for the various HW modules, set initial
4389 * values for some adapter tunables, take PHYs out of reset, and
4390 * initialize the MDIO interface.
4392 int t4_prep_adapter(struct adapter *adapter)
4397 ret = t4_wait_dev_ready(adapter);
4401 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4402 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4403 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4406 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4407 * ADAPTER (VERSION << 4 | REVISION)
4409 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4410 adapter->params.chip = 0;
4413 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4414 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4415 adapter->params.arch.mps_tcam_size =
4416 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4417 adapter->params.arch.mps_rplc_size = 128;
4418 adapter->params.arch.nchan = NCHAN;
4419 adapter->params.arch.vfcount = 128;
4422 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4423 adapter->params.arch.sge_fl_db = 0;
4424 adapter->params.arch.mps_tcam_size =
4425 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4426 adapter->params.arch.mps_rplc_size = 256;
4427 adapter->params.arch.nchan = 2;
4428 adapter->params.arch.vfcount = 256;
4431 dev_err(adapter, "%s: Device %d is not supported\n",
4432 __func__, adapter->params.pci.device_id);
4436 adapter->params.pci.vpd_cap_addr =
4437 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4439 ret = t4_get_flash_params(adapter);
4441 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4446 adapter->params.cim_la_size = CIMLA_SIZE;
4448 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4451 * Default port and clock for debugging in case we can't reach FW.
4453 adapter->params.nports = 1;
4454 adapter->params.portvec = 1;
4455 adapter->params.vpd.cclk = 50000;
4457 /* Set pci completion timeout value to 4 seconds. */
4458 set_pcie_completion_timeout(adapter, 0xd);
4463 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4464 * @adapter: the adapter
4465 * @qid: the Queue ID
4466 * @qtype: the Ingress or Egress type for @qid
4467 * @pbar2_qoffset: BAR2 Queue Offset
4468 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4470 * Returns the BAR2 SGE Queue Registers information associated with the
4471 * indicated Absolute Queue ID. These are passed back in return value
4472 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4473 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4475 * This may return an error which indicates that BAR2 SGE Queue
4476 * registers aren't available. If an error is not returned, then the
4477 * following values are returned:
4479 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4480 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4482 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4483 * require the "Inferred Queue ID" ability may be used. E.g. the
4484 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4485 * then these "Inferred Queue ID" register may not be used.
4487 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4488 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4489 unsigned int *pbar2_qid)
4491 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4492 u64 bar2_page_offset, bar2_qoffset;
4493 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4496 * T4 doesn't support BAR2 SGE Queue registers.
4498 if (is_t4(adapter->params.chip))
4502 * Get our SGE Page Size parameters.
4504 page_shift = adapter->params.sge.hps + 10;
4505 page_size = 1 << page_shift;
4508 * Get the right Queues per Page parameters for our Queue.
4510 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4511 adapter->params.sge.eq_qpp :
4512 adapter->params.sge.iq_qpp);
4513 qpp_mask = (1 << qpp_shift) - 1;
4516 * Calculate the basics of the BAR2 SGE Queue register area:
4517 * o The BAR2 page the Queue registers will be in.
4518 * o The BAR2 Queue ID.
4519 * o The BAR2 Queue ID Offset into the BAR2 page.
4521 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4522 bar2_qid = qid & qpp_mask;
4523 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4526 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4527 * hardware will infer the Absolute Queue ID simply from the writes to
4528 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4529 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4530 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4531 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4532 * from the BAR2 Page and BAR2 Queue ID.
4534 * One important censequence of this is that some BAR2 SGE registers
4535 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4536 * there. But other registers synthesize the SGE Queue ID purely
4537 * from the writes to the registers -- the Write Combined Doorbell
4538 * Buffer is a good example. These BAR2 SGE Registers are only
4539 * available for those BAR2 SGE Register areas where the SGE Absolute
4540 * Queue ID can be inferred from simple writes.
4542 bar2_qoffset = bar2_page_offset;
4543 bar2_qinferred = (bar2_qid_offset < page_size);
4544 if (bar2_qinferred) {
4545 bar2_qoffset += bar2_qid_offset;
4549 *pbar2_qoffset = bar2_qoffset;
4550 *pbar2_qid = bar2_qid;
4555 * t4_init_sge_params - initialize adap->params.sge
4556 * @adapter: the adapter
4558 * Initialize various fields of the adapter's SGE Parameters structure.
4560 int t4_init_sge_params(struct adapter *adapter)
4562 struct sge_params *sge_params = &adapter->params.sge;
4564 unsigned int s_hps, s_qpp;
4567 * Extract the SGE Page Size for our PF.
4569 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4570 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4572 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4575 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4577 s_qpp = (S_QUEUESPERPAGEPF0 +
4578 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4579 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4580 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4581 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4582 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4588 * t4_init_tp_params - initialize adap->params.tp
4589 * @adap: the adapter
4591 * Initialize various fields of the adapter's TP Parameters structure.
4593 int t4_init_tp_params(struct adapter *adap)
4598 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4599 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4600 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4602 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4603 for (chan = 0; chan < NCHAN; chan++)
4604 adap->params.tp.tx_modq[chan] = chan;
4607 * Cache the adapter's Compressed Filter Mode and global Incress
4610 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4611 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4612 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4613 &adap->params.tp.ingress_config, 1,
4614 A_TP_INGRESS_CONFIG);
4616 /* For T6, cache the adapter's compressed error vector
4617 * and passing outer header info for encapsulated packets.
4619 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4620 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4621 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4625 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4626 * shift positions of several elements of the Compressed Filter Tuple
4627 * for this adapter which we need frequently ...
4629 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4630 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4631 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4632 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4636 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4637 * represents the presense of an Outer VLAN instead of a VNIC ID.
4639 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4640 adap->params.tp.vnic_shift = -1;
4646 * t4_filter_field_shift - calculate filter field shift
4647 * @adap: the adapter
4648 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4650 * Return the shift position of a filter field within the Compressed
4651 * Filter Tuple. The filter field is specified via its selection bit
4652 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4654 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4656 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4660 if ((filter_mode & filter_sel) == 0)
4663 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4664 switch (filter_mode & sel) {
4666 field_shift += W_FT_FCOE;
4669 field_shift += W_FT_PORT;
4672 field_shift += W_FT_VNIC_ID;
4675 field_shift += W_FT_VLAN;
4678 field_shift += W_FT_TOS;
4681 field_shift += W_FT_PROTOCOL;
4684 field_shift += W_FT_ETHERTYPE;
4687 field_shift += W_FT_MACMATCH;
4690 field_shift += W_FT_MPSHITTYPE;
4692 case F_FRAGMENTATION:
4693 field_shift += W_FT_FRAGMENTATION;
4700 int t4_init_rss_mode(struct adapter *adap, int mbox)
4703 struct fw_rss_vi_config_cmd rvc;
4705 memset(&rvc, 0, sizeof(rvc));
4707 for_each_port(adap, i) {
4708 struct port_info *p = adap2pinfo(adap, i);
4710 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4711 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4712 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4713 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4714 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4717 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4722 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4726 struct fw_port_cmd c;
4728 memset(&c, 0, sizeof(c));
4730 for_each_port(adap, i) {
4731 unsigned int rss_size = 0;
4732 struct port_info *p = adap2pinfo(adap, i);
4734 while ((adap->params.portvec & (1 << j)) == 0)
4737 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4738 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4739 V_FW_PORT_CMD_PORTID(j));
4740 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4741 FW_PORT_ACTION_GET_PORT_INFO) |
4743 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4747 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4753 p->rss_size = rss_size;
4754 t4_os_set_hw_addr(adap, i, addr);
4756 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4757 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4758 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4759 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4760 p->mod_type = FW_PORT_MOD_TYPE_NA;
4762 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4763 be16_to_cpu(c.u.info.acap));