cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "t4_pci_id_tbl.h"
  61
  62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  63                          uint16_t nb_pkts)
  64 {
  65         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  66         uint16_t pkts_sent, pkts_remain;
  67         uint16_t total_sent = 0;
  68         int ret = 0;
  69
  70         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  71                        __func__, txq, tx_pkts, nb_pkts);
  72
  73         t4_os_lock(&txq->txq_lock);
  74         /* free up desc from already completed tx */
  75         reclaim_completed_tx(&txq->q);
  76         while (total_sent < nb_pkts) {
  77                 pkts_remain = nb_pkts - total_sent;
  78
  79                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  80                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
  81                                           nb_pkts);
  82                         if (ret < 0)
  83                                 break;
  84                 }
  85                 if (!pkts_sent)
  86                         break;
  87                 total_sent += pkts_sent;
  88                 /* reclaim as much as possible */
  89                 reclaim_completed_tx(&txq->q);
  90         }
  91
  92         t4_os_unlock(&txq->txq_lock);
  93         return total_sent;
  94 }
  95
  96 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  97                          uint16_t nb_pkts)
  98 {
  99         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 100         unsigned int work_done;
 101
 102         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 103                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 104
 105         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 106                 dev_err(adapter, "error in cxgbe poll\n");
 107
 108         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 109         return work_done;
 110 }
 111
 112 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 113                         struct rte_eth_dev_info *device_info)
 114 {
 115         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 116         struct adapter *adapter = pi->adapter;
 117         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 118
 119         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 120                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 121                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 122                 .nb_align = 1,
 123         };
 124
 125         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 126         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 127         device_info->max_rx_queues = max_queues;
 128         device_info->max_tx_queues = max_queues;
 129         device_info->max_mac_addrs = 1;
 130         /* XXX: For now we support one MAC/port */
 131         device_info->max_vfs = adapter->params.arch.vfcount;
 132         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 133
 134         device_info->rx_queue_offload_capa = 0UL;
 135         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 136
 137         device_info->tx_queue_offload_capa = 0UL;
 138         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 139
 140         device_info->reta_size = pi->rss_size;
 141         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 142         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 143
 144         device_info->rx_desc_lim = cxgbe_desc_lim;
 145         device_info->tx_desc_lim = cxgbe_desc_lim;
 146         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 147 }
 148
 149 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 150 {
 151         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 152         struct adapter *adapter = pi->adapter;
 153
 154         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 155                       1, -1, 1, -1, false);
 156 }
 157
 158 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 159 {
 160         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 161         struct adapter *adapter = pi->adapter;
 162
 163         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 164                       0, -1, 1, -1, false);
 165 }
 166
 167 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 168 {
 169         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 170         struct adapter *adapter = pi->adapter;
 171
 172         /* TODO: address filters ?? */
 173
 174         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 175                       -1, 1, 1, -1, false);
 176 }
 177
 178 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 179 {
 180         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 181         struct adapter *adapter = pi->adapter;
 182
 183         /* TODO: address filters ?? */
 184
 185         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 186                       -1, 0, 1, -1, false);
 187 }
 188
 189 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 190                           int wait_to_complete)
 191 {
 192         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 193         struct adapter *adapter = pi->adapter;
 194         struct sge *s = &adapter->sge;
 195         struct rte_eth_link new_link = { 0 };
 196         unsigned int i, work_done, budget = 32;
 197         u8 old_link = pi->link_cfg.link_ok;
 198
 199         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 200                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 201
 202                 /* Exit if link status changed or always forced up */
 203                 if (pi->link_cfg.link_ok != old_link || force_linkup(adapter))
 204                         break;
 205
 206                 if (!wait_to_complete)
 207                         break;
 208
 209                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 210         }
 211
 212         new_link.link_status = force_linkup(adapter) ?
 213                                ETH_LINK_UP : pi->link_cfg.link_ok;
 214         new_link.link_autoneg = pi->link_cfg.autoneg;
 215         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 216         new_link.link_speed = pi->link_cfg.speed;
 217
 218         return rte_eth_linkstatus_set(eth_dev, &new_link);
 219 }
 220
 221 /**
 222  * Set device link up.
 223  */
 224 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 225 {
 226         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 227         struct adapter *adapter = pi->adapter;
 228         unsigned int work_done, budget = 32;
 229         struct sge *s = &adapter->sge;
 230         int ret;
 231
 232         /* Flush all link events */
 233         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 234
 235         /* If link already up, nothing to do */
 236         if (pi->link_cfg.link_ok)
 237                 return 0;
 238
 239         ret = cxgbe_set_link_status(pi, true);
 240         if (ret)
 241                 return ret;
 242
 243         cxgbe_dev_link_update(dev, 1);
 244         return 0;
 245 }
 246
 247 /**
 248  * Set device link down.
 249  */
 250 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 251 {
 252         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 253         struct adapter *adapter = pi->adapter;
 254         unsigned int work_done, budget = 32;
 255         struct sge *s = &adapter->sge;
 256         int ret;
 257
 258         /* Flush all link events */
 259         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 260
 261         /* If link already down, nothing to do */
 262         if (!pi->link_cfg.link_ok)
 263                 return 0;
 264
 265         ret = cxgbe_set_link_status(pi, false);
 266         if (ret)
 267                 return ret;
 268
 269         cxgbe_dev_link_update(dev, 0);
 270         return 0;
 271 }
 272
 273 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 274 {
 275         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 276         struct adapter *adapter = pi->adapter;
 277         struct rte_eth_dev_info dev_info;
 278         int err;
 279         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 280
 281         cxgbe_dev_info_get(eth_dev, &dev_info);
 282
 283         /* Must accommodate at least ETHER_MIN_MTU */
 284         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 285                 return -EINVAL;
 286
 287         /* set to jumbo mode if needed */
 288         if (new_mtu > ETHER_MAX_LEN)
 289                 eth_dev->data->dev_conf.rxmode.offloads |=
 290                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 291         else
 292                 eth_dev->data->dev_conf.rxmode.offloads &=
 293                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 294
 295         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 296                             -1, -1, true);
 297         if (!err)
 298                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 299
 300         return err;
 301 }
 302
 303 /*
 304  * Stop device.
 305  */
 306 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 307 {
 308         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 309         struct adapter *adapter = pi->adapter;
 310
 311         CXGBE_FUNC_TRACE();
 312
 313         if (!(adapter->flags & FULL_INIT_DONE))
 314                 return;
 315
 316         cxgbe_down(pi);
 317
 318         /*
 319          *  We clear queues only if both tx and rx path of the port
 320          *  have been disabled
 321          */
 322         t4_sge_eth_clear_queues(pi);
 323 }
 324
 325 /* Start the device.
 326  * It returns 0 on success.
 327  */
 328 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 329 {
 330         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 331         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 332         struct adapter *adapter = pi->adapter;
 333         int err = 0, i;
 334
 335         CXGBE_FUNC_TRACE();
 336
 337         /*
 338          * If we don't have a connection to the firmware there's nothing we
 339          * can do.
 340          */
 341         if (!(adapter->flags & FW_OK)) {
 342                 err = -ENXIO;
 343                 goto out;
 344         }
 345
 346         if (!(adapter->flags & FULL_INIT_DONE)) {
 347                 err = cxgbe_up(adapter);
 348                 if (err < 0)
 349                         goto out;
 350         }
 351
 352         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 353                 eth_dev->data->scattered_rx = 1;
 354         else
 355                 eth_dev->data->scattered_rx = 0;
 356
 357         cxgbe_enable_rx_queues(pi);
 358
 359         err = setup_rss(pi);
 360         if (err)
 361                 goto out;
 362
 363         for (i = 0; i < pi->n_tx_qsets; i++) {
 364                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 365                 if (err)
 366                         goto out;
 367         }
 368
 369         for (i = 0; i < pi->n_rx_qsets; i++) {
 370                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 371                 if (err)
 372                         goto out;
 373         }
 374
 375         err = link_start(pi);
 376         if (err)
 377                 goto out;
 378
 379 out:
 380         return err;
 381 }
 382
 383 /*
 384  * Stop device: disable rx and tx functions to allow for reconfiguring.
 385  */
 386 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 387 {
 388         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 389         struct adapter *adapter = pi->adapter;
 390
 391         CXGBE_FUNC_TRACE();
 392
 393         if (!(adapter->flags & FULL_INIT_DONE))
 394                 return;
 395
 396         cxgbe_down(pi);
 397
 398         /*
 399          *  We clear queues only if both tx and rx path of the port
 400          *  have been disabled
 401          */
 402         t4_sge_eth_clear_queues(pi);
 403         eth_dev->data->scattered_rx = 0;
 404 }
 405
 406 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 407 {
 408         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 409         struct adapter *adapter = pi->adapter;
 410         int err;
 411
 412         CXGBE_FUNC_TRACE();
 413
 414         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 415                 err = setup_sge_fwevtq(adapter);
 416                 if (err)
 417                         return err;
 418                 adapter->flags |= FW_QUEUE_BOUND;
 419                 if (is_pf4(adapter)) {
 420                         err = setup_sge_ctrl_txq(adapter);
 421                         if (err)
 422                                 return err;
 423                 }
 424         }
 425
 426         err = cfg_queue_count(eth_dev);
 427         if (err)
 428                 return err;
 429
 430         return 0;
 431 }
 432
 433 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 434 {
 435         int ret;
 436         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 437                                   (eth_dev->data->tx_queues[tx_queue_id]);
 438
 439         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 440
 441         ret = t4_sge_eth_txq_start(txq);
 442         if (ret == 0)
 443                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 444
 445         return ret;
 446 }
 447
 448 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 449 {
 450         int ret;
 451         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 452                                   (eth_dev->data->tx_queues[tx_queue_id]);
 453
 454         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 455
 456         ret = t4_sge_eth_txq_stop(txq);
 457         if (ret == 0)
 458                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 459
 460         return ret;
 461 }
 462
 463 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 464                              uint16_t queue_idx, uint16_t nb_desc,
 465                              unsigned int socket_id,
 466                              const struct rte_eth_txconf *tx_conf __rte_unused)
 467 {
 468         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 469         struct adapter *adapter = pi->adapter;
 470         struct sge *s = &adapter->sge;
 471         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 472         int err = 0;
 473         unsigned int temp_nb_desc;
 474
 475         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 476                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 477                   socket_id, pi->first_qset);
 478
 479         /*  Free up the existing queue  */
 480         if (eth_dev->data->tx_queues[queue_idx]) {
 481                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 482                 eth_dev->data->tx_queues[queue_idx] = NULL;
 483         }
 484
 485         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 486
 487         /* Sanity Checking
 488          *
 489          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 490          */
 491         temp_nb_desc = nb_desc;
 492         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 493                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 494                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 495                          CXGBE_DEFAULT_TX_DESC_SIZE);
 496                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 497         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 498                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 499                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 500                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 501                 return -(EINVAL);
 502         }
 503
 504         txq->q.size = temp_nb_desc;
 505
 506         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 507                                    s->fw_evtq.cntxt_id, socket_id);
 508
 509         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 510                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 511         return err;
 512 }
 513
 514 void cxgbe_dev_tx_queue_release(void *q)
 515 {
 516         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 517
 518         if (txq) {
 519                 struct port_info *pi = (struct port_info *)
 520                                        (txq->eth_dev->data->dev_private);
 521                 struct adapter *adap = pi->adapter;
 522
 523                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 524                           __func__, pi->port_id, txq->q.cntxt_id);
 525
 526                 t4_sge_eth_txq_release(adap, txq);
 527         }
 528 }
 529
 530 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 531 {
 532         int ret;
 533         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 534         struct adapter *adap = pi->adapter;
 535         struct sge_rspq *q;
 536
 537         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 538                   __func__, pi->port_id, rx_queue_id);
 539
 540         q = eth_dev->data->rx_queues[rx_queue_id];
 541
 542         ret = t4_sge_eth_rxq_start(adap, q);
 543         if (ret == 0)
 544                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 545
 546         return ret;
 547 }
 548
 549 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 550 {
 551         int ret;
 552         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 553         struct adapter *adap = pi->adapter;
 554         struct sge_rspq *q;
 555
 556         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 557                   __func__, pi->port_id, rx_queue_id);
 558
 559         q = eth_dev->data->rx_queues[rx_queue_id];
 560         ret = t4_sge_eth_rxq_stop(adap, q);
 561         if (ret == 0)
 562                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 563
 564         return ret;
 565 }
 566
 567 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 568                              uint16_t queue_idx, uint16_t nb_desc,
 569                              unsigned int socket_id,
 570                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 571                              struct rte_mempool *mp)
 572 {
 573         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 574         struct adapter *adapter = pi->adapter;
 575         struct sge *s = &adapter->sge;
 576         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 577         int err = 0;
 578         int msi_idx = 0;
 579         unsigned int temp_nb_desc;
 580         struct rte_eth_dev_info dev_info;
 581         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 582
 583         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 584                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 585                   socket_id, mp);
 586
 587         cxgbe_dev_info_get(eth_dev, &dev_info);
 588
 589         /* Must accommodate at least ETHER_MIN_MTU */
 590         if ((pkt_len < dev_info.min_rx_bufsize) ||
 591             (pkt_len > dev_info.max_rx_pktlen)) {
 592                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 593                         __func__, dev_info.min_rx_bufsize,
 594                         dev_info.max_rx_pktlen);
 595                 return -EINVAL;
 596         }
 597
 598         /*  Free up the existing queue  */
 599         if (eth_dev->data->rx_queues[queue_idx]) {
 600                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 601                 eth_dev->data->rx_queues[queue_idx] = NULL;
 602         }
 603
 604         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 605
 606         /* Sanity Checking
 607          *
 608          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 609          */
 610         temp_nb_desc = nb_desc;
 611         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 612                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 613                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 614                          CXGBE_DEFAULT_RX_DESC_SIZE);
 615                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 616         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 617                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 618                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 619                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 620                 return -(EINVAL);
 621         }
 622
 623         rxq->rspq.size = temp_nb_desc;
 624         if ((&rxq->fl) != NULL)
 625                 rxq->fl.size = temp_nb_desc;
 626
 627         /* Set to jumbo mode if necessary */
 628         if (pkt_len > ETHER_MAX_LEN)
 629                 eth_dev->data->dev_conf.rxmode.offloads |=
 630                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 631         else
 632                 eth_dev->data->dev_conf.rxmode.offloads &=
 633                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 634
 635         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 636                                &rxq->fl, t4_ethrx_handler,
 637                                is_pf4(adapter) ?
 638                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 639                                queue_idx, socket_id);
 640
 641         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 642                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 643                   rxq->rspq.abs_id);
 644         return err;
 645 }
 646
 647 void cxgbe_dev_rx_queue_release(void *q)
 648 {
 649         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 650         struct sge_rspq *rq = &rxq->rspq;
 651
 652         if (rq) {
 653                 struct port_info *pi = (struct port_info *)
 654                                        (rq->eth_dev->data->dev_private);
 655                 struct adapter *adap = pi->adapter;
 656
 657                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 658                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 659
 660                 t4_sge_eth_rxq_release(adap, rxq);
 661         }
 662 }
 663
 664 /*
 665  * Get port statistics.
 666  */
 667 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 668                                 struct rte_eth_stats *eth_stats)
 669 {
 670         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 671         struct adapter *adapter = pi->adapter;
 672         struct sge *s = &adapter->sge;
 673         struct port_stats ps;
 674         unsigned int i;
 675
 676         cxgbe_stats_get(pi, &ps);
 677
 678         /* RX Stats */
 679         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 680                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 681                               ps.rx_trunc0 + ps.rx_trunc1 +
 682                               ps.rx_trunc2 + ps.rx_trunc3;
 683         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 684                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 685                               ps.rx_len_err;
 686
 687         /* TX Stats */
 688         eth_stats->opackets = ps.tx_frames;
 689         eth_stats->obytes   = ps.tx_octets;
 690         eth_stats->oerrors  = ps.tx_error_frames;
 691
 692         for (i = 0; i < pi->n_rx_qsets; i++) {
 693                 struct sge_eth_rxq *rxq =
 694                         &s->ethrxq[pi->first_qset + i];
 695
 696                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 697                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 698                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 699                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 700         }
 701
 702         for (i = 0; i < pi->n_tx_qsets; i++) {
 703                 struct sge_eth_txq *txq =
 704                         &s->ethtxq[pi->first_qset + i];
 705
 706                 eth_stats->q_opackets[i] = txq->stats.pkts;
 707                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 708                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 709         }
 710         return 0;
 711 }
 712
 713 /*
 714  * Reset port statistics.
 715  */
 716 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 717 {
 718         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 719         struct adapter *adapter = pi->adapter;
 720         struct sge *s = &adapter->sge;
 721         unsigned int i;
 722
 723         cxgbe_stats_reset(pi);
 724         for (i = 0; i < pi->n_rx_qsets; i++) {
 725                 struct sge_eth_rxq *rxq =
 726                         &s->ethrxq[pi->first_qset + i];
 727
 728                 rxq->stats.pkts = 0;
 729                 rxq->stats.rx_bytes = 0;
 730         }
 731         for (i = 0; i < pi->n_tx_qsets; i++) {
 732                 struct sge_eth_txq *txq =
 733                         &s->ethtxq[pi->first_qset + i];
 734
 735                 txq->stats.pkts = 0;
 736                 txq->stats.tx_bytes = 0;
 737                 txq->stats.mapping_err = 0;
 738         }
 739 }
 740
 741 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 742                                struct rte_eth_fc_conf *fc_conf)
 743 {
 744         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 745         struct link_config *lc = &pi->link_cfg;
 746         int rx_pause, tx_pause;
 747
 748         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 749         rx_pause = lc->fc & PAUSE_RX;
 750         tx_pause = lc->fc & PAUSE_TX;
 751
 752         if (rx_pause && tx_pause)
 753                 fc_conf->mode = RTE_FC_FULL;
 754         else if (rx_pause)
 755                 fc_conf->mode = RTE_FC_RX_PAUSE;
 756         else if (tx_pause)
 757                 fc_conf->mode = RTE_FC_TX_PAUSE;
 758         else
 759                 fc_conf->mode = RTE_FC_NONE;
 760         return 0;
 761 }
 762
 763 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 764                                struct rte_eth_fc_conf *fc_conf)
 765 {
 766         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 767         struct adapter *adapter = pi->adapter;
 768         struct link_config *lc = &pi->link_cfg;
 769
 770         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 771                 if (fc_conf->autoneg)
 772                         lc->requested_fc |= PAUSE_AUTONEG;
 773                 else
 774                         lc->requested_fc &= ~PAUSE_AUTONEG;
 775         }
 776
 777         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 778             (fc_conf->mode & RTE_FC_RX_PAUSE))
 779                 lc->requested_fc |= PAUSE_RX;
 780         else
 781                 lc->requested_fc &= ~PAUSE_RX;
 782
 783         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 784             (fc_conf->mode & RTE_FC_TX_PAUSE))
 785                 lc->requested_fc |= PAUSE_TX;
 786         else
 787                 lc->requested_fc &= ~PAUSE_TX;
 788
 789         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 790                              &pi->link_cfg);
 791 }
 792
 793 const uint32_t *
 794 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 795 {
 796         static const uint32_t ptypes[] = {
 797                 RTE_PTYPE_L3_IPV4,
 798                 RTE_PTYPE_L3_IPV6,
 799                 RTE_PTYPE_UNKNOWN
 800         };
 801
 802         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 803                 return ptypes;
 804         return NULL;
 805 }
 806
 807 /* Update RSS hash configuration
 808  */
 809 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 810                                      struct rte_eth_rss_conf *rss_conf)
 811 {
 812         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 813         struct adapter *adapter = pi->adapter;
 814         int err;
 815
 816         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 817         if (err)
 818                 return err;
 819
 820         pi->rss_hf = rss_conf->rss_hf;
 821
 822         if (rss_conf->rss_key) {
 823                 u32 key[10], mod_key[10];
 824                 int i, j;
 825
 826                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 827
 828                 for (i = 9, j = 0; i >= 0; i--, j++)
 829                         mod_key[j] = cpu_to_be32(key[i]);
 830
 831                 t4_write_rss_key(adapter, mod_key, -1);
 832         }
 833
 834         return 0;
 835 }
 836
 837 /* Get RSS hash configuration
 838  */
 839 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 840                                        struct rte_eth_rss_conf *rss_conf)
 841 {
 842         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 843         struct adapter *adapter = pi->adapter;
 844         u64 rss_hf = 0;
 845         u64 flags = 0;
 846         int err;
 847
 848         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 849                                     &flags, NULL);
 850
 851         if (err)
 852                 return err;
 853
 854         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 855                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
 856                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 857                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
 858         }
 859
 860         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 861                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
 862
 863         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 864                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 865                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 866                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 867         }
 868
 869         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 870                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
 871
 872         rss_conf->rss_hf = rss_hf;
 873
 874         if (rss_conf->rss_key) {
 875                 u32 key[10], mod_key[10];
 876                 int i, j;
 877
 878                 t4_read_rss_key(adapter, key);
 879
 880                 for (i = 9, j = 0; i >= 0; i--, j++)
 881                         mod_key[j] = be32_to_cpu(key[i]);
 882
 883                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 884         }
 885
 886         return 0;
 887 }
 888
 889 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 890 {
 891         RTE_SET_USED(dev);
 892         return EEPROMSIZE;
 893 }
 894
 895 /**
 896  * eeprom_ptov - translate a physical EEPROM address to virtual
 897  * @phys_addr: the physical EEPROM address
 898  * @fn: the PCI function number
 899  * @sz: size of function-specific area
 900  *
 901  * Translate a physical EEPROM address to virtual.  The first 1K is
 902  * accessed through virtual addresses starting at 31K, the rest is
 903  * accessed through virtual addresses starting at 0.
 904  *
 905  * The mapping is as follows:
 906  * [0..1K) -> [31K..32K)
 907  * [1K..1K+A) -> [31K-A..31K)
 908  * [1K+A..ES) -> [0..ES-A-1K)
 909  *
 910  * where A = @fn * @sz, and ES = EEPROM size.
 911  */
 912 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 913 {
 914         fn *= sz;
 915         if (phys_addr < 1024)
 916                 return phys_addr + (31 << 10);
 917         if (phys_addr < 1024 + fn)
 918                 return fn + phys_addr - 1024;
 919         if (phys_addr < EEPROMSIZE)
 920                 return phys_addr - 1024 - fn;
 921         if (phys_addr < EEPROMVSIZE)
 922                 return phys_addr - 1024;
 923         return -EINVAL;
 924 }
 925
 926 /* The next two routines implement eeprom read/write from physical addresses.
 927  */
 928 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 929 {
 930         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 931
 932         if (vaddr >= 0)
 933                 vaddr = t4_seeprom_read(adap, vaddr, v);
 934         return vaddr < 0 ? vaddr : 0;
 935 }
 936
 937 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 938 {
 939         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 940
 941         if (vaddr >= 0)
 942                 vaddr = t4_seeprom_write(adap, vaddr, v);
 943         return vaddr < 0 ? vaddr : 0;
 944 }
 945
 946 #define EEPROM_MAGIC 0x38E2F10C
 947
 948 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 949                             struct rte_dev_eeprom_info *e)
 950 {
 951         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 952         struct adapter *adapter = pi->adapter;
 953         u32 i, err = 0;
 954         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 955
 956         if (!buf)
 957                 return -ENOMEM;
 958
 959         e->magic = EEPROM_MAGIC;
 960         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 961                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 962
 963         if (!err)
 964                 rte_memcpy(e->data, buf + e->offset, e->length);
 965         rte_free(buf);
 966         return err;
 967 }
 968
 969 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 970                             struct rte_dev_eeprom_info *eeprom)
 971 {
 972         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 973         struct adapter *adapter = pi->adapter;
 974         u8 *buf;
 975         int err = 0;
 976         u32 aligned_offset, aligned_len, *p;
 977
 978         if (eeprom->magic != EEPROM_MAGIC)
 979                 return -EINVAL;
 980
 981         aligned_offset = eeprom->offset & ~3;
 982         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 983
 984         if (adapter->pf > 0) {
 985                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 986
 987                 if (aligned_offset < start ||
 988                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 989                         return -EPERM;
 990         }
 991
 992         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 993                 /* RMW possibly needed for first or last words.
 994                  */
 995                 buf = rte_zmalloc(NULL, aligned_len, 0);
 996                 if (!buf)
 997                         return -ENOMEM;
 998                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
 999                 if (!err && aligned_len > 4)
1000                         err = eeprom_rd_phys(adapter,
1001                                              aligned_offset + aligned_len - 4,
1002                                              (u32 *)&buf[aligned_len - 4]);
1003                 if (err)
1004                         goto out;
1005                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1006                            eeprom->length);
1007         } else {
1008                 buf = eeprom->data;
1009         }
1010
1011         err = t4_seeprom_wp(adapter, false);
1012         if (err)
1013                 goto out;
1014
1015         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1016                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1017                 aligned_offset += 4;
1018         }
1019
1020         if (!err)
1021                 err = t4_seeprom_wp(adapter, true);
1022 out:
1023         if (buf != eeprom->data)
1024                 rte_free(buf);
1025         return err;
1026 }
1027
1028 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1029 {
1030         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1031         struct adapter *adapter = pi->adapter;
1032
1033         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1034 }
1035
1036 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1037                           struct rte_dev_reg_info *regs)
1038 {
1039         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1040         struct adapter *adapter = pi->adapter;
1041
1042         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1043                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1044                 (1 << 16);
1045
1046         if (regs->data == NULL) {
1047                 regs->length = cxgbe_get_regs_len(eth_dev);
1048                 regs->width = sizeof(uint32_t);
1049
1050                 return 0;
1051         }
1052
1053         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1054
1055         return 0;
1056 }
1057
1058 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1059 {
1060         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1061         int ret;
1062
1063         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1064         if (ret < 0) {
1065                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1066                         ret);
1067                 return ret;
1068         }
1069         pi->xact_addr_filt = ret;
1070         return 0;
1071 }
1072
1073 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1074         .dev_start              = cxgbe_dev_start,
1075         .dev_stop               = cxgbe_dev_stop,
1076         .dev_close              = cxgbe_dev_close,
1077         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1078         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1079         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1080         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1081         .dev_configure          = cxgbe_dev_configure,
1082         .dev_infos_get          = cxgbe_dev_info_get,
1083         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1084         .link_update            = cxgbe_dev_link_update,
1085         .dev_set_link_up        = cxgbe_dev_set_link_up,
1086         .dev_set_link_down      = cxgbe_dev_set_link_down,
1087         .mtu_set                = cxgbe_dev_mtu_set,
1088         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1089         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1090         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1091         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1092         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1093         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1094         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1095         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1096         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1097         .stats_get              = cxgbe_dev_stats_get,
1098         .stats_reset            = cxgbe_dev_stats_reset,
1099         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1100         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1101         .get_eeprom_length      = cxgbe_get_eeprom_length,
1102         .get_eeprom             = cxgbe_get_eeprom,
1103         .set_eeprom             = cxgbe_set_eeprom,
1104         .get_reg                = cxgbe_get_regs,
1105         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1106         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1107         .mac_addr_set           = cxgbe_mac_addr_set,
1108 };
1109
1110 /*
1111  * Initialize driver
1112  * It returns 0 on success.
1113  */
1114 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1115 {
1116         struct rte_pci_device *pci_dev;
1117         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1118         struct adapter *adapter = NULL;
1119         char name[RTE_ETH_NAME_MAX_LEN];
1120         int err = 0;
1121
1122         CXGBE_FUNC_TRACE();
1123
1124         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1125         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1126         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1127         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1128
1129         /* for secondary processes, we attach to ethdevs allocated by primary
1130          * and do minimal initialization.
1131          */
1132         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1133                 int i;
1134
1135                 for (i = 1; i < MAX_NPORTS; i++) {
1136                         struct rte_eth_dev *rest_eth_dev;
1137                         char namei[RTE_ETH_NAME_MAX_LEN];
1138
1139                         snprintf(namei, sizeof(namei), "%s_%d",
1140                                  pci_dev->device.name, i);
1141                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1142                         if (rest_eth_dev) {
1143                                 rest_eth_dev->device = &pci_dev->device;
1144                                 rest_eth_dev->dev_ops =
1145                                         eth_dev->dev_ops;
1146                                 rest_eth_dev->rx_pkt_burst =
1147                                         eth_dev->rx_pkt_burst;
1148                                 rest_eth_dev->tx_pkt_burst =
1149                                         eth_dev->tx_pkt_burst;
1150                                 rte_eth_dev_probing_finish(rest_eth_dev);
1151                         }
1152                 }
1153                 return 0;
1154         }
1155
1156         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1157         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1158         if (!adapter)
1159                 return -1;
1160
1161         adapter->use_unpacked_mode = 1;
1162         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1163         if (!adapter->regs) {
1164                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1165                 err = -ENOMEM;
1166                 goto out_free_adapter;
1167         }
1168         adapter->pdev = pci_dev;
1169         adapter->eth_dev = eth_dev;
1170         pi->adapter = adapter;
1171
1172         err = cxgbe_probe(adapter);
1173         if (err) {
1174                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1175                         __func__, err);
1176                 goto out_free_adapter;
1177         }
1178
1179         return 0;
1180
1181 out_free_adapter:
1182         rte_free(adapter);
1183         return err;
1184 }
1185
1186 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1187 {
1188         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1189         struct adapter *adap = pi->adapter;
1190
1191         /* Free up other ports and all resources */
1192         cxgbe_close(adap);
1193         return 0;
1194 }
1195
1196 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1197         struct rte_pci_device *pci_dev)
1198 {
1199         return rte_eth_dev_pci_generic_probe(pci_dev,
1200                 sizeof(struct port_info), eth_cxgbe_dev_init);
1201 }
1202
1203 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1204 {
1205         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1206 }
1207
1208 static struct rte_pci_driver rte_cxgbe_pmd = {
1209         .id_table = cxgb4_pci_tbl,
1210         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1211         .probe = eth_cxgbe_pci_probe,
1212         .remove = eth_cxgbe_pci_remove,
1213 };
1214
1215 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1216 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1217 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1218 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1219                               CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1220                               CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");