1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2019 Intel Corporation
4 Intel(R) FPGA 5GNR FEC Poll Mode Driver
5 =======================================
7 The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
8 LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA
9 based Vista Creek device.
14 FPGA 5GNR FEC PMD supports the following features:
16 - LDPC Encode in the DL
17 - LDPC Decode in the UL
18 - 8 VFs per PF (physical device)
19 - Maximum of 32 UL queues per VF
20 - Maximum of 32 DL queues per VF
21 - PCIe Gen-3 x8 Interface
25 FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
27 * For the LDPC encode operation:
28 - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
29 - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
31 * For the LDPC decode operation:
32 - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
33 - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
34 - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
35 - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
36 - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
37 - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
38 - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
39 - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
40 - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
46 FPGA 5GNR FEC does not support the following:
48 - Scatter-Gather function
54 Section 3 of the DPDK manual provides instructions on installing and compiling DPDK. The
55 default set of bbdev compile flags may be found in config/common_base, where for example
56 the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,
59 DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
60 The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
61 hugepage configuration of a server may be examined using:
63 .. code-block:: console
65 grep Huge* /proc/meminfo
71 When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
73 .. code-block:: console
75 sudo lspci -vd8086:0d8f
77 The physical and virtual functions are compatible with Linux UIO drivers:
78 ``vfio`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs
79 to be bound to one of these linux drivers through DPDK.
85 Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
86 ``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
88 The igb_uio driver may be bound to the PF PCI device using one of three methods:
91 1. PCI functions (physical or virtual, depending on the use case) can be bound to
92 the UIO driver by repeating this command for every function.
94 .. code-block:: console
97 echo "8086 0d8f" > /sys/bus/pci/drivers/igb_uio/new_id
101 2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
103 .. code-block:: console
105 cd <dpdk-top-level-directory>
106 ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
108 where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d8f
111 3. A third way to bind is to use ``dpdk-setup.sh`` tool
113 .. code-block:: console
115 cd <dpdk-top-level-directory>
116 ./usertools/dpdk-setup.sh
118 select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
120 select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
122 select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
125 In the same way the FPGA 5GNR FEC PF can be bound with vfio, but vfio driver does not
126 support SR-IOV configuration right out of the box, so it will need to be patched.
129 Enable Virtual Functions
130 ~~~~~~~~~~~~~~~~~~~~~~~~
132 Now, it should be visible in the printouts that PCI PF is under igb_uio control
133 "``Kernel driver in use: igb_uio``"
135 To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
137 .. code-block:: console
139 cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
141 where 0000\:<b>\:<d>.<f> is the PCI device ID
144 To enable VFs via igb_uio, echo the number of virtual functions intended to
145 enable to ``max_vfs`` file..
147 .. code-block:: console
149 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
152 Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
153 way it was done with the physical function previously.
155 Enabling SR-IOV via vfio driver is pretty much the same, except that the file
158 .. code-block:: console
160 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
163 Configure the VFs through PF
164 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
166 The PCI virtual functions must be configured before working or getting assigned
167 to VMs/Containers. The configuration involves allocating the number of hardware
168 queues, priorities, load balance, bandwidth and other settings necessary for the
169 device to perform FEC functions.
171 This configuration needs to be executed at least once after reboot or PCI FLR and can
172 be achieved by using the function ``rte_fpga_5gnr_fec_configure()``, which sets up the
173 parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
177 struct rte_fpga_5gnr_fec_conf {
179 uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
180 uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
181 uint8_t ul_bandwidth;
182 uint8_t dl_bandwidth;
183 uint8_t ul_load_balance;
184 uint8_t dl_load_balance;
185 uint16_t flr_time_out;
188 - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
189 VFs are mutually exclusive and cannot run simultaneously.
190 Set to 1 for PF mode enabled.
191 If PF mode is enabled all queues available in the device are assigned
192 exclusively to PF and 0 queues given to VFs.
194 - ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
196 - ``*l_bandwidth``: in case of congestion on PCIe interface. The device
197 allocates different bandwidth to UL and DL. The weight is configured by this
198 setting. The unit of weight is 3 code blocks. For example, if the code block
199 cbps (code block per second) ratio between UL and DL is 12:1, then the
200 configuration value should be set to 36:3. The schedule algorithm is based
201 on code block regardless the length of each block.
203 - ``*l_load_balance``: hardware queues are load-balanced in a round-robin
204 fashion. Queues get filled first-in first-out until they reach a pre-defined
205 watermark level, if exceeded, they won't get assigned new code blocks..
206 This watermark is defined by this setting.
208 If all hardware queues exceeds the watermark, no code blocks will be
209 streamed in from UL/DL code block FIFO.
211 - ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
212 time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
213 the FLR time out then set this setting to 0x262=610.
216 An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown
221 struct rte_fpga_5gnr_fec_conf conf;
224 memset(&conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));
227 for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
228 conf.vf_ul_queues_number[i] = 4;
229 conf.vf_dl_queues_number[i] = 4;
231 conf.ul_bandwidth = 12;
232 conf.dl_bandwidth = 5;
233 conf.dl_load_balance = 64;
234 conf.ul_load_balance = 64;
237 ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
238 TEST_ASSERT_SUCCESS(ret,
239 "Failed to configure 4G FPGA PF for bbdev %s",
246 BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
247 the functionality of FPGA 5GNR FEC encode and decode, depending on the device's
248 capabilities. The test application is located under app->test-bbdev folder and has the
251 .. code-block:: console
253 "-p", "--testapp-path": specifies path to the bbdev test app.
254 "-e", "--eal-params" : EAL arguments which are passed to the test app.
255 "-t", "--timeout" : Timeout in seconds (default=300).
256 "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
257 "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
258 "-n", "--num-ops" : Number of operations to process on device (default=32).
259 "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
260 "-l", "--num-lcores" : Number of lcores to run (default=16).
261 "-i", "--init-device" : Initialise PF device with default values.
264 To execute the test application tool using simple decode or encode data,
265 type one of the following:
267 .. code-block:: console
269 ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
270 ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
273 The test application ``test-bbdev.py``, supports the ability to configure the PF device with
274 a default set of values, if the "-i" or "- -init-device" option is included. The default values
275 are defined in test_bbdev_perf.c as:
277 - VF_UL_QUEUE_VALUE 4
278 - VF_DL_QUEUE_VALUE 4
281 - UL_LOAD_BALANCE 128
282 - DL_LOAD_BALANCE 128
289 In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
290 a range of additional tests under the test_vectors folder, which may be useful. The results
291 of these tests will depend on the FPGA 5GNR FEC capabilities.