1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2019 Intel Corporation
4 Intel(R) FPGA LTE FEC Poll Mode Driver
5 ======================================
7 The BBDEV FPGA LTE FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
8 Turbo Encode / Decode LTE wireless acceleration function, using Intel's PCI-e and FPGA
9 based Vista Creek device.
14 FPGA LTE FEC PMD supports the following features:
16 - Turbo Encode in the DL with total throughput of 4.5 Gbits/s
17 - Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations
18 - 8 VFs per PF (physical device)
19 - Maximum of 32 UL queues per VF
20 - Maximum of 32 DL queues per VF
21 - PCIe Gen-3 x8 Interface
26 FPGA LTE FEC PMD supports the following BBDEV capabilities:
28 * For the turbo encode operation:
29 - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
30 - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass
31 - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts
34 * For the turbo decode operation:
35 - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
36 - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave
37 - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts
38 - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported
39 - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding
45 FPGA LTE FEC does not support the following:
47 - Scatter-Gather function
53 Section 3 of the DPDK manual provides instructions on installing and compiling DPDK. The
54 default set of bbdev compile flags may be found in config/common_base, where for example
55 the flag to build the FPGA LTE FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC``, is already
58 DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
59 The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
60 hugepage configuration of a server may be examined using:
62 .. code-block:: console
64 grep Huge* /proc/meminfo
70 When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
72 .. code-block:: console
74 sudo lspci -vd1172:5052
76 The physical and virtual functions are compatible with Linux UIO drivers:
77 ``vfio`` and ``igb_uio``. However, in order to work the FPGA LTE FEC device firstly needs
78 to be bound to one of these linux drivers through DPDK.
84 Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
85 ``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
87 The igb_uio driver may be bound to the PF PCI device using one of three methods:
90 1. PCI functions (physical or virtual, depending on the use case) can be bound to
91 the UIO driver by repeating this command for every function.
93 .. code-block:: console
96 echo "1172 5052" > /sys/bus/pci/drivers/igb_uio/new_id
100 2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
102 .. code-block:: console
104 cd <dpdk-top-level-directory>
105 ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
107 where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd1172:
110 3. A third way to bind is to use ``dpdk-setup.sh`` tool
112 .. code-block:: console
114 cd <dpdk-top-level-directory>
115 ./usertools/dpdk-setup.sh
117 select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
119 select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
121 select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
124 In the same way the FPGA LTE FEC PF can be bound with vfio, but vfio driver does not
125 support SR-IOV configuration right out of the box, so it will need to be patched.
128 Enable Virtual Functions
129 ~~~~~~~~~~~~~~~~~~~~~~~~
131 Now, it should be visible in the printouts that PCI PF is under igb_uio control
132 "``Kernel driver in use: igb_uio``"
134 To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
136 .. code-block:: console
138 cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
140 where 0000\:<b>\:<d>.<f> is the PCI device ID
143 To enable VFs via igb_uio, echo the number of virtual functions intended to
144 enable to ``max_vfs`` file..
146 .. code-block:: console
148 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
151 Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
152 way it was done with the physical function previously.
154 Enabling SR-IOV via vfio driver is pretty much the same, except that the file
157 .. code-block:: console
159 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
162 Configure the VFs through PF
163 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
165 The PCI virtual functions must be configured before working or getting assigned
166 to VMs/Containers. The configuration involves allocating the number of hardware
167 queues, priorities, load balance, bandwidth and other settings necessary for the
168 device to perform FEC functions.
170 This configuration needs to be executed at least once after reboot or PCI FLR and can
171 be achieved by using the function ``rte_fpga_lte_fec_configure()``, which sets up the
172 parameters defined in ``rte_fpga_lte_fec_conf`` structure:
176 struct rte_fpga_lte_fec_conf {
178 uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS];
179 uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS];
180 uint8_t ul_bandwidth;
181 uint8_t dl_bandwidth;
182 uint8_t ul_load_balance;
183 uint8_t dl_load_balance;
184 uint16_t flr_time_out;
187 - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
188 VFs are mutually exclusive and cannot run simultaneously.
189 Set to 1 for PF mode enabled.
190 If PF mode is enabled all queues available in the device are assigned
191 exclusively to PF and 0 queues given to VFs.
193 - ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
195 - ``*l_bandwidth``: in case of congestion on PCIe interface. The device
196 allocates different bandwidth to UL and DL. The weight is configured by this
197 setting. The unit of weight is 3 code blocks. For example, if the code block
198 cbps (code block per second) ratio between UL and DL is 12:1, then the
199 configuration value should be set to 36:3. The schedule algorithm is based
200 on code block regardless the length of each block.
202 - ``*l_load_balance``: hardware queues are load-balanced in a round-robin
203 fashion. Queues get filled first-in first-out until they reach a pre-defined
204 watermark level, if exceeded, they won't get assigned new code blocks..
205 This watermark is defined by this setting.
207 If all hardware queues exceeds the watermark, no code blocks will be
208 streamed in from UL/DL code block FIFO.
210 - ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
211 time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
212 the FLR time out then set this setting to 0x262=610.
215 An example configuration code calling the function ``rte_fpga_lte_fec_configure()`` is shown
220 struct rte_fpga_lte_fec_conf conf;
223 memset(&conf, 0, sizeof(struct rte_fpga_lte_fec_conf));
226 for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {
227 conf.vf_ul_queues_number[i] = 4;
228 conf.vf_dl_queues_number[i] = 4;
230 conf.ul_bandwidth = 12;
231 conf.dl_bandwidth = 5;
232 conf.dl_load_balance = 64;
233 conf.ul_load_balance = 64;
236 ret = rte_fpga_lte_fec_configure(info->dev_name, &conf);
237 TEST_ASSERT_SUCCESS(ret,
238 "Failed to configure 4G FPGA PF for bbdev %s",
245 BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
246 the functionality of FPGA LTE FEC turbo encode and turbo decode, depending on the device's
247 capabilities. The test application is located under app->test-bbdev folder and has the
250 .. code-block:: console
252 "-p", "--testapp-path": specifies path to the bbdev test app.
253 "-e", "--eal-params" : EAL arguments which are passed to the test app.
254 "-t", "--timeout" : Timeout in seconds (default=300).
255 "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
256 "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
257 "-n", "--num-ops" : Number of operations to process on device (default=32).
258 "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
259 "-l", "--num-lcores" : Number of lcores to run (default=16).
260 "-i", "--init-device" : Initialise PF device with default values.
263 To execute the test application tool using simple turbo decode or turbo encode data,
264 type one of the following:
266 .. code-block:: console
268 ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_dec_default.data
269 ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_enc_default.data
272 The test application ``test-bbdev.py``, supports the ability to configure the PF device with
273 a default set of values, if the "-i" or "- -init-device" option is included. The default values
274 are defined in test_bbdev_perf.c as:
276 - VF_UL_QUEUE_VALUE 4
277 - VF_DL_QUEUE_VALUE 4
280 - UL_LOAD_BALANCE 128
281 - DL_LOAD_BALANCE 128
288 In addition to the simple turbo decoder and turbo encoder tests, bbdev also provides
289 a range of additional tests under the test_vectors folder, which may be useful. The results
290 of these tests will depend on the FPGA LTE FEC capabilities:
292 * turbo decoder tests:
293 - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data``
294 - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_low_snr.data``
295 - ``turbo_dec_c1_k6144_r0_e34560_negllr.data``
296 - ``turbo_dec_c1_k6144_r0_e34560_sbd_negllr.data``
297 - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data``
298 - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data``
301 * turbo encoder tests:
302 - ``turbo_enc_c1_k40_r0_e1190_rm.data``
303 - ``turbo_enc_c1_k40_r0_e1194_rm.data``
304 - ``turbo_enc_c1_k40_r0_e1196_rm.data``
305 - ``turbo_enc_c1_k40_r0_e272_rm.data``
306 - ``turbo_enc_c1_k6144_r0_e18444.data``
307 - ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data``
308 - ``turbo_enc_c2_k5952_r0_e17868_crc24b.data``
309 - ``turbo_enc_c3_k4800_r2_e14412_crc24b.data``
310 - ``turbo_enc_c4_k4800_r2_e14412_crc24b.data``