1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2019 Intel Corporation
4 Intel(R) FPGA LTE FEC Poll Mode Driver
5 ======================================
7 The BBDEV FPGA LTE FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
8 Turbo Encode / Decode LTE wireless acceleration function, using Intel's PCI-e and FPGA
9 based Vista Creek device.
14 FPGA LTE FEC PMD supports the following features:
16 - Turbo Encode in the DL with total throughput of 4.5 Gbits/s
17 - Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations
18 - 8 VFs per PF (physical device)
19 - Maximum of 32 UL queues per VF
20 - Maximum of 32 DL queues per VF
21 - PCIe Gen-3 x8 Interface
26 FPGA LTE FEC PMD supports the following BBDEV capabilities:
28 * For the turbo encode operation:
29 - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
30 - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass
31 - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts
34 * For the turbo decode operation:
35 - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
36 - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave
37 - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts
38 - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported
39 - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding
45 FPGA LTE FEC does not support the following:
47 - Scatter-Gather function
53 Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
55 DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
56 The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
57 hugepage configuration of a server may be examined using:
59 .. code-block:: console
61 grep Huge* /proc/meminfo
67 When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
69 .. code-block:: console
71 sudo lspci -vd1172:5052
73 The physical and virtual functions are compatible with Linux UIO drivers:
74 ``vfio`` and ``igb_uio``. However, in order to work the FPGA LTE FEC device firstly needs
75 to be bound to one of these linux drivers through DPDK.
81 Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
82 ``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
84 The igb_uio driver may be bound to the PF PCI device using one of three methods:
87 1. PCI functions (physical or virtual, depending on the use case) can be bound to
88 the UIO driver by repeating this command for every function.
90 .. code-block:: console
93 echo "1172 5052" > /sys/bus/pci/drivers/igb_uio/new_id
97 2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
99 .. code-block:: console
101 cd <dpdk-top-level-directory>
102 ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
104 where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd1172:
107 3. A third way to bind is to use ``dpdk-setup.sh`` tool
109 .. code-block:: console
111 cd <dpdk-top-level-directory>
112 ./usertools/dpdk-setup.sh
114 select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
116 select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
118 select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
121 In the same way the FPGA LTE FEC PF can be bound with vfio, but vfio driver does not
122 support SR-IOV configuration right out of the box, so it will need to be patched.
125 Enable Virtual Functions
126 ~~~~~~~~~~~~~~~~~~~~~~~~
128 Now, it should be visible in the printouts that PCI PF is under igb_uio control
129 "``Kernel driver in use: igb_uio``"
131 To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
133 .. code-block:: console
135 cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
137 where 0000\:<b>\:<d>.<f> is the PCI device ID
140 To enable VFs via igb_uio, echo the number of virtual functions intended to
141 enable to ``max_vfs`` file..
143 .. code-block:: console
145 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
148 Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
149 way it was done with the physical function previously.
151 Enabling SR-IOV via vfio driver is pretty much the same, except that the file
154 .. code-block:: console
156 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
159 Configure the VFs through PF
160 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
162 The PCI virtual functions must be configured before working or getting assigned
163 to VMs/Containers. The configuration involves allocating the number of hardware
164 queues, priorities, load balance, bandwidth and other settings necessary for the
165 device to perform FEC functions.
167 This configuration needs to be executed at least once after reboot or PCI FLR and can
168 be achieved by using the function ``rte_fpga_lte_fec_configure()``, which sets up the
169 parameters defined in ``rte_fpga_lte_fec_conf`` structure:
173 struct rte_fpga_lte_fec_conf {
175 uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS];
176 uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS];
177 uint8_t ul_bandwidth;
178 uint8_t dl_bandwidth;
179 uint8_t ul_load_balance;
180 uint8_t dl_load_balance;
181 uint16_t flr_time_out;
184 - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
185 VFs are mutually exclusive and cannot run simultaneously.
186 Set to 1 for PF mode enabled.
187 If PF mode is enabled all queues available in the device are assigned
188 exclusively to PF and 0 queues given to VFs.
190 - ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
192 - ``*l_bandwidth``: in case of congestion on PCIe interface. The device
193 allocates different bandwidth to UL and DL. The weight is configured by this
194 setting. The unit of weight is 3 code blocks. For example, if the code block
195 cbps (code block per second) ratio between UL and DL is 12:1, then the
196 configuration value should be set to 36:3. The schedule algorithm is based
197 on code block regardless the length of each block.
199 - ``*l_load_balance``: hardware queues are load-balanced in a round-robin
200 fashion. Queues get filled first-in first-out until they reach a pre-defined
201 watermark level, if exceeded, they won't get assigned new code blocks..
202 This watermark is defined by this setting.
204 If all hardware queues exceeds the watermark, no code blocks will be
205 streamed in from UL/DL code block FIFO.
207 - ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
208 time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
209 the FLR time out then set this setting to 0x262=610.
212 An example configuration code calling the function ``rte_fpga_lte_fec_configure()`` is shown
217 struct rte_fpga_lte_fec_conf conf;
220 memset(&conf, 0, sizeof(struct rte_fpga_lte_fec_conf));
223 for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {
224 conf.vf_ul_queues_number[i] = 4;
225 conf.vf_dl_queues_number[i] = 4;
227 conf.ul_bandwidth = 12;
228 conf.dl_bandwidth = 5;
229 conf.dl_load_balance = 64;
230 conf.ul_load_balance = 64;
233 ret = rte_fpga_lte_fec_configure(info->dev_name, &conf);
234 TEST_ASSERT_SUCCESS(ret,
235 "Failed to configure 4G FPGA PF for bbdev %s",
242 BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
243 the functionality of FPGA LTE FEC turbo encode and turbo decode, depending on the device's
244 capabilities. The test application is located under app->test-bbdev folder and has the
247 .. code-block:: console
249 "-p", "--testapp-path": specifies path to the bbdev test app.
250 "-e", "--eal-params" : EAL arguments which are passed to the test app.
251 "-t", "--timeout" : Timeout in seconds (default=300).
252 "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
253 "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
254 "-n", "--num-ops" : Number of operations to process on device (default=32).
255 "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
256 "-l", "--num-lcores" : Number of lcores to run (default=16).
257 "-i", "--init-device" : Initialise PF device with default values.
260 To execute the test application tool using simple turbo decode or turbo encode data,
261 type one of the following:
263 .. code-block:: console
265 ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_dec_default.data
266 ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_enc_default.data
269 The test application ``test-bbdev.py``, supports the ability to configure the PF device with
270 a default set of values, if the "-i" or "- -init-device" option is included. The default values
271 are defined in test_bbdev_perf.c as:
273 - VF_UL_QUEUE_VALUE 4
274 - VF_DL_QUEUE_VALUE 4
277 - UL_LOAD_BALANCE 128
278 - DL_LOAD_BALANCE 128
285 In addition to the simple turbo decoder and turbo encoder tests, bbdev also provides
286 a range of additional tests under the test_vectors folder, which may be useful. The results
287 of these tests will depend on the FPGA LTE FEC capabilities:
289 * turbo decoder tests:
290 - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data``
291 - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_low_snr.data``
292 - ``turbo_dec_c1_k6144_r0_e34560_negllr.data``
293 - ``turbo_dec_c1_k6144_r0_e34560_sbd_negllr.data``
294 - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data``
295 - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data``
298 * turbo encoder tests:
299 - ``turbo_enc_c1_k40_r0_e1190_rm.data``
300 - ``turbo_enc_c1_k40_r0_e1194_rm.data``
301 - ``turbo_enc_c1_k40_r0_e1196_rm.data``
302 - ``turbo_enc_c1_k40_r0_e272_rm.data``
303 - ``turbo_enc_c1_k6144_r0_e18444.data``
304 - ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data``
305 - ``turbo_enc_c2_k5952_r0_e17868_crc24b.data``
306 - ``turbo_enc_c3_k4800_r2_e14412_crc24b.data``
307 - ``turbo_enc_c4_k4800_r2_e14412_crc24b.data``