1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2021 Marvell.
4 Marvell cnxk Crypto Poll Mode Driver
5 ====================================
7 The cnxk crypto poll mode driver provides support for offloading
8 cryptographic operations to cryptographic accelerator units on the
9 **Marvell OCTEON cnxk** SoC family.
11 The cnxk crypto PMD code is organized into different sets of files.
12 The file names starting with cn9k and cn10k provides support for CN9XX
13 and CN10XX respectively. The common code between the SoCs is present
14 in file names starting with cnxk.
16 More information about OCTEON cnxk SoCs may be obtained from `<https://www.marvell.com>`_
18 Supported OCTEON cnxk SoCs
19 --------------------------
27 The OCTEON cnxk crypto PMD has support for:
29 Symmetric Crypto Algorithms
30 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
34 * ``RTE_CRYPTO_CIPHER_NULL``
35 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
36 * ``RTE_CRYPTO_CIPHER_3DES_ECB``
37 * ``RTE_CRYPTO_CIPHER_AES_CBC``
38 * ``RTE_CRYPTO_CIPHER_AES_CTR``
39 * ``RTE_CRYPTO_CIPHER_AES_XTS``
40 * ``RTE_CRYPTO_CIPHER_DES_CBC``
41 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
42 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
43 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
47 * ``RTE_CRYPTO_AUTH_NULL``
48 * ``RTE_CRYPTO_AUTH_AES_GMAC``
49 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
50 * ``RTE_CRYPTO_AUTH_MD5``
51 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
52 * ``RTE_CRYPTO_AUTH_SHA1``
53 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
54 * ``RTE_CRYPTO_AUTH_SHA224``
55 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
56 * ``RTE_CRYPTO_AUTH_SHA256``
57 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
58 * ``RTE_CRYPTO_AUTH_SHA384``
59 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
60 * ``RTE_CRYPTO_AUTH_SHA512``
61 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
62 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
63 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
67 * ``RTE_CRYPTO_AEAD_AES_GCM``
68 * ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``
73 The OCTEON cnxk crypto PMD may be compiled natively on an OCTEON cnxk platform
74 or cross-compiled on an x86 platform.
76 Refer to :doc:`../platform/cnxk` for instructions to build your DPDK
81 The OCTEON cnxk crypto PMD uses services from the kernel mode OCTEON cnxk
82 crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
87 ``CN9K Initialization``
89 List the CPT PF devices available on cn9k platform:
91 .. code-block:: console
95 ``a0fd`` is the CPT PF device id. You should see output similar to:
97 .. code-block:: console
99 0002:10:00.0 Class 1080: Device 177d:a0fd
101 Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
103 .. code-block:: console
105 echo 1 > /sys/bus/pci/devices/0002:10:00.0/sriov_numvfs
107 Bind the CPT VF device to the vfio_pci driver:
109 .. code-block:: console
112 ./usertools/dpdk-devbind.py -u 0002:10:00.1
113 ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
117 * For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve
118 higher performance as even VF uses one crypto engine and odd one uses
119 another crypto engine.
121 * Ensure that sufficient huge pages are available for your application::
123 dpdk-hugepages.py --setup 4G --pagesize 512M
125 Refer to :ref:`linux_gsg_hugepages` for more details.
127 ``CN10K Initialization``
129 List the CPT PF devices available on cn10k platform:
131 .. code-block:: console
135 ``a0f2`` is the CPT PF device id. You should see output similar to:
137 .. code-block:: console
139 0002:20:00.0 Class 1080: Device 177d:a0f2
141 Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
143 .. code-block:: console
145 echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs
147 Bind the CPT VF device to the vfio_pci driver:
149 .. code-block:: console
152 ./usertools/dpdk-devbind.py -u 0002:20:00.1
153 ./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1
158 .. _table_octeon_cnxk_crypto_debug_options:
160 .. table:: OCTEON cnxk crypto PMD debug options
162 +---+------------+-------------------------------------------------------+
163 | # | Component | EAL log command |
164 +===+============+=======================================================+
165 | 1 | CPT | --log-level='pmd\.crypto\.cnxk,8' |
166 +---+------------+-------------------------------------------------------+
171 Multiple lcores may not operate on the same crypto queue pair. The lcore that
172 enqueues to a queue pair is the one that must dequeue from it.