1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2018 Cavium, Inc
4 Cavium OCTEON TX Crypto Poll Mode Driver
5 ========================================
7 The OCTEON TX crypto poll mode driver provides support for offloading
8 cryptographic operations to cryptographic accelerator units on
9 **OCTEON TX** :sup:`®` family of processors (CN8XXX). The OCTEON TX crypto
10 poll mode driver enqueues the crypto request to this accelerator and dequeues
11 the response once the operation is completed.
13 Supported Symmetric Crypto Algorithms
14 -------------------------------------
19 * ``RTE_CRYPTO_CIPHER_NULL``
20 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
21 * ``RTE_CRYPTO_CIPHER_3DES_ECB``
22 * ``RTE_CRYPTO_CIPHER_AES_CBC``
23 * ``RTE_CRYPTO_CIPHER_AES_CTR``
24 * ``RTE_CRYPTO_CIPHER_AES_XTS``
25 * ``RTE_CRYPTO_CIPHER_DES_CBC``
26 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
27 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
28 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
33 * ``RTE_CRYPTO_AUTH_NULL``
34 * ``RTE_CRYPTO_AUTH_AES_GMAC``
35 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
36 * ``RTE_CRYPTO_AUTH_MD5``
37 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
38 * ``RTE_CRYPTO_AUTH_SHA1``
39 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
40 * ``RTE_CRYPTO_AUTH_SHA224``
41 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
42 * ``RTE_CRYPTO_AUTH_SHA256``
43 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
44 * ``RTE_CRYPTO_AUTH_SHA384``
45 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
46 * ``RTE_CRYPTO_AUTH_SHA512``
47 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
48 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
49 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
54 * ``RTE_CRYPTO_AEAD_AES_GCM``
56 Supported Asymmetric Crypto Algorithms
57 --------------------------------------
59 * ``RTE_CRYPTO_ASYM_XFORM_RSA``
60 * ``RTE_CRYPTO_ASYM_XFORM_MODEX``
66 The OCTEON TX crypto poll mode driver can be compiled either natively on
67 **OCTEON TX** :sup:`®` board or cross-compiled on an x86 based platform.
69 Refer :doc:`../platform/octeontx` for details about setting up the platform
70 and building DPDK applications.
74 OCTEON TX crypto PF driver needs microcode to be available at `/lib/firmware/` directory.
75 Refer SDK documents for further information.
77 SDK and related information can be obtained from: `Cavium support site <https://support.cavium.com/>`_.
82 The number of crypto VFs to be enabled can be controlled by setting sysfs entry,
83 `sriov_numvfs`, for the corresponding PF driver.
85 .. code-block:: console
87 echo <num_vfs> > /sys/bus/pci/devices/<dev_bus_id>/sriov_numvfs
89 The device bus ID, `dev_bus_id`, to be used in the above step can be found out
90 by using dpdk-devbind.py script. The OCTEON TX crypto PF device need to be
91 identified and the corresponding device number can be used to tune various PF
95 Once the required VFs are enabled, dpdk-devbind.py script can be used to
96 identify the VFs. To be accessible from DPDK, VFs need to be bound to vfio-pci
99 .. code-block:: console
102 ./usertools/dpdk-devbind.py -u <vf device no>
103 ./usertools/dpdk-devbind.py -b vfio-pci <vf device no>
105 Appropriate huge page need to be setup in order to run the DPDK example
108 .. code-block:: console
110 dpdk-hugepages.py --setup 4G --pagesize 512M
112 Example applications can now be executed with crypto operations offloaded to
113 OCTEON TX crypto PMD.
115 .. code-block:: console
117 ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
118 "(1,0,0),(0,0,0)" -f ep1.cfg
123 The symmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
126 .. code-block:: console
129 RTE>>cryptodev_octeontx_autotest
131 The asymmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
134 .. code-block:: console
137 RTE>>cryptodev_octeontx_asym_autotest