1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2019 Marvell International Ltd.
5 Marvell OCTEON TX2 Crypto Poll Mode Driver
6 ==========================================
8 The OCTEON TX2 crypto poll mode driver provides support for offloading
9 cryptographic operations to cryptographic accelerator units on the
10 **OCTEON TX2** :sup:`®` family of processors (CN9XXX).
12 More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_
17 The OCTEON TX2 crypto PMD has support for:
19 Symmetric Crypto Algorithms
20 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
24 * ``RTE_CRYPTO_CIPHER_NULL``
25 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
26 * ``RTE_CRYPTO_CIPHER_3DES_ECB``
27 * ``RTE_CRYPTO_CIPHER_AES_CBC``
28 * ``RTE_CRYPTO_CIPHER_AES_CTR``
29 * ``RTE_CRYPTO_CIPHER_AES_XTS``
30 * ``RTE_CRYPTO_CIPHER_DES_CBC``
31 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
32 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
33 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
37 * ``RTE_CRYPTO_AUTH_NULL``
38 * ``RTE_CRYPTO_AUTH_AES_GMAC``
39 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
40 * ``RTE_CRYPTO_AUTH_MD5``
41 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
42 * ``RTE_CRYPTO_AUTH_SHA1``
43 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
44 * ``RTE_CRYPTO_AUTH_SHA224``
45 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
46 * ``RTE_CRYPTO_AUTH_SHA256``
47 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
48 * ``RTE_CRYPTO_AUTH_SHA384``
49 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
50 * ``RTE_CRYPTO_AUTH_SHA512``
51 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
52 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
53 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
57 * ``RTE_CRYPTO_AEAD_AES_GCM``
63 The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or
64 cross-compiled on an x86 platform.
66 Enable OCTEON TX2 crypto PMD in your config file:
68 * ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y``
70 Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK
75 The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2
76 crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
81 List the CPT PF devices available on your OCTEON TX2 platform:
83 .. code-block:: console
87 ``a0fd`` is the CPT PF device id. You should see output similar to:
89 .. code-block:: console
91 0002:10:00.0 Class 1080: Device 177d:a0fd
93 Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
95 .. code-block:: console
97 echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs
99 Bind the CPT VF device to the vfio_pci driver:
101 .. code-block:: console
103 echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id
104 echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind
105 echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind
107 Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:
109 .. code-block:: console
112 ./usertools/dpdk-devbind.py -u 0002:10:00.1
113 ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
117 Ensure that sufficient huge pages are available for your application::
119 echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
121 Refer to :ref:`linux_gsg_hugepages` for more details.
126 .. _table_octeontx2_crypto_debug_options:
128 .. table:: OCTEON TX2 crypto PMD debug options
130 +---+------------+-------------------------------------------------------+
131 | # | Component | EAL log command |
132 +===+============+=======================================================+
133 | 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' |
134 +---+------------+-------------------------------------------------------+
139 The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test
142 .. code-block:: console
145 RTE>>cryptodev_octeontx2_autotest