1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2015-2019 Intel Corporation.
4 Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver
5 ==================================================
7 QAT documentation consists of three parts:
9 * Details of the symmetric and asymmetric crypto services below.
10 * Details of the :doc:`compression service <../compressdevs/qat_comp>`
11 in the compressdev drivers section.
12 * Details of building the common QAT infrastructure and the PMDs to support the
13 above services. See :ref:`building_qat` below.
16 Symmetric Crypto Service on QAT
17 -------------------------------
19 The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides
20 poll mode crypto driver support for the following hardware accelerator devices:
22 * ``Intel QuickAssist Technology DH895xCC``
23 * ``Intel QuickAssist Technology C62x``
24 * ``Intel QuickAssist Technology C3xxx``
25 * ``Intel QuickAssist Technology D15xx``
26 * ``Intel QuickAssist Technology C4xxx``
32 The QAT SYM PMD has support for:
36 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
37 * ``RTE_CRYPTO_CIPHER_3DES_CTR``
38 * ``RTE_CRYPTO_CIPHER_AES128_CBC``
39 * ``RTE_CRYPTO_CIPHER_AES192_CBC``
40 * ``RTE_CRYPTO_CIPHER_AES256_CBC``
41 * ``RTE_CRYPTO_CIPHER_AES128_CTR``
42 * ``RTE_CRYPTO_CIPHER_AES192_CTR``
43 * ``RTE_CRYPTO_CIPHER_AES256_CTR``
44 * ``RTE_CRYPTO_CIPHER_AES_XTS``
45 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
46 * ``RTE_CRYPTO_CIPHER_NULL``
47 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
48 * ``RTE_CRYPTO_CIPHER_DES_CBC``
49 * ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI``
50 * ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``
51 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
55 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
56 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
57 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
58 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
59 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
60 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
61 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
62 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
63 * ``RTE_CRYPTO_AUTH_NULL``
64 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
65 * ``RTE_CRYPTO_AUTH_AES_GMAC``
66 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
67 * ``RTE_CRYPTO_AUTH_AES_CMAC``
69 Supported AEAD algorithms:
71 * ``RTE_CRYPTO_AEAD_AES_GCM``
72 * ``RTE_CRYPTO_AEAD_AES_CCM``
78 All the usual chains are supported and also some mixed chains:
80 .. table:: Supported hash-cipher chains for wireless digest-encrypted cases
82 +------------------+-----------+-------------+----------+----------+
83 | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
84 +==================+===========+=============+==========+==========+
85 | NULL CIPHER | Y | 3 | 3 | Y |
86 +------------------+-----------+-------------+----------+----------+
87 | SNOW3G UEA2 | 3 | Y | 3 | 3 |
88 +------------------+-----------+-------------+----------+----------+
89 | ZUC EEA3 | 3 | 3 | 2&3 | 3 |
90 +------------------+-----------+-------------+----------+----------+
91 | AES CTR | Y | 3 | 3 | Y |
92 +------------------+-----------+-------------+----------+----------+
94 * The combinations marked as "Y" are supported on all QAT hardware versions.
95 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
96 * The combinations marked as "3" are supported on GEN3 QAT hardware only.
102 * Only supports the session-oriented API implementation (session-less APIs are not supported).
103 * SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple.
104 * SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple.
105 * No BSD support as BSD QAT kernel driver not available.
106 * ZUC EEA3/EIA3 is not supported by dh895xcc devices
107 * Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros.
108 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
109 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
110 from the RX queue must be done from one thread, but enqueues and dequeues may be done
111 in different threads.)
112 * A GCM limitation exists, but only in the case where there are multiple
113 generations of QAT devices on a single platform.
114 To optimise performance, the GCM crypto session should be initialised for the
115 device generation to which the ops will be enqueued. Specifically if a GCM
116 session is initialised on a GEN2 device, but then attached to an op enqueued
117 to a GEN3 device, it will work but cannot take advantage of hardware
118 optimisations in the GEN3 device. And if a GCM session is initialised on a
119 GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be
120 enqueued to the device and will be marked as failed. The simplest way to
121 mitigate this is to use the bdf whitelist to avoid mixing devices of different
122 generations in the same process if planning to use for GCM.
124 Extra notes on KASUMI F9
125 ~~~~~~~~~~~~~~~~~~~~~~~~
127 When using KASUMI F9 authentication algorithm, the input buffer must be
128 constructed according to the
129 `3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_
130 (section 4.4, page 13). The input buffer has to have COUNT (4 bytes),
131 FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION
132 bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that
133 the total length of the buffer is multiple of 8 bits. Note that the actual
134 message can be any length, specified in bits.
136 Once this buffer is passed this way, when creating the crypto operation,
137 length of data to authenticate "op.sym.auth.data.length" must be the length
138 of all the items described above, including the padding at the end.
139 Also, offset of data to authenticate "op.sym.auth.data.offset"
140 must be such that points at the start of the COUNT bytes.
142 Asymmetric Crypto Service on QAT
143 --------------------------------
145 The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides
146 poll mode crypto driver support for the following hardware accelerator devices:
148 * ``Intel QuickAssist Technology DH895xCC``
149 * ``Intel QuickAssist Technology C62x``
150 * ``Intel QuickAssist Technology C3xxx``
151 * ``Intel QuickAssist Technology D15xx``
152 * ``Intel QuickAssist Technology C4xxx``
154 The QAT ASYM PMD has support for:
156 * ``RTE_CRYPTO_ASYM_XFORM_MODEX``
157 * ``RTE_CRYPTO_ASYM_XFORM_MODINV``
162 * Big integers longer than 4096 bits are not supported.
163 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
164 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
165 from the RX queue must be done from one thread, but enqueues and dequeues may be done
166 in different threads.)
167 * RSA-2560, RSA-3584 are not supported
174 A QAT device can host multiple acceleration services:
176 * symmetric cryptography
178 * asymmetric cryptography
180 These services are provided to DPDK applications via PMDs which register to
181 implement the corresponding cryptodev and compressdev APIs. The PMDs use
182 common QAT driver code which manages the QAT PCI device. They also depend on a
183 QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below.
186 Configuring and Building the DPDK QAT PMDs
187 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
190 Further information on configuring, building and installing DPDK is described
191 :doc:`here <../linux_gsg/build_dpdk>`.
194 Quick instructions for QAT cryptodev PMD are as follows:
196 .. code-block:: console
198 cd to the top-level DPDK directory
200 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
202 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config
205 Quick instructions for QAT compressdev PMD are as follows:
207 .. code-block:: console
209 cd to the top-level DPDK directory
214 .. _building_qat_config:
219 These are the build configuration options affecting QAT, and their default values:
221 .. code-block:: console
223 CONFIG_RTE_LIBRTE_PMD_QAT=y
224 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
225 CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
226 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
227 CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
229 CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built.
231 Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not
232 built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them.
234 The QAT compressdev PMD has no external dependencies, so needs no configuration
235 options and is built by default.
237 The number of VFs per PF varies - see table below. If multiple QAT packages are
238 installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be
239 adjusted to the number of VFs which the QAT common code will need to handle.
243 There are separate config items (not QAT-specific) for max cryptodevs
244 CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS,
245 if necessary these should be adjusted to handle the total of QAT and other
246 devices which the process will use. In particular for crypto, where each
247 QAT VF may expose two crypto devices, sym and asym, it may happen that the
248 number of devices will be bigger than MAX_DEVS and the process will show an error
249 during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be
250 increased or -w, pci-whitelist domain:bus:devid:func option may be used.
253 QAT compression PMD needs intermediate buffers to support Deflate compression
254 with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE
255 specifies the size of a single buffer, the PMD will allocate a multiple of these,
256 plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are
257 allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead.
261 If the compressed output of a Deflate operation using Dynamic Huffman
262 Encoding is too big to fit in an intermediate buffer, then the
263 operation will fall back to fixed compression rather than failing the operation.
264 To avoid this less performant case, applications should configure
265 the intermediate buffer size to be larger than the expected input data size
266 (compressed output size is usually unknown, so the only option is to make
267 larger than the input size).
270 Running QAT PMD with minimum threshold for burst size
271 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
273 If only a small number or packets can be enqueued. Each enqueue causes an expensive MMIO write.
274 These MMIO write occurrences can be optimised by setting any of the following parameters:
276 - qat_sym_enq_threshold
277 - qat_asym_enq_threshold
278 - qat_comp_enq_threshold
280 When any of these parameters is set rte_cryptodev_enqueue_burst function will
281 return 0 (thereby avoiding an MMIO) if the device is congested and number of packets
282 possible to enqueue is smaller.
283 To use this feature the user must set the parameter on process start as a device additional parameter::
285 -w 03:01.1,qat_sym_enq_threshold=32,qat_comp_enq_threshold=16
287 All parameters can be used with the same device regardless of order. Parameters are separated
288 by comma. When the same parameter is used more than once first occurrence of the parameter
290 Maximum threshold that can be set is 32.
293 Device and driver naming
294 ~~~~~~~~~~~~~~~~~~~~~~~~
296 * The qat cryptodev symmetric crypto driver name is "crypto_qat".
297 * The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym".
299 The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers.
301 * Each qat sym crypto device has a unique name, in format
302 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym".
303 * Each qat asym crypto device has a unique name, in format
304 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym".
305 This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id.
309 The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter.
311 The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
313 * The qat compressdev driver name is "compress_qat".
314 The rte_compressdev_devices_get() returns the devices exposed by this driver.
316 * Each qat compression device has a unique name, in format
317 <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
318 This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
322 Dependency on the QAT kernel driver
323 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
325 To use QAT an SRIOV-enabled QAT kernel driver is required. The VF
326 devices created and initialised by this driver will be used by the QAT PMDs.
328 Instructions for installation are below, but first an explanation of the
329 relationships between the PF/VF devices and the PMDs visible to
332 Each QuickAssist PF device exposes a number of VF devices. Each VF device can
333 enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or
335 These QAT PMDs share the same underlying device and pci-mgmt code, but are
336 enumerated independently on their respective APIs and appear as independent
337 devices to applications.
341 Each VF can only be used by one DPDK process. It is not possible to share
342 the same VF across multiple processes, even if these processes are using
343 different acceleration services.
345 Conversely one DPDK process can use one or more QAT VFs and can expose both
346 cryptodev and compressdev instances on each of those VFs.
349 Available kernel drivers
350 ~~~~~~~~~~~~~~~~~~~~~~~~
352 Kernel drivers for each device for each service are listed in the following table. (Scroll right
353 to see the full table)
356 .. _table_qat_pmds_drivers:
358 .. table:: QAT device generations, devices and drivers
360 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
361 | S | A | C | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF |
362 +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+
363 | Yes | No | No | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
364 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
365 | Yes | Yes | No | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
366 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
367 | Yes | Yes | Yes | " | " | 01.org/4.3.0+ | " | " | " | " | " | " |
368 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
369 | Yes | No | No | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
370 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
371 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
372 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
373 | Yes | No | No | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
374 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
375 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
376 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
377 | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
378 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
379 | Yes | No | No | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 |
380 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
382 The first 3 columns indicate the service:
384 * S = Symmetric crypto service (via cryptodev API)
385 * A = Asymmetric crypto service (via cryptodev API)
386 * C = Compression service (via compressdev API)
388 The ``Driver`` column indicates either the Linux kernel version in which
389 support for this device was introduced or a driver available on Intel's 01.org
390 website. There are both linux in-tree and 01.org kernel drivers available for some
391 devices. p = release pending.
393 If you are running on a kernel which includes a driver for your device, see
394 `Installation using kernel.org driver`_ below. Otherwise see
395 `Installation using 01.org QAT driver`_.
398 Installation using kernel.org driver
399 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
401 The examples below are based on the C62x device, if you have a different device
402 use the corresponding values in the above table.
404 In BIOS ensure that SRIOV is enabled and either:
407 * Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
409 Check that the QAT driver is loaded on your system, by executing::
413 You should see the kernel module for your device listed, e.g.::
416 intel_qat 82336 1 qat_c62x
418 Next, you need to expose the Virtual Functions (VFs) using the sysfs file system.
420 First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of
425 You should see output similar to::
427 1a:00.0 Co-processor: Intel Corporation Device 37c8
428 3d:00.0 Co-processor: Intel Corporation Device 37c8
429 3f:00.0 Co-processor: Intel Corporation Device 37c8
431 Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver::
433 echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs
434 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs
435 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs
437 Check that the VFs are available for use. For example ``lspci -d:37c9`` should
438 list 48 VF devices available for a ``C62x`` device.
440 To complete the installation follow the instructions in
441 `Binding the available VFs to the DPDK UIO driver`_.
445 If the QAT kernel modules are not loaded and you see an error like ``Failed
446 to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a
447 result of not using a distribution, but just updating the kernel directly.
449 Download firmware from the `kernel firmware repo
450 <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_.
452 Copy qat binaries to ``/lib/firmware``::
454 cp qat_895xcc.bin /lib/firmware
455 cp qat_895xcc_mmp.bin /lib/firmware
457 Change to your linux source root directory and start the qat kernel modules::
459 insmod ./drivers/crypto/qat/qat_common/intel_qat.ko
460 insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko
465 If you see the following warning in ``/var/log/messages`` it can be ignored:
466 ``IOMMU should be enabled for SR-IOV to work correctly``.
469 Installation using 01.org QAT driver
470 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
472 Download the latest QuickAssist Technology Driver from `01.org
473 <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_.
474 Consult the *Getting Started Guide* at the same URL for further information.
476 The steps below assume you are:
478 * Building on a platform with one ``C62x`` device.
479 * Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
480 * On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
482 In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
484 Uninstall any existing QAT driver, for example by running:
486 * ``./installer.sh uninstall`` in the directory where originally installed.
489 Build and install the SRIOV-enabled QAT driver::
494 # Copy the package to this location and unpack
495 tar zxof qat1.7.l.4.2.0-000xx.tar.gz
497 ./configure --enable-icp-sriov=host
500 You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
501 You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
503 Confirm the driver is correctly installed and is using firmware version 4.2.0::
505 cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
508 Confirm the presence of 48 VF devices - 16 per PF::
513 To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
517 If using a later kernel and the build fails with an error relating to
518 ``strict_stroul`` not being available apply the following patch:
522 /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h
523 + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5)
524 + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
526 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
527 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
529 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
530 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));}
532 #define STR_TO_64(str, base, num, endPtr) \
536 *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \
538 *(num) = simple_strtoull((str), &(endPtr), (base)); \
548 If the build fails due to missing header files you may need to do following::
550 sudo yum install zlib-devel
551 sudo yum install openssl-devel
552 sudo yum install libudev-devel
556 If the build or install fails due to mismatching kernel sources you may need to do the following::
558 sudo yum install kernel-headers-`uname -r`
559 sudo yum install kernel-src-`uname -r`
560 sudo yum install kernel-devel-`uname -r`
563 Binding the available VFs to the DPDK UIO driver
564 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
566 Unbind the VFs from the stock driver so they can be bound to the uio driver.
568 For an Intel(R) QuickAssist Technology DH895xCC device
569 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
571 The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your
572 VFs are different adjust the unbind command below::
574 for device in $(seq 1 4); do \
575 for fn in $(seq 0 7); do \
576 echo -n 0000:03:0${device}.${fn} > \
577 /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \
581 For an Intel(R) QuickAssist Technology C62x device
582 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
584 The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``,
585 ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different
586 adjust the unbind command below::
588 for device in $(seq 1 2); do \
589 for fn in $(seq 0 7); do \
590 echo -n 0000:1a:0${device}.${fn} > \
591 /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \
593 echo -n 0000:3d:0${device}.${fn} > \
594 /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \
596 echo -n 0000:3f:0${device}.${fn} > \
597 /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \
601 For Intel(R) QuickAssist Technology C3xxx or D15xx device
602 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
604 The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your
605 VFs are different adjust the unbind command below::
607 for device in $(seq 1 2); do \
608 for fn in $(seq 0 7); do \
609 echo -n 0000:01:0${device}.${fn} > \
610 /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \
614 Bind to the DPDK uio driver
615 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
617 Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci
618 to confirm the VF devices are now in use by igb_uio kernel driver,
619 e.g. for the C62x device::
621 cd to the top-level DPDK directory
623 insmod ./build/kmod/igb_uio.ko
624 echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
628 Another way to bind the VFs to the DPDK UIO driver is by using the
629 ``dpdk-devbind.py`` script::
631 cd to the top-level DPDK directory
632 ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
637 QAT SYM crypto PMD can be tested by running the test application::
642 ./test -l1 -n1 -w <your qat bdf>
643 RTE>>cryptodev_qat_autotest
645 QAT ASYM crypto PMD can be tested by running the test application::
650 ./test -l1 -n1 -w <your qat bdf>
651 RTE>>cryptodev_qat_asym_autotest
653 QAT compression PMD can be tested by running the test application::
656 sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config
659 ./test -l1 -n1 -w <your qat bdf>
660 RTE>>compressdev_autotest
666 There are 2 sets of trace available via the dynamic logging feature:
668 * pmd.qat_dp exposes trace on the data-path.
669 * pmd.qat_general exposes all other trace.
671 pmd.qat exposes both sets of traces.
672 They can be enabled using the log-level option (where 8=maximum log level) on
673 the process cmdline, e.g. using any of the following::
675 --log-level="pmd.qat_general,8"
676 --log-level="pmd.qat_dp,8"
677 --log-level="pmd.qat,8"
681 The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to
682 RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h
683 for meson build and config/common_base for gnu make.
684 Also the dynamic global log level overrides both sets of trace, so e.g. no
685 QAT trace would display in this case::
687 --log-level="7" --log-level="pmd.qat_general,8"