1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2015-2019 Intel Corporation.
4 Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver
5 ==================================================
7 QAT documentation consists of three parts:
9 * Details of the symmetric and asymmetric crypto services below.
10 * Details of the :doc:`compression service <../compressdevs/qat_comp>`
11 in the compressdev drivers section.
12 * Details of building the common QAT infrastructure and the PMDs to support the
13 above services. See :ref:`building_qat` below.
16 Symmetric Crypto Service on QAT
17 -------------------------------
19 The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides
20 poll mode crypto driver support for the following hardware accelerator devices:
22 * ``Intel QuickAssist Technology DH895xCC``
23 * ``Intel QuickAssist Technology C62x``
24 * ``Intel QuickAssist Technology C3xxx``
25 * ``Intel QuickAssist Technology D15xx``
26 * ``Intel QuickAssist Technology C4xxx``
32 The QAT SYM PMD has support for:
36 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
37 * ``RTE_CRYPTO_CIPHER_3DES_CTR``
38 * ``RTE_CRYPTO_CIPHER_AES128_CBC``
39 * ``RTE_CRYPTO_CIPHER_AES192_CBC``
40 * ``RTE_CRYPTO_CIPHER_AES256_CBC``
41 * ``RTE_CRYPTO_CIPHER_AES128_CTR``
42 * ``RTE_CRYPTO_CIPHER_AES192_CTR``
43 * ``RTE_CRYPTO_CIPHER_AES256_CTR``
44 * ``RTE_CRYPTO_CIPHER_AES_XTS``
45 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
46 * ``RTE_CRYPTO_CIPHER_NULL``
47 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
48 * ``RTE_CRYPTO_CIPHER_DES_CBC``
49 * ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI``
50 * ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``
51 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
55 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
56 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
57 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
58 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
59 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
60 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
61 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
62 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
63 * ``RTE_CRYPTO_AUTH_NULL``
64 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
65 * ``RTE_CRYPTO_AUTH_AES_GMAC``
66 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
67 * ``RTE_CRYPTO_AUTH_AES_CMAC``
69 Supported AEAD algorithms:
71 * ``RTE_CRYPTO_AEAD_AES_GCM``
72 * ``RTE_CRYPTO_AEAD_AES_CCM``
78 * Only supports the session-oriented API implementation (session-less APIs are not supported).
79 * SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple.
80 * SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple.
81 * No BSD support as BSD QAT kernel driver not available.
82 * ZUC EEA3/EIA3 is not supported by dh895xcc devices
83 * Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros.
84 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
85 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
86 from the RX queue must be done from one thread, but enqueues and dequeues may be done
87 in different threads.)
88 * A GCM limitation exists, but only in the case where there are multiple
89 generations of QAT devices on a single platform.
90 To optimise performance, the GCM crypto session should be initialised for the
91 device generation to which the ops will be enqueued. Specifically if a GCM
92 session is initialised on a GEN2 device, but then attached to an op enqueued
93 to a GEN3 device, it will work but cannot take advantage of hardware
94 optimisations in the GEN3 device. And if a GCM session is initialised on a
95 GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be
96 enqueued to the device and will be marked as failed. The simplest way to
97 mitigate this is to use the bdf whitelist to avoid mixing devices of different
98 generations in the same process if planning to use for GCM.
100 Extra notes on KASUMI F9
101 ~~~~~~~~~~~~~~~~~~~~~~~~
103 When using KASUMI F9 authentication algorithm, the input buffer must be
104 constructed according to the
105 `3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_
106 (section 4.4, page 13). The input buffer has to have COUNT (4 bytes),
107 FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION
108 bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that
109 the total length of the buffer is multiple of 8 bits. Note that the actual
110 message can be any length, specified in bits.
112 Once this buffer is passed this way, when creating the crypto operation,
113 length of data to authenticate "op.sym.auth.data.length" must be the length
114 of all the items described above, including the padding at the end.
115 Also, offset of data to authenticate "op.sym.auth.data.offset"
116 must be such that points at the start of the COUNT bytes.
118 Asymmetric Crypto Service on QAT
119 --------------------------------
121 The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides
122 poll mode crypto driver support for the following hardware accelerator devices:
124 * ``Intel QuickAssist Technology DH895xCC``
125 * ``Intel QuickAssist Technology C62x``
126 * ``Intel QuickAssist Technology C3xxx``
127 * ``Intel QuickAssist Technology D15xx``
128 * ``Intel QuickAssist Technology C4xxx``
130 The QAT ASYM PMD has support for:
132 * ``RTE_CRYPTO_ASYM_XFORM_MODEX``
133 * ``RTE_CRYPTO_ASYM_XFORM_MODINV``
138 * Big integers longer than 4096 bits are not supported.
139 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
140 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
141 from the RX queue must be done from one thread, but enqueues and dequeues may be done
142 in different threads.)
143 * RSA-2560, RSA-3584 are not supported
150 A QAT device can host multiple acceleration services:
152 * symmetric cryptography
154 * asymmetric cryptography
156 These services are provided to DPDK applications via PMDs which register to
157 implement the corresponding cryptodev and compressdev APIs. The PMDs use
158 common QAT driver code which manages the QAT PCI device. They also depend on a
159 QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below.
162 Configuring and Building the DPDK QAT PMDs
163 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
166 Further information on configuring, building and installing DPDK is described
167 :doc:`here <../linux_gsg/build_dpdk>`.
170 Quick instructions for QAT cryptodev PMD are as follows:
172 .. code-block:: console
174 cd to the top-level DPDK directory
176 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
178 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config
181 Quick instructions for QAT compressdev PMD are as follows:
183 .. code-block:: console
185 cd to the top-level DPDK directory
190 .. _building_qat_config:
195 These are the build configuration options affecting QAT, and their default values:
197 .. code-block:: console
199 CONFIG_RTE_LIBRTE_PMD_QAT=y
200 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
201 CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
202 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
203 CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
205 CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built.
207 Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not
208 built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them.
210 The QAT compressdev PMD has no external dependencies, so needs no configuration
211 options and is built by default.
213 The number of VFs per PF varies - see table below. If multiple QAT packages are
214 installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be
215 adjusted to the number of VFs which the QAT common code will need to handle.
219 There are separate config items (not QAT-specific) for max cryptodevs
220 CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS,
221 if necessary these should be adjusted to handle the total of QAT and other
222 devices which the process will use. In particular for crypto, where each
223 QAT VF may expose two crypto devices, sym and asym, it may happen that the
224 number of devices will be bigger than MAX_DEVS and the process will show an error
225 during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be
226 increased or -w, pci-whitelist domain:bus:devid:func option may be used.
229 QAT compression PMD needs intermediate buffers to support Deflate compression
230 with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE
231 specifies the size of a single buffer, the PMD will allocate a multiple of these,
232 plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are
233 allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead.
237 If the compressed output of a Deflate operation using Dynamic Huffman
238 Encoding is too big to fit in an intermediate buffer, then the
239 operation will fall back to fixed compression rather than failing the operation.
240 To avoid this less performant case, applications should configure
241 the intermediate buffer size to be larger than the expected input data size
242 (compressed output size is usually unknown, so the only option is to make
243 larger than the input size).
246 Device and driver naming
247 ~~~~~~~~~~~~~~~~~~~~~~~~
249 * The qat cryptodev symmetric crypto driver name is "crypto_qat".
250 * The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym".
252 The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers.
254 * Each qat sym crypto device has a unique name, in format
255 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym".
256 * Each qat asym crypto device has a unique name, in format
257 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym".
258 This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id.
262 The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter.
264 The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
266 * The qat compressdev driver name is "compress_qat".
267 The rte_compressdev_devices_get() returns the devices exposed by this driver.
269 * Each qat compression device has a unique name, in format
270 <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
271 This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
275 Dependency on the QAT kernel driver
276 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
278 To use QAT an SRIOV-enabled QAT kernel driver is required. The VF
279 devices created and initialised by this driver will be used by the QAT PMDs.
281 Instructions for installation are below, but first an explanation of the
282 relationships between the PF/VF devices and the PMDs visible to
285 Each QuickAssist PF device exposes a number of VF devices. Each VF device can
286 enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or
288 These QAT PMDs share the same underlying device and pci-mgmt code, but are
289 enumerated independently on their respective APIs and appear as independent
290 devices to applications.
294 Each VF can only be used by one DPDK process. It is not possible to share
295 the same VF across multiple processes, even if these processes are using
296 different acceleration services.
298 Conversely one DPDK process can use one or more QAT VFs and can expose both
299 cryptodev and compressdev instances on each of those VFs.
302 Available kernel drivers
303 ~~~~~~~~~~~~~~~~~~~~~~~~
305 Kernel drivers for each device for each service are listed in the following table. (Scroll right
306 to see the full table)
309 .. _table_qat_pmds_drivers:
311 .. table:: QAT device generations, devices and drivers
313 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
314 | S | A | C | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF |
315 +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+
316 | Yes | No | No | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
317 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
318 | Yes | Yes | No | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
319 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
320 | Yes | Yes | Yes | " | " | 01.org/4.3.0+ | " | " | " | " | " | " |
321 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
322 | Yes | No | No | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
323 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
324 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
325 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
326 | Yes | No | No | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
327 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
328 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " |
329 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
330 | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
331 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
332 | Yes | No | No | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 |
333 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
335 The first 3 columns indicate the service:
337 * S = Symmetric crypto service (via cryptodev API)
338 * A = Asymmetric crypto service (via cryptodev API)
339 * C = Compression service (via compressdev API)
341 The ``Driver`` column indicates either the Linux kernel version in which
342 support for this device was introduced or a driver available on Intel's 01.org
343 website. There are both linux in-tree and 01.org kernel drivers available for some
344 devices. p = release pending.
346 If you are running on a kernel which includes a driver for your device, see
347 `Installation using kernel.org driver`_ below. Otherwise see
348 `Installation using 01.org QAT driver`_.
351 Installation using kernel.org driver
352 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
354 The examples below are based on the C62x device, if you have a different device
355 use the corresponding values in the above table.
357 In BIOS ensure that SRIOV is enabled and either:
360 * Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
362 Check that the QAT driver is loaded on your system, by executing::
366 You should see the kernel module for your device listed, e.g.::
369 intel_qat 82336 1 qat_c62x
371 Next, you need to expose the Virtual Functions (VFs) using the sysfs file system.
373 First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of
378 You should see output similar to::
380 1a:00.0 Co-processor: Intel Corporation Device 37c8
381 3d:00.0 Co-processor: Intel Corporation Device 37c8
382 3f:00.0 Co-processor: Intel Corporation Device 37c8
384 Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver::
386 echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs
387 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs
388 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs
390 Check that the VFs are available for use. For example ``lspci -d:37c9`` should
391 list 48 VF devices available for a ``C62x`` device.
393 To complete the installation follow the instructions in
394 `Binding the available VFs to the DPDK UIO driver`_.
398 If the QAT kernel modules are not loaded and you see an error like ``Failed
399 to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a
400 result of not using a distribution, but just updating the kernel directly.
402 Download firmware from the `kernel firmware repo
403 <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_.
405 Copy qat binaries to ``/lib/firmware``::
407 cp qat_895xcc.bin /lib/firmware
408 cp qat_895xcc_mmp.bin /lib/firmware
410 Change to your linux source root directory and start the qat kernel modules::
412 insmod ./drivers/crypto/qat/qat_common/intel_qat.ko
413 insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko
418 If you see the following warning in ``/var/log/messages`` it can be ignored:
419 ``IOMMU should be enabled for SR-IOV to work correctly``.
422 Installation using 01.org QAT driver
423 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
425 Download the latest QuickAssist Technology Driver from `01.org
426 <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_.
427 Consult the *Getting Started Guide* at the same URL for further information.
429 The steps below assume you are:
431 * Building on a platform with one ``C62x`` device.
432 * Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
433 * On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
435 In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
437 Uninstall any existing QAT driver, for example by running:
439 * ``./installer.sh uninstall`` in the directory where originally installed.
442 Build and install the SRIOV-enabled QAT driver::
447 # Copy the package to this location and unpack
448 tar zxof qat1.7.l.4.2.0-000xx.tar.gz
450 ./configure --enable-icp-sriov=host
453 You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
454 You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
456 Confirm the driver is correctly installed and is using firmware version 4.2.0::
458 cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
461 Confirm the presence of 48 VF devices - 16 per PF::
466 To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
470 If using a later kernel and the build fails with an error relating to
471 ``strict_stroul`` not being available apply the following patch:
475 /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h
476 + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5)
477 + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
479 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
480 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
482 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
483 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));}
485 #define STR_TO_64(str, base, num, endPtr) \
489 *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \
491 *(num) = simple_strtoull((str), &(endPtr), (base)); \
501 If the build fails due to missing header files you may need to do following::
503 sudo yum install zlib-devel
504 sudo yum install openssl-devel
505 sudo yum install libudev-devel
509 If the build or install fails due to mismatching kernel sources you may need to do the following::
511 sudo yum install kernel-headers-`uname -r`
512 sudo yum install kernel-src-`uname -r`
513 sudo yum install kernel-devel-`uname -r`
516 Binding the available VFs to the DPDK UIO driver
517 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
519 Unbind the VFs from the stock driver so they can be bound to the uio driver.
521 For an Intel(R) QuickAssist Technology DH895xCC device
522 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
524 The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your
525 VFs are different adjust the unbind command below::
527 for device in $(seq 1 4); do \
528 for fn in $(seq 0 7); do \
529 echo -n 0000:03:0${device}.${fn} > \
530 /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \
534 For an Intel(R) QuickAssist Technology C62x device
535 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
537 The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``,
538 ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different
539 adjust the unbind command below::
541 for device in $(seq 1 2); do \
542 for fn in $(seq 0 7); do \
543 echo -n 0000:1a:0${device}.${fn} > \
544 /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \
546 echo -n 0000:3d:0${device}.${fn} > \
547 /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \
549 echo -n 0000:3f:0${device}.${fn} > \
550 /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \
554 For Intel(R) QuickAssist Technology C3xxx or D15xx device
555 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
557 The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your
558 VFs are different adjust the unbind command below::
560 for device in $(seq 1 2); do \
561 for fn in $(seq 0 7); do \
562 echo -n 0000:01:0${device}.${fn} > \
563 /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \
567 Bind to the DPDK uio driver
568 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
570 Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci
571 to confirm the VF devices are now in use by igb_uio kernel driver,
572 e.g. for the C62x device::
574 cd to the top-level DPDK directory
576 insmod ./build/kmod/igb_uio.ko
577 echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
581 Another way to bind the VFs to the DPDK UIO driver is by using the
582 ``dpdk-devbind.py`` script::
584 cd to the top-level DPDK directory
585 ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
590 QAT SYM crypto PMD can be tested by running the test application::
595 ./test -l1 -n1 -w <your qat bdf>
596 RTE>>cryptodev_qat_autotest
598 QAT ASYM crypto PMD can be tested by running the test application::
603 ./test -l1 -n1 -w <your qat bdf>
604 RTE>>cryptodev_qat_asym_autotest
606 QAT compression PMD can be tested by running the test application::
609 sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config
612 ./test -l1 -n1 -w <your qat bdf>
613 RTE>>compressdev_autotest
619 There are 2 sets of trace available via the dynamic logging feature:
621 * pmd.qat_dp exposes trace on the data-path.
622 * pmd.qat_general exposes all other trace.
624 pmd.qat exposes both sets of traces.
625 They can be enabled using the log-level option (where 8=maximum log level) on
626 the process cmdline, e.g. using any of the following::
628 --log-level="pmd.qat_general,8"
629 --log-level="pmd.qat_dp,8"
630 --log-level="pmd.qat,8"
634 The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to
635 RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h
636 for meson build and config/common_base for gnu make.
637 Also the dynamic global log level overrides both sets of trace, so e.g. no
638 QAT trace would display in this case::
640 --log-level="7" --log-level="pmd.qat_general,8"