1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2021 Marvell.
4 Marvell cnxk SSO Eventdev Driver
5 ================================
7 The SSO PMD (**librte_event_cnxk**) and provides poll mode
8 eventdev driver support for the inbuilt event device found in the
9 **Marvell OCTEON cnxk** SoC family.
11 More information about OCTEON cnxk SoC can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
14 Supported OCTEON cnxk SoCs
15 --------------------------
23 Features of the OCTEON cnxk SSO PMD are:
26 - 26 (dual) and 52 (single) Event ports on CN9XX
27 - 52 Event ports on CN10XX
29 - Supports 1M flows per event queue
30 - Flow based event pipelining
31 - Flow pinning support in flow based event pipelining
32 - Queue based event pipelining
33 - Supports ATOMIC, ORDERED, PARALLEL schedule types per flow
34 - Event scheduling QoS based on event queue priority
35 - Open system with configurable amount of outstanding events limited only by
37 - HW accelerated dequeue timeout support to enable power management
39 Prerequisites and Compilation procedure
40 ---------------------------------------
42 See :doc:`../platform/cnxk` for setup information.
45 Runtime Config Options
46 ----------------------
48 - ``Maximum number of in-flight events`` (default ``8192``)
50 In **Marvell OCTEON cnxk** the max number of in-flight events are only limited
51 by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide
52 upper limit for in-flight events.
56 -a 0002:0e:00.0,xae_cnt=16384
58 - ``CN9K Getwork mode``
60 CN9K ``single_ws`` devargs parameter is introduced to select single workslot
61 mode in SSO and disable the default dual workslot mode.
65 -a 0002:0e:00.0,single_ws=1
67 - ``CN10K Getwork mode``
69 CN10K supports multiple getwork prefetch modes, by default the prefetch
74 -a 0002:0e:00.0,gw_mode=1
76 - ``Event Group QoS support``
78 SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight
79 events. By default the buffers are assigned to the SSO GGRPs to
80 satisfy minimum HW requirements. SSO is free to assign the remaining
81 buffers to GGRPs based on a preconfigured threshold.
82 We can control the QoS of SSO GGRP by modifying the above mentioned
83 thresholds. GGRPs that have higher importance can be assigned higher
84 thresholds than the rest. The dictionary format is as follows
85 [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents
90 -a 0002:0e:00.0,qos=[1-50-50-50]
95 .. _table_octeon_cnxk_event_debug_options:
97 .. table:: OCTEON cnxk event device debug options
99 +---+------------+-------------------------------------------------------+
100 | # | Component | EAL log command |
101 +===+============+=======================================================+
102 | 1 | SSO | --log-level='pmd\.event\.cnxk,8' |
103 +---+------------+-------------------------------------------------------+