1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2021 Marvell.
7 The CNXK ETHDEV PMD (**librte_net_cnxk**) provides poll mode ethdev driver
8 support for the inbuilt network device found in **Marvell OCTEON CN9K/CN10K**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the CNXK Ethdev PMD are:
21 - Multiple queues for TX and RX
22 - Receiver Side Scaling (RSS)
23 - Link state information
28 See :doc:`../platform/cnxk` for setup information.
31 Driver compilation and testing
32 ------------------------------
34 Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
37 Runtime Config Options
38 ----------------------
40 - ``Rx&Tx scalar mode enable`` (default ``0``)
42 PMD supports both scalar and vector mode, it may be selected at runtime
43 using ``scalar_enable`` ``devargs`` parameter.
45 - ``RSS reta size`` (default ``64``)
47 RSS redirection table size may be configured during runtime using ``reta_size``
48 ``devargs`` parameter.
52 -a 0002:02:00.0,reta_size=256
54 With the above configuration, reta table of size 256 is populated.
56 - ``Flow priority levels`` (default ``3``)
58 RTE Flow priority levels can be configured during runtime using
59 ``flow_max_priority`` ``devargs`` parameter.
63 -a 0002:02:00.0,flow_max_priority=10
65 With the above configuration, priority level was set to 10 (0-9). Max
66 priority level supported is 32.
68 - ``Reserve Flow entries`` (default ``8``)
70 RTE flow entries can be pre allocated and the size of pre allocation can be
71 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
75 -a 0002:02:00.0,flow_prealloc_size=4
77 With the above configuration, pre alloc size was set to 4. Max pre alloc
80 - ``Max SQB buffer count`` (default ``512``)
82 Send queue descriptor buffer count may be limited during runtime using
83 ``max_sqb_count`` ``devargs`` parameter.
87 -a 0002:02:00.0,max_sqb_count=64
89 With the above configuration, each send queue's descriptor buffer count is
90 limited to a maximum of 64 buffers.
92 - ``Switch header enable`` (default ``none``)
94 A port can be configured to a specific switch header type by using
95 ``switch_header`` ``devargs`` parameter.
99 -a 0002:02:00.0,switch_header="higig2"
101 With the above configuration, higig2 will be enabled on that port and the
102 traffic on this port should be higig2 traffic only. Supported switch header
103 types are "higig2", "dsa", "chlen90b" and "chlen24b".
105 - ``RSS tag as XOR`` (default ``0``)
107 The HW gives two options to configure the RSS adder i.e
109 * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``
111 * ``rss_adder<7:0> = flow_tag<7:0>``
113 Latter one aligns with standard NIC behavior vs former one is a legacy
114 RSS adder scheme used in OCTEON TX2 products.
116 By default, the driver runs in the latter mode.
117 Setting this flag to 1 to select the legacy mode.
119 For example to select the legacy mode(RSS tag adder as XOR)::
121 -a 0002:02:00.0,tag_as_xor=1
126 Above devarg parameters are configurable per device, user needs to pass the
127 parameters to all the PCIe devices if application requires to configure on
128 all the ethdev ports.