1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2021 Marvell.
7 The CNXK ETHDEV PMD (**librte_net_cnxk**) provides poll mode ethdev driver
8 support for the inbuilt network device found in **Marvell OCTEON CN9K/CN10K**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the CNXK Ethdev PMD are:
19 - Packet type information
23 - Multiple queues for TX and RX
24 - Receiver Side Scaling (RSS)
25 - Inner and Outer Checksum offload
26 - Link state information
27 - Scatter-Gather IO support
28 - Vector Poll mode driver
33 See :doc:`../platform/cnxk` for setup information.
36 Driver compilation and testing
37 ------------------------------
39 Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
42 Runtime Config Options
43 ----------------------
45 - ``Rx&Tx scalar mode enable`` (default ``0``)
47 PMD supports both scalar and vector mode, it may be selected at runtime
48 using ``scalar_enable`` ``devargs`` parameter.
50 - ``RSS reta size`` (default ``64``)
52 RSS redirection table size may be configured during runtime using ``reta_size``
53 ``devargs`` parameter.
57 -a 0002:02:00.0,reta_size=256
59 With the above configuration, reta table of size 256 is populated.
61 - ``Flow priority levels`` (default ``3``)
63 RTE Flow priority levels can be configured during runtime using
64 ``flow_max_priority`` ``devargs`` parameter.
68 -a 0002:02:00.0,flow_max_priority=10
70 With the above configuration, priority level was set to 10 (0-9). Max
71 priority level supported is 32.
73 - ``Reserve Flow entries`` (default ``8``)
75 RTE flow entries can be pre allocated and the size of pre allocation can be
76 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
80 -a 0002:02:00.0,flow_prealloc_size=4
82 With the above configuration, pre alloc size was set to 4. Max pre alloc
85 - ``Max SQB buffer count`` (default ``512``)
87 Send queue descriptor buffer count may be limited during runtime using
88 ``max_sqb_count`` ``devargs`` parameter.
92 -a 0002:02:00.0,max_sqb_count=64
94 With the above configuration, each send queue's descriptor buffer count is
95 limited to a maximum of 64 buffers.
97 - ``Switch header enable`` (default ``none``)
99 A port can be configured to a specific switch header type by using
100 ``switch_header`` ``devargs`` parameter.
104 -a 0002:02:00.0,switch_header="higig2"
106 With the above configuration, higig2 will be enabled on that port and the
107 traffic on this port should be higig2 traffic only. Supported switch header
108 types are "higig2", "dsa", "chlen90b" and "chlen24b".
110 - ``RSS tag as XOR`` (default ``0``)
112 The HW gives two options to configure the RSS adder i.e
114 * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``
116 * ``rss_adder<7:0> = flow_tag<7:0>``
118 Latter one aligns with standard NIC behavior vs former one is a legacy
119 RSS adder scheme used in OCTEON TX2 products.
121 By default, the driver runs in the latter mode.
122 Setting this flag to 1 to select the legacy mode.
124 For example to select the legacy mode(RSS tag adder as XOR)::
126 -a 0002:02:00.0,tag_as_xor=1
131 Above devarg parameters are configurable per device, user needs to pass the
132 parameters to all the PCIe devices if application requires to configure on
133 all the ethdev ports.