1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2021 Marvell.
7 The CNXK ETHDEV PMD (**librte_net_cnxk**) provides poll mode ethdev driver
8 support for the inbuilt network device found in **Marvell OCTEON CN9K/CN10K**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the CNXK Ethdev PMD are:
19 - Packet type information
23 - Multiple queues for TX and RX
24 - Receiver Side Scaling (RSS)
25 - Link state information
26 - Scatter-Gather IO support
31 See :doc:`../platform/cnxk` for setup information.
34 Driver compilation and testing
35 ------------------------------
37 Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
40 Runtime Config Options
41 ----------------------
43 - ``Rx&Tx scalar mode enable`` (default ``0``)
45 PMD supports both scalar and vector mode, it may be selected at runtime
46 using ``scalar_enable`` ``devargs`` parameter.
48 - ``RSS reta size`` (default ``64``)
50 RSS redirection table size may be configured during runtime using ``reta_size``
51 ``devargs`` parameter.
55 -a 0002:02:00.0,reta_size=256
57 With the above configuration, reta table of size 256 is populated.
59 - ``Flow priority levels`` (default ``3``)
61 RTE Flow priority levels can be configured during runtime using
62 ``flow_max_priority`` ``devargs`` parameter.
66 -a 0002:02:00.0,flow_max_priority=10
68 With the above configuration, priority level was set to 10 (0-9). Max
69 priority level supported is 32.
71 - ``Reserve Flow entries`` (default ``8``)
73 RTE flow entries can be pre allocated and the size of pre allocation can be
74 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
78 -a 0002:02:00.0,flow_prealloc_size=4
80 With the above configuration, pre alloc size was set to 4. Max pre alloc
83 - ``Max SQB buffer count`` (default ``512``)
85 Send queue descriptor buffer count may be limited during runtime using
86 ``max_sqb_count`` ``devargs`` parameter.
90 -a 0002:02:00.0,max_sqb_count=64
92 With the above configuration, each send queue's descriptor buffer count is
93 limited to a maximum of 64 buffers.
95 - ``Switch header enable`` (default ``none``)
97 A port can be configured to a specific switch header type by using
98 ``switch_header`` ``devargs`` parameter.
102 -a 0002:02:00.0,switch_header="higig2"
104 With the above configuration, higig2 will be enabled on that port and the
105 traffic on this port should be higig2 traffic only. Supported switch header
106 types are "higig2", "dsa", "chlen90b" and "chlen24b".
108 - ``RSS tag as XOR`` (default ``0``)
110 The HW gives two options to configure the RSS adder i.e
112 * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``
114 * ``rss_adder<7:0> = flow_tag<7:0>``
116 Latter one aligns with standard NIC behavior vs former one is a legacy
117 RSS adder scheme used in OCTEON TX2 products.
119 By default, the driver runs in the latter mode.
120 Setting this flag to 1 to select the legacy mode.
122 For example to select the legacy mode(RSS tag adder as XOR)::
124 -a 0002:02:00.0,tag_as_xor=1
129 Above devarg parameters are configurable per device, user needs to pass the
130 parameters to all the PCIe devices if application requires to configure on
131 all the ethdev ports.