1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2021 Marvell.
7 The CNXK ETHDEV PMD (**librte_net_cnxk**) provides poll mode ethdev driver
8 support for the inbuilt network device found in **Marvell OCTEON CN9K/CN10K**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the CNXK Ethdev PMD are:
19 - Packet type information
22 - Multiple queues for TX and RX
23 - Receiver Side Scaling (RSS)
24 - Link state information
29 See :doc:`../platform/cnxk` for setup information.
32 Driver compilation and testing
33 ------------------------------
35 Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
38 Runtime Config Options
39 ----------------------
41 - ``Rx&Tx scalar mode enable`` (default ``0``)
43 PMD supports both scalar and vector mode, it may be selected at runtime
44 using ``scalar_enable`` ``devargs`` parameter.
46 - ``RSS reta size`` (default ``64``)
48 RSS redirection table size may be configured during runtime using ``reta_size``
49 ``devargs`` parameter.
53 -a 0002:02:00.0,reta_size=256
55 With the above configuration, reta table of size 256 is populated.
57 - ``Flow priority levels`` (default ``3``)
59 RTE Flow priority levels can be configured during runtime using
60 ``flow_max_priority`` ``devargs`` parameter.
64 -a 0002:02:00.0,flow_max_priority=10
66 With the above configuration, priority level was set to 10 (0-9). Max
67 priority level supported is 32.
69 - ``Reserve Flow entries`` (default ``8``)
71 RTE flow entries can be pre allocated and the size of pre allocation can be
72 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
76 -a 0002:02:00.0,flow_prealloc_size=4
78 With the above configuration, pre alloc size was set to 4. Max pre alloc
81 - ``Max SQB buffer count`` (default ``512``)
83 Send queue descriptor buffer count may be limited during runtime using
84 ``max_sqb_count`` ``devargs`` parameter.
88 -a 0002:02:00.0,max_sqb_count=64
90 With the above configuration, each send queue's descriptor buffer count is
91 limited to a maximum of 64 buffers.
93 - ``Switch header enable`` (default ``none``)
95 A port can be configured to a specific switch header type by using
96 ``switch_header`` ``devargs`` parameter.
100 -a 0002:02:00.0,switch_header="higig2"
102 With the above configuration, higig2 will be enabled on that port and the
103 traffic on this port should be higig2 traffic only. Supported switch header
104 types are "higig2", "dsa", "chlen90b" and "chlen24b".
106 - ``RSS tag as XOR`` (default ``0``)
108 The HW gives two options to configure the RSS adder i.e
110 * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``
112 * ``rss_adder<7:0> = flow_tag<7:0>``
114 Latter one aligns with standard NIC behavior vs former one is a legacy
115 RSS adder scheme used in OCTEON TX2 products.
117 By default, the driver runs in the latter mode.
118 Setting this flag to 1 to select the legacy mode.
120 For example to select the legacy mode(RSS tag adder as XOR)::
122 -a 0002:02:00.0,tag_as_xor=1
127 Above devarg parameters are configurable per device, user needs to pass the
128 parameters to all the PCIe devices if application requires to configure on
129 all the ethdev ports.