1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2021 Marvell.
7 The CNXK ETHDEV PMD (**librte_net_cnxk**) provides poll mode ethdev driver
8 support for the inbuilt network device found in **Marvell OCTEON CN9K/CN10K**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the CNXK Ethdev PMD are:
22 See :doc:`../platform/cnxk` for setup information.
25 Driver compilation and testing
26 ------------------------------
28 Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
31 Runtime Config Options
32 ----------------------
34 - ``Rx&Tx scalar mode enable`` (default ``0``)
36 PMD supports both scalar and vector mode, it may be selected at runtime
37 using ``scalar_enable`` ``devargs`` parameter.
39 - ``RSS reta size`` (default ``64``)
41 RSS redirection table size may be configured during runtime using ``reta_size``
42 ``devargs`` parameter.
46 -a 0002:02:00.0,reta_size=256
48 With the above configuration, reta table of size 256 is populated.
50 - ``Flow priority levels`` (default ``3``)
52 RTE Flow priority levels can be configured during runtime using
53 ``flow_max_priority`` ``devargs`` parameter.
57 -a 0002:02:00.0,flow_max_priority=10
59 With the above configuration, priority level was set to 10 (0-9). Max
60 priority level supported is 32.
62 - ``Reserve Flow entries`` (default ``8``)
64 RTE flow entries can be pre allocated and the size of pre allocation can be
65 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
69 -a 0002:02:00.0,flow_prealloc_size=4
71 With the above configuration, pre alloc size was set to 4. Max pre alloc
74 - ``Max SQB buffer count`` (default ``512``)
76 Send queue descriptor buffer count may be limited during runtime using
77 ``max_sqb_count`` ``devargs`` parameter.
81 -a 0002:02:00.0,max_sqb_count=64
83 With the above configuration, each send queue's descriptor buffer count is
84 limited to a maximum of 64 buffers.
86 - ``Switch header enable`` (default ``none``)
88 A port can be configured to a specific switch header type by using
89 ``switch_header`` ``devargs`` parameter.
93 -a 0002:02:00.0,switch_header="higig2"
95 With the above configuration, higig2 will be enabled on that port and the
96 traffic on this port should be higig2 traffic only. Supported switch header
97 types are "higig2", "dsa", "chlen90b" and "chlen24b".
99 - ``RSS tag as XOR`` (default ``0``)
101 The HW gives two options to configure the RSS adder i.e
103 * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``
105 * ``rss_adder<7:0> = flow_tag<7:0>``
107 Latter one aligns with standard NIC behavior vs former one is a legacy
108 RSS adder scheme used in OCTEON TX2 products.
110 By default, the driver runs in the latter mode.
111 Setting this flag to 1 to select the legacy mode.
113 For example to select the legacy mode(RSS tag adder as XOR)::
115 -a 0002:02:00.0,tag_as_xor=1
120 Above devarg parameters are configurable per device, user needs to pass the
121 parameters to all the PCIe devices if application requires to configure on
122 all the ethdev ports.