2 Copyright(c) 2017 Marvell International Ltd.
3 Copyright(c) 2017 Semihalf.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions
10 * Redistributions of source code must retain the above copyright
11 notice, this list of conditions and the following disclaimer.
12 * Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in
14 the documentation and/or other materials provided with the
16 * Neither the name of the copyright holder nor the names of its
17 contributors may be used to endorse or promote products derived
18 from this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 .. _mrvl_poll_mode_driver:
35 ======================
37 The MRVL PMD (librte_pmd_mrvl) provides poll mode driver support
38 for the Marvell PPv2 (Packet Processor v2) 1/10 Gbps adapter.
40 Detailed information about SoCs that use PPv2 can be obtained here:
42 * https://www.marvell.com/embedded-processors/armada-70xx/
43 * https://www.marvell.com/embedded-processors/armada-80xx/
47 Due to external dependencies, this driver is disabled by default. It must
48 be enabled manually by setting relevant configuration option manually.
49 Please refer to `Config File Options`_ section for further details.
55 Features of the MRVL PMD are:
65 - Multicast MAC filter
81 - Number of lcores is limited to 9 by MUSDK internal design. If more lcores
82 need to be allocated, locking will have to be considered. Number of available
83 lcores can be changed via ``MRVL_MUSDK_HIFS_RESERVED`` define in
84 ``mrvl_ethdev.c`` source file.
86 - Flushing vlans added for filtering is not possible due to MUSDK missing
87 functionality. Current workaround is to reset board so that PPv2 has a
88 chance to start in a sane state.
94 - Custom Linux Kernel sources
96 .. code-block:: console
98 git clone https://github.com/MarvellEmbeddedProcessors/linux-marvell.git -b linux-4.4.52-armada-17.10
100 - Out of tree `mvpp2x_sysfs` kernel module sources
102 .. code-block:: console
104 git clone https://github.com/MarvellEmbeddedProcessors/mvpp2x-marvell.git -b mvpp2x-armada-17.10
106 - MUSDK (Marvell User-Space SDK) sources
108 .. code-block:: console
110 git clone https://github.com/MarvellEmbeddedProcessors/musdk-marvell.git -b musdk-armada-17.10
112 MUSDK is a light-weight library that provides direct access to Marvell's
113 PPv2 (Packet Processor v2). Alternatively prebuilt MUSDK library can be
114 requested from `Marvell Extranet <https://extranet.marvell.com>`_. Once
115 approval has been granted, library can be found by typing ``musdk`` in
118 To get better understanding of the library one can consult documentation
119 available in the ``doc`` top level directory of the MUSDK sources.
121 MUSDK must be configured with the following features:
123 .. code-block:: console
125 --enable-bpool-dma=64
129 Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup
136 The following options can be modified in the ``config`` file.
138 - ``CONFIG_RTE_LIBRTE_MRVL_PMD`` (default ``n``)
140 Toggle compilation of the librte_pmd_mrvl driver.
146 QoS configuration is done through external configuration file. Path to the
147 file must be given as `cfg` in driver's vdev parameter list.
152 .. code-block:: console
154 [port <portnum> default]
155 default_tc = <default_tc>
156 mapping_priority = <mapping_priority>
157 policer_enable = <policer_enable>
158 token_unit = <token_unit>
164 rate_limit_enable = <rate_limit_enable>
165 rate_limit = <rate_limit>
166 burst_size = <burst_size>
168 [port <portnum> tc <traffic_class>]
169 rxq = <rx_queue_list>
172 default_color = <default_color>
174 [port <portnum> tc <traffic_class>]
175 rxq = <rx_queue_list>
179 [port <portnum> txq <txqnum>]
180 sched_mode = <sched_mode>
181 wrr_weight = <wrr_weight>
183 rate_limit_enable = <rate_limit_enable>
184 rate_limit = <rate_limit>
185 burst_size = <burst_size>
189 - ``<portnum>``: DPDK Port number (0..n).
191 - ``<default_tc>``: Default traffic class (e.g. 0)
193 - ``<mapping_priority>``: QoS priority for mapping (`ip`, `vlan`, `ip/vlan` or `vlan/ip`).
195 - ``<traffic_class>``: Traffic Class to be configured.
197 - ``<rx_queue_list>``: List of DPDK RX queues (e.g. 0 1 3-4)
199 - ``<pcp_list>``: List of PCP values to handle in particular TC (e.g. 0 1 3-4 7).
201 - ``<dscp_list>``: List of DSCP values to handle in particular TC (e.g. 0-12 32-48 63).
203 - ``<policer_enable>``: Enable ingress policer.
205 - ``<token_unit>``: Policer token unit (`bytes` or `packets`).
207 - ``<color_mode>``: Policer color mode (`aware` or `blind`).
209 - ``<cir>``: Committed information rate in unit of kilo bits per second (data rate) or packets per second.
211 - ``<cbs>``: Committed burst size in unit of kilo bytes or number of packets.
213 - ``<ebs>``: Excess burst size in unit of kilo bytes or number of packets.
215 - ``<default_color>``: Default color for specific tc.
217 - ``<rate_limit_enable>``: Enables per port or per txq rate limiting.
219 - ``<rate_limit>``: Committed information rate, in kilo bits per second.
221 - ``<burst_size>``: Committed burst size, in kilo bytes.
223 - ``<sched_mode>``: Egress scheduler mode (`wrr` or `sp`).
225 - ``<wrr_weight>``: Txq weight.
227 Setting PCP/DSCP values for the default TC is not required. All PCP/DSCP
228 values not assigned explicitly to particular TC will be handled by the
231 Configuration file example
232 ^^^^^^^^^^^^^^^^^^^^^^^^^^
234 .. code-block:: console
238 mapping_priority = ip
240 rate_limit_enable = 1
265 mapping_priority = vlan/ip
287 rate_limit_enable = 1
294 .. code-block:: console
296 ./testpmd --vdev=eth_mrvl,iface=eth0,iface=eth2,cfg=/home/user/mrvl.conf \
297 -c 7 -- -i -a --disable-hw-vlan-strip --rxq=3 --txq=3
303 Driver needs precompiled MUSDK library during compilation.
305 .. code-block:: console
307 export CROSS_COMPILE=<toolchain>/bin/aarch64-linux-gnu-
309 ./configure --host=aarch64-linux-gnu --enable-bpool-dma=64
312 MUSDK will be installed to `usr/local` under current directory.
313 For the detailed build instructions please consult ``doc/musdk_get_started.txt``.
315 Before the DPDK build process the environmental variable ``LIBMUSDK_PATH`` with
316 the path to the MUSDK installation directory needs to be exported.
318 .. code-block:: console
320 export LIBMUSDK_PATH=<musdk>/usr/local
321 export CROSS=aarch64-linux-gnu-
322 make config T=arm64-armv8a-linuxapp-gcc
323 sed -ri 's,(MRVL_PMD=)n,\1y,' build/.config
329 PPv2 offers packet classification capabilities via classifier engine which
330 can be configured via generic flow API offered by DPDK.
332 Supported flow actions
333 ~~~~~~~~~~~~~~~~~~~~~~
335 Following flow action items are supported by the driver:
343 Following flow items and their respective fields are supported by the driver:
361 * destination address
368 * destination address
380 Classifier match engine
381 ~~~~~~~~~~~~~~~~~~~~~~~
383 Classifier has an internal match engine which can be configured to
384 operate in either exact or maskable mode.
386 Mode is selected upon creation of the first unique flow rule as follows:
388 * maskable, if key size is up to 8 bytes.
389 * exact, otherwise, i.e for keys bigger than 8 bytes.
391 Where the key size equals the number of bytes of all fields specified
394 .. table:: Examples of key size calculation
396 +----------------------------------------------------------------------------+-------------------+-------------+
397 | Flow pattern | Key size in bytes | Used engine |
398 +============================================================================+===================+=============+
399 | ETH (destination MAC) / VLAN (VID) | 6 + 2 = 8 | Maskable |
400 +----------------------------------------------------------------------------+-------------------+-------------+
401 | VLAN (VID) / IPV4 (source address) | 2 + 4 = 6 | Maskable |
402 +----------------------------------------------------------------------------+-------------------+-------------+
403 | TCP (source port, destination port) | 2 + 2 = 4 | Maskable |
404 +----------------------------------------------------------------------------+-------------------+-------------+
405 | VLAN (priority) / IPV4 (source address) | 1 + 4 = 5 | Maskable |
406 +----------------------------------------------------------------------------+-------------------+-------------+
407 | IPV4 (destination address) / UDP (source port, destination port) | 6 + 2 + 2 = 10 | Exact |
408 +----------------------------------------------------------------------------+-------------------+-------------+
409 | VLAN (VID) / IPV6 (flow label, destination address) | 2 + 3 + 16 = 21 | Exact |
410 +----------------------------------------------------------------------------+-------------------+-------------+
411 | IPV4 (DSCP, source address, destination address) | 1 + 4 + 4 = 9 | Exact |
412 +----------------------------------------------------------------------------+-------------------+-------------+
413 | IPV6 (flow label, source address, destination address) | 3 + 16 + 16 = 35 | Exact |
414 +----------------------------------------------------------------------------+-------------------+-------------+
416 From the user perspective maskable mode means that masks specified
417 via flow rules are respected. In case of exact match mode, masks
418 which do not provide exact matching (all bits masked) are ignored.
420 If the flow matches more than one classifier rule the first
421 (with the lowest index) matched takes precedence.
423 Flow rules usage example
424 ~~~~~~~~~~~~~~~~~~~~~~~~
426 Before proceeding run testpmd user application:
428 .. code-block:: console
430 ./testpmd --vdev=net_mrvl,iface=eth0,iface=eth2 -c 3 -- -i --p 3 -a --disable-hw-vlan-strip
435 .. code-block:: console
437 testpmd> flow create 0 ingress pattern eth src is 10:11:12:13:14:15 / end actions drop / end
439 In this case key size is 6 bytes thus maskable type is selected. Testpmd
440 will set mask to ff:ff:ff:ff:ff:ff i.e traffic explicitly matching
441 above rule will be dropped.
446 .. code-block:: console
448 testpmd> flow create 0 ingress pattern ipv4 src spec 10.10.10.0 src mask 255.255.255.0 / tcp src spec 0x10 src mask 0x10 / end action drop / end
450 In this case key size is 8 bytes thus maskable type is selected.
451 Flows which have IPv4 source addresses ranging from 10.10.10.0 to 10.10.10.255
452 and tcp source port set to 16 will be dropped.
457 .. code-block:: console
459 testpmd> flow create 0 ingress pattern vlan vid spec 0x10 vid mask 0x10 / ipv4 src spec 10.10.1.1 src mask 255.255.0.0 dst spec 11.11.11.1 dst mask 255.255.255.0 / end actions drop / end
461 In this case key size is 10 bytes thus exact type is selected.
462 Even though each item has partial mask set, masks will be ignored.
463 As a result only flows with VID set to 16 and IPv4 source and destination
464 addresses set to 10.10.1.1 and 11.11.11.1 respectively will be dropped.
469 Following limitations need to be taken into account while creating flow rules:
471 * For IPv4 exact match type the key size must be up to 12 bytes.
472 * For IPv6 exact match type the key size must be up to 36 bytes.
473 * Following fields cannot be partially masked (all masks are treated as
480 * TCP/UDP: source port, destination port
482 * Only one classifier table can be created thus all rules in the table
483 have to match table format. Table format is set during creation of
484 the first unique flow rule.
485 * Up to 5 fields can be specified per flow rule.
486 * Up to 20 flow rules can be added.
488 For additional information about classifier please consult
489 ``doc/musdk_cls_user_guide.txt``.
494 MRVL PMD requires extra out of tree kernel modules to function properly.
495 `musdk_uio` and `mv_pp_uio` sources are part of the MUSDK. Please consult
496 ``doc/musdk_get_started.txt`` for the detailed build instructions.
497 For `mvpp2x_sysfs` please consult ``Documentation/pp22_sysfs.txt`` for the
498 detailed build instructions.
500 .. code-block:: console
504 insmod mvpp2x_sysfs.ko
506 Additionally interfaces used by DPDK application need to be put up:
508 .. code-block:: console
513 In order to run testpmd example application following command can be used:
515 .. code-block:: console
517 ./testpmd --vdev=eth_mrvl,iface=eth0,iface=eth2 -c 7 -- \
518 --burst=128 --txd=2048 --rxd=1024 --rxq=2 --txq=2 --nb-cores=2 \