1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2019 Marvell International Ltd.
4 OCTEON TX2 Poll Mode driver
5 ===========================
7 The OCTEON TX2 ETHDEV PMD (**librte_pmd_octeontx2**) provides poll mode ethdev
8 driver support for the inbuilt network device found in **Marvell OCTEON TX2**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the OCTEON TX2 Ethdev PMD are:
19 - Packet type information
24 - Multiple queues for TX and RX
25 - Receiver Side Scaling (RSS)
28 - VLAN/QinQ stripping and insertion
29 - Port hardware statistics
30 - Link state information
32 - Scatter-Gather IO support
33 - Debug utilities - Context dump and error interrupt support
34 - IEEE1588 timestamping
39 See :doc:`../platform/octeontx2` for setup information.
41 Compile time Config Options
42 ---------------------------
44 The following options may be modified in the ``config`` file.
46 - ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)
48 Toggle compilation of the ``librte_pmd_octeontx2`` driver.
50 Runtime Config Options
51 ----------------------
53 - ``HW offload ptype parsing disable`` (default ``0``)
55 Packet type parsing is HW offloaded by default and this feature may be toggled
56 using ``ptype_disable`` ``devargs`` parameter.
58 - ``Rx&Tx scalar mode enable`` (default ``0``)
60 Ethdev supports both scalar and vector mode, it may be selected at runtime
61 using ``scalar_enable`` ``devargs`` parameter.
63 - ``RSS reta size`` (default ``64``)
65 RSS redirection table size may be configured during runtime using ``reta_size``
66 ``devargs`` parameter.
70 -w 0002:02:00.0,reta_size=256
72 With the above configuration, reta table of size 256 is populated.
74 - ``Flow priority levels`` (default ``3``)
76 RTE Flow priority levels can be configured during runtime using
77 ``flow_max_priority`` ``devargs`` parameter.
81 -w 0002:02:00.0,flow_max_priority=10
83 With the above configuration, priority level was set to 10 (0-9). Max
84 priority level supported is 32.
86 - ``Reserve Flow entries`` (default ``8``)
88 RTE flow entries can be pre allocated and the size of pre allocation can be
89 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
93 -w 0002:02:00.0,flow_prealloc_size=4
95 With the above configuration, pre alloc size was set to 4. Max pre alloc
98 - ``Max SQB buffer count`` (default ``512``)
100 Send queue descriptor buffer count may be limited during runtime using
101 ``max_sqb_count`` ``devargs`` parameter.
105 -w 0002:02:00.0,max_sqb_count=64
107 With the above configuration, each send queue's decscriptor buffer count is
108 limited to a maximum of 64 buffers.
113 Above devarg parameters are configurable per device, user needs to pass the
114 parameters to all the PCIe devices if application requires to configure on
115 all the ethdev ports.
120 The OCTEON TX2 SoC family NIC has support for the following patterns and
125 .. _table_octeontx2_supported_flow_item_types:
127 .. table:: Item types
129 +----+--------------------------------+
131 +====+================================+
132 | 1 | RTE_FLOW_ITEM_TYPE_ETH |
133 +----+--------------------------------+
134 | 2 | RTE_FLOW_ITEM_TYPE_VLAN |
135 +----+--------------------------------+
136 | 3 | RTE_FLOW_ITEM_TYPE_E_TAG |
137 +----+--------------------------------+
138 | 4 | RTE_FLOW_ITEM_TYPE_IPV4 |
139 +----+--------------------------------+
140 | 5 | RTE_FLOW_ITEM_TYPE_IPV6 |
141 +----+--------------------------------+
142 | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|
143 +----+--------------------------------+
144 | 7 | RTE_FLOW_ITEM_TYPE_MPLS |
145 +----+--------------------------------+
146 | 8 | RTE_FLOW_ITEM_TYPE_ICMP |
147 +----+--------------------------------+
148 | 9 | RTE_FLOW_ITEM_TYPE_UDP |
149 +----+--------------------------------+
150 | 10 | RTE_FLOW_ITEM_TYPE_TCP |
151 +----+--------------------------------+
152 | 11 | RTE_FLOW_ITEM_TYPE_SCTP |
153 +----+--------------------------------+
154 | 12 | RTE_FLOW_ITEM_TYPE_ESP |
155 +----+--------------------------------+
156 | 13 | RTE_FLOW_ITEM_TYPE_GRE |
157 +----+--------------------------------+
158 | 14 | RTE_FLOW_ITEM_TYPE_NVGRE |
159 +----+--------------------------------+
160 | 15 | RTE_FLOW_ITEM_TYPE_VXLAN |
161 +----+--------------------------------+
162 | 16 | RTE_FLOW_ITEM_TYPE_GTPC |
163 +----+--------------------------------+
164 | 17 | RTE_FLOW_ITEM_TYPE_GTPU |
165 +----+--------------------------------+
166 | 18 | RTE_FLOW_ITEM_TYPE_GENEVE |
167 +----+--------------------------------+
168 | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE |
169 +----+--------------------------------+
170 | 20 | RTE_FLOW_ITEM_TYPE_VOID |
171 +----+--------------------------------+
172 | 21 | RTE_FLOW_ITEM_TYPE_ANY |
173 +----+--------------------------------+
177 .. _table_octeontx2_supported_ingress_action_types:
179 .. table:: Ingress action types
181 +----+--------------------------------+
183 +====+================================+
184 | 1 | RTE_FLOW_ACTION_TYPE_VOID |
185 +----+--------------------------------+
186 | 2 | RTE_FLOW_ACTION_TYPE_MARK |
187 +----+--------------------------------+
188 | 3 | RTE_FLOW_ACTION_TYPE_FLAG |
189 +----+--------------------------------+
190 | 4 | RTE_FLOW_ACTION_TYPE_COUNT |
191 +----+--------------------------------+
192 | 5 | RTE_FLOW_ACTION_TYPE_DROP |
193 +----+--------------------------------+
194 | 6 | RTE_FLOW_ACTION_TYPE_QUEUE |
195 +----+--------------------------------+
196 | 7 | RTE_FLOW_ACTION_TYPE_RSS |
197 +----+--------------------------------+
198 | 8 | RTE_FLOW_ACTION_TYPE_SECURITY |
199 +----+--------------------------------+
201 .. _table_octeontx2_supported_egress_action_types:
203 .. table:: Egress action types
205 +----+--------------------------------+
207 +====+================================+
208 | 1 | RTE_FLOW_ACTION_TYPE_COUNT |
209 +----+--------------------------------+
210 | 2 | RTE_FLOW_ACTION_TYPE_DROP |
211 +----+--------------------------------+