1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2019 Marvell International Ltd.
4 OCTEON TX2 Poll Mode driver
5 ===========================
7 The OCTEON TX2 ETHDEV PMD (**librte_pmd_octeontx2**) provides poll mode ethdev
8 driver support for the inbuilt network device found in **Marvell OCTEON TX2**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the OCTEON TX2 Ethdev PMD are:
19 - Packet type information
23 - Multiple queues for TX and RX
24 - Receiver Side Scaling (RSS)
27 - VLAN/QinQ stripping and insertion
28 - Port hardware statistics
29 - Link state information
31 - Debug utilities - Context dump and error interrupt support
32 - IEEE1588 timestamping
37 See :doc:`../platform/octeontx2` for setup information.
39 Compile time Config Options
40 ---------------------------
42 The following options may be modified in the ``config`` file.
44 - ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)
46 Toggle compilation of the ``librte_pmd_octeontx2`` driver.
48 Runtime Config Options
49 ----------------------
51 - ``HW offload ptype parsing disable`` (default ``0``)
53 Packet type parsing is HW offloaded by default and this feature may be toggled
54 using ``ptype_disable`` ``devargs`` parameter.
56 - ``Rx&Tx scalar mode enable`` (default ``0``)
58 Ethdev supports both scalar and vector mode, it may be selected at runtime
59 using ``scalar_enable`` ``devargs`` parameter.
61 - ``RSS reta size`` (default ``64``)
63 RSS redirection table size may be configured during runtime using ``reta_size``
64 ``devargs`` parameter.
68 -w 0002:02:00.0,reta_size=256
70 With the above configuration, reta table of size 256 is populated.
72 - ``Flow priority levels`` (default ``3``)
74 RTE Flow priority levels can be configured during runtime using
75 ``flow_max_priority`` ``devargs`` parameter.
79 -w 0002:02:00.0,flow_max_priority=10
81 With the above configuration, priority level was set to 10 (0-9). Max
82 priority level supported is 32.
84 - ``Reserve Flow entries`` (default ``8``)
86 RTE flow entries can be pre allocated and the size of pre allocation can be
87 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
91 -w 0002:02:00.0,flow_prealloc_size=4
93 With the above configuration, pre alloc size was set to 4. Max pre alloc
96 - ``Max SQB buffer count`` (default ``512``)
98 Send queue descriptor buffer count may be limited during runtime using
99 ``max_sqb_count`` ``devargs`` parameter.
103 -w 0002:02:00.0,max_sqb_count=64
105 With the above configuration, each send queue's decscriptor buffer count is
106 limited to a maximum of 64 buffers.
111 Above devarg parameters are configurable per device, user needs to pass the
112 parameters to all the PCIe devices if application requires to configure on
113 all the ethdev ports.
118 The OCTEON TX2 SoC family NIC has support for the following patterns and
123 .. _table_octeontx2_supported_flow_item_types:
125 .. table:: Item types
127 +----+--------------------------------+
129 +====+================================+
130 | 1 | RTE_FLOW_ITEM_TYPE_ETH |
131 +----+--------------------------------+
132 | 2 | RTE_FLOW_ITEM_TYPE_VLAN |
133 +----+--------------------------------+
134 | 3 | RTE_FLOW_ITEM_TYPE_E_TAG |
135 +----+--------------------------------+
136 | 4 | RTE_FLOW_ITEM_TYPE_IPV4 |
137 +----+--------------------------------+
138 | 5 | RTE_FLOW_ITEM_TYPE_IPV6 |
139 +----+--------------------------------+
140 | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|
141 +----+--------------------------------+
142 | 7 | RTE_FLOW_ITEM_TYPE_MPLS |
143 +----+--------------------------------+
144 | 8 | RTE_FLOW_ITEM_TYPE_ICMP |
145 +----+--------------------------------+
146 | 9 | RTE_FLOW_ITEM_TYPE_UDP |
147 +----+--------------------------------+
148 | 10 | RTE_FLOW_ITEM_TYPE_TCP |
149 +----+--------------------------------+
150 | 11 | RTE_FLOW_ITEM_TYPE_SCTP |
151 +----+--------------------------------+
152 | 12 | RTE_FLOW_ITEM_TYPE_ESP |
153 +----+--------------------------------+
154 | 13 | RTE_FLOW_ITEM_TYPE_GRE |
155 +----+--------------------------------+
156 | 14 | RTE_FLOW_ITEM_TYPE_NVGRE |
157 +----+--------------------------------+
158 | 15 | RTE_FLOW_ITEM_TYPE_VXLAN |
159 +----+--------------------------------+
160 | 16 | RTE_FLOW_ITEM_TYPE_GTPC |
161 +----+--------------------------------+
162 | 17 | RTE_FLOW_ITEM_TYPE_GTPU |
163 +----+--------------------------------+
164 | 18 | RTE_FLOW_ITEM_TYPE_GENEVE |
165 +----+--------------------------------+
166 | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE |
167 +----+--------------------------------+
168 | 20 | RTE_FLOW_ITEM_TYPE_VOID |
169 +----+--------------------------------+
170 | 21 | RTE_FLOW_ITEM_TYPE_ANY |
171 +----+--------------------------------+
175 .. _table_octeontx2_supported_ingress_action_types:
177 .. table:: Ingress action types
179 +----+--------------------------------+
181 +====+================================+
182 | 1 | RTE_FLOW_ACTION_TYPE_VOID |
183 +----+--------------------------------+
184 | 2 | RTE_FLOW_ACTION_TYPE_MARK |
185 +----+--------------------------------+
186 | 3 | RTE_FLOW_ACTION_TYPE_FLAG |
187 +----+--------------------------------+
188 | 4 | RTE_FLOW_ACTION_TYPE_COUNT |
189 +----+--------------------------------+
190 | 5 | RTE_FLOW_ACTION_TYPE_DROP |
191 +----+--------------------------------+
192 | 6 | RTE_FLOW_ACTION_TYPE_QUEUE |
193 +----+--------------------------------+
194 | 7 | RTE_FLOW_ACTION_TYPE_RSS |
195 +----+--------------------------------+
196 | 8 | RTE_FLOW_ACTION_TYPE_SECURITY |
197 +----+--------------------------------+
199 .. _table_octeontx2_supported_egress_action_types:
201 .. table:: Egress action types
203 +----+--------------------------------+
205 +====+================================+
206 | 1 | RTE_FLOW_ACTION_TYPE_COUNT |
207 +----+--------------------------------+
208 | 2 | RTE_FLOW_ACTION_TYPE_DROP |
209 +----+--------------------------------+