1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2019 Marvell International Ltd.
4 OCTEON TX2 Poll Mode driver
5 ===========================
7 The OCTEON TX2 ETHDEV PMD (**librte_pmd_octeontx2**) provides poll mode ethdev
8 driver support for the inbuilt network device found in **Marvell OCTEON TX2**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the OCTEON TX2 Ethdev PMD are:
19 - Packet type information
24 - Multiple queues for TX and RX
25 - Receiver Side Scaling (RSS)
28 - Inner and Outer Checksum offload
29 - VLAN/QinQ stripping and insertion
30 - Port hardware statistics
31 - Link state information
34 - Scatter-Gather IO support
35 - Vector Poll mode driver
36 - Debug utilities - Context dump and error interrupt support
37 - IEEE1588 timestamping
38 - HW offloaded `ethdev Rx queue` to `eventdev event queue` packet injection
43 See :doc:`../platform/octeontx2` for setup information.
45 Compile time Config Options
46 ---------------------------
48 The following options may be modified in the ``config`` file.
50 - ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)
52 Toggle compilation of the ``librte_pmd_octeontx2`` driver.
54 Driver compilation and testing
55 ------------------------------
57 Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
60 To compile the OCTEON TX2 PMD for Linux arm64 gcc,
61 use arm64-octeontx2-linux-gcc as target.
65 Follow instructions available in the document
66 :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
71 .. code-block:: console
73 ./build/app/testpmd -c 0x300 -w 0002:02:00.0 -- --portmask=0x1 --nb-cores=1 --port-topology=loop --rxq=1 --txq=1
74 EAL: Detected 24 lcore(s)
75 EAL: Detected 1 NUMA nodes
76 EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
77 EAL: No available hugepages reported in hugepages-2048kB
78 EAL: Probing VFIO support...
79 EAL: VFIO support initialized
80 EAL: PCI device 0002:02:00.0 on NUMA socket 0
81 EAL: probe driver: 177d:a063 net_octeontx2
82 EAL: using IOMMU type 1 (Type 1)
83 testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=267456, size=2176, socket=0
84 testpmd: preferred mempool ops selected: octeontx2_npa
85 Configuring Port 0 (socket 0)
86 PMD: Port 0: Link Up - speed 40000 Mbps - full-duplex
88 Port 0: link state change event
89 Port 0: 36:10:66:88:7A:57
90 Checking link statuses...
92 No commandline core given, start packet forwarding
93 io packet forwarding - ports=1 - cores=1 - streams=1 - NUMA support enabled, MP allocation mode: native
94 Logical Core 9 (socket 0) forwards packets on 1 streams:
95 RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
97 io packet forwarding packets/burst=32
98 nb forwarding cores=1 - nb forwarding ports=1
99 port 0: RX queue number: 1 Tx queue number: 1
100 Rx offloads=0x0 Tx offloads=0x10000
102 RX desc=512 - RX free threshold=0
103 RX threshold registers: pthresh=0 hthresh=0 wthresh=0
106 TX desc=512 - TX free threshold=0
107 TX threshold registers: pthresh=0 hthresh=0 wthresh=0
108 TX offloads=0x10000 - TX RS bit threshold=0
111 Runtime Config Options
112 ----------------------
114 - ``HW offload ptype parsing disable`` (default ``0``)
116 Packet type parsing is HW offloaded by default and this feature may be toggled
117 using ``ptype_disable`` ``devargs`` parameter.
119 - ``Rx&Tx scalar mode enable`` (default ``0``)
121 Ethdev supports both scalar and vector mode, it may be selected at runtime
122 using ``scalar_enable`` ``devargs`` parameter.
124 - ``RSS reta size`` (default ``64``)
126 RSS redirection table size may be configured during runtime using ``reta_size``
127 ``devargs`` parameter.
131 -w 0002:02:00.0,reta_size=256
133 With the above configuration, reta table of size 256 is populated.
135 - ``Flow priority levels`` (default ``3``)
137 RTE Flow priority levels can be configured during runtime using
138 ``flow_max_priority`` ``devargs`` parameter.
142 -w 0002:02:00.0,flow_max_priority=10
144 With the above configuration, priority level was set to 10 (0-9). Max
145 priority level supported is 32.
147 - ``Reserve Flow entries`` (default ``8``)
149 RTE flow entries can be pre allocated and the size of pre allocation can be
150 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
154 -w 0002:02:00.0,flow_prealloc_size=4
156 With the above configuration, pre alloc size was set to 4. Max pre alloc
157 size supported is 32.
159 - ``Max SQB buffer count`` (default ``512``)
161 Send queue descriptor buffer count may be limited during runtime using
162 ``max_sqb_count`` ``devargs`` parameter.
166 -w 0002:02:00.0,max_sqb_count=64
168 With the above configuration, each send queue's decscriptor buffer count is
169 limited to a maximum of 64 buffers.
174 Above devarg parameters are configurable per device, user needs to pass the
175 parameters to all the PCIe devices if application requires to configure on
176 all the ethdev ports.
181 ``mempool_octeontx2`` external mempool handler dependency
182 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
184 The OCTEON TX2 SoC family NIC has inbuilt HW assisted external mempool manager.
185 ``net_octeontx2`` pmd only works with ``mempool_octeontx2`` mempool handler
186 as it is performance wise most effective way for packet allocation and Tx buffer
187 recycling on OCTEON TX2 SoC platform.
192 The OCTEON TX2 SoC family NICs strip the CRC for every packet being received by
193 the host interface irrespective of the offload configuration.
199 .. _table_octeontx2_ethdev_debug_options:
201 .. table:: OCTEON TX2 ethdev debug options
203 +---+------------+-------------------------------------------------------+
204 | # | Component | EAL log command |
205 +===+============+=======================================================+
206 | 1 | NIX | --log-level='pmd\.net.octeontx2,8' |
207 +---+------------+-------------------------------------------------------+
208 | 2 | NPC | --log-level='pmd\.net.octeontx2\.flow,8' |
209 +---+------------+-------------------------------------------------------+
214 The OCTEON TX2 SoC family NIC has support for the following patterns and
219 .. _table_octeontx2_supported_flow_item_types:
221 .. table:: Item types
223 +----+--------------------------------+
225 +====+================================+
226 | 1 | RTE_FLOW_ITEM_TYPE_ETH |
227 +----+--------------------------------+
228 | 2 | RTE_FLOW_ITEM_TYPE_VLAN |
229 +----+--------------------------------+
230 | 3 | RTE_FLOW_ITEM_TYPE_E_TAG |
231 +----+--------------------------------+
232 | 4 | RTE_FLOW_ITEM_TYPE_IPV4 |
233 +----+--------------------------------+
234 | 5 | RTE_FLOW_ITEM_TYPE_IPV6 |
235 +----+--------------------------------+
236 | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|
237 +----+--------------------------------+
238 | 7 | RTE_FLOW_ITEM_TYPE_MPLS |
239 +----+--------------------------------+
240 | 8 | RTE_FLOW_ITEM_TYPE_ICMP |
241 +----+--------------------------------+
242 | 9 | RTE_FLOW_ITEM_TYPE_UDP |
243 +----+--------------------------------+
244 | 10 | RTE_FLOW_ITEM_TYPE_TCP |
245 +----+--------------------------------+
246 | 11 | RTE_FLOW_ITEM_TYPE_SCTP |
247 +----+--------------------------------+
248 | 12 | RTE_FLOW_ITEM_TYPE_ESP |
249 +----+--------------------------------+
250 | 13 | RTE_FLOW_ITEM_TYPE_GRE |
251 +----+--------------------------------+
252 | 14 | RTE_FLOW_ITEM_TYPE_NVGRE |
253 +----+--------------------------------+
254 | 15 | RTE_FLOW_ITEM_TYPE_VXLAN |
255 +----+--------------------------------+
256 | 16 | RTE_FLOW_ITEM_TYPE_GTPC |
257 +----+--------------------------------+
258 | 17 | RTE_FLOW_ITEM_TYPE_GTPU |
259 +----+--------------------------------+
260 | 18 | RTE_FLOW_ITEM_TYPE_GENEVE |
261 +----+--------------------------------+
262 | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE |
263 +----+--------------------------------+
264 | 20 | RTE_FLOW_ITEM_TYPE_VOID |
265 +----+--------------------------------+
266 | 21 | RTE_FLOW_ITEM_TYPE_ANY |
267 +----+--------------------------------+
271 .. _table_octeontx2_supported_ingress_action_types:
273 .. table:: Ingress action types
275 +----+--------------------------------+
277 +====+================================+
278 | 1 | RTE_FLOW_ACTION_TYPE_VOID |
279 +----+--------------------------------+
280 | 2 | RTE_FLOW_ACTION_TYPE_MARK |
281 +----+--------------------------------+
282 | 3 | RTE_FLOW_ACTION_TYPE_FLAG |
283 +----+--------------------------------+
284 | 4 | RTE_FLOW_ACTION_TYPE_COUNT |
285 +----+--------------------------------+
286 | 5 | RTE_FLOW_ACTION_TYPE_DROP |
287 +----+--------------------------------+
288 | 6 | RTE_FLOW_ACTION_TYPE_QUEUE |
289 +----+--------------------------------+
290 | 7 | RTE_FLOW_ACTION_TYPE_RSS |
291 +----+--------------------------------+
292 | 8 | RTE_FLOW_ACTION_TYPE_SECURITY |
293 +----+--------------------------------+
295 .. _table_octeontx2_supported_egress_action_types:
297 .. table:: Egress action types
299 +----+--------------------------------+
301 +====+================================+
302 | 1 | RTE_FLOW_ACTION_TYPE_COUNT |
303 +----+--------------------------------+
304 | 2 | RTE_FLOW_ACTION_TYPE_DROP |
305 +----+--------------------------------+