1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2019 Marvell International Ltd.
4 OCTEON TX2 Poll Mode driver
5 ===========================
7 The OCTEON TX2 ETHDEV PMD (**librte_pmd_octeontx2**) provides poll mode ethdev
8 driver support for the inbuilt network device found in **Marvell OCTEON TX2**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the OCTEON TX2 Ethdev PMD are:
22 - Receiver Side Scaling (RSS)
24 - Port hardware statistics
25 - Link state information
26 - Debug utilities - Context dump and error interrupt support
31 See :doc:`../platform/octeontx2` for setup information.
33 Compile time Config Options
34 ---------------------------
36 The following options may be modified in the ``config`` file.
38 - ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)
40 Toggle compilation of the ``librte_pmd_octeontx2`` driver.
42 Runtime Config Options
43 ----------------------
45 - ``HW offload ptype parsing disable`` (default ``0``)
47 Packet type parsing is HW offloaded by default and this feature may be toggled
48 using ``ptype_disable`` ``devargs`` parameter.
50 - ``Rx&Tx scalar mode enable`` (default ``0``)
52 Ethdev supports both scalar and vector mode, it may be selected at runtime
53 using ``scalar_enable`` ``devargs`` parameter.
55 - ``RSS reta size`` (default ``64``)
57 RSS redirection table size may be configured during runtime using ``reta_size``
58 ``devargs`` parameter.
62 -w 0002:02:00.0,reta_size=256
64 With the above configuration, reta table of size 256 is populated.
66 - ``Flow priority levels`` (default ``3``)
68 RTE Flow priority levels can be configured during runtime using
69 ``flow_max_priority`` ``devargs`` parameter.
73 -w 0002:02:00.0,flow_max_priority=10
75 With the above configuration, priority level was set to 10 (0-9). Max
76 priority level supported is 32.
78 - ``Reserve Flow entries`` (default ``8``)
80 RTE flow entries can be pre allocated and the size of pre allocation can be
81 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
85 -w 0002:02:00.0,flow_prealloc_size=4
87 With the above configuration, pre alloc size was set to 4. Max pre alloc
90 - ``Max SQB buffer count`` (default ``512``)
92 Send queue descriptor buffer count may be limited during runtime using
93 ``max_sqb_count`` ``devargs`` parameter.
97 -w 0002:02:00.0,max_sqb_count=64
99 With the above configuration, each send queue's decscriptor buffer count is
100 limited to a maximum of 64 buffers.
105 Above devarg parameters are configurable per device, user needs to pass the
106 parameters to all the PCIe devices if application requires to configure on
107 all the ethdev ports.