1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(C) 2019 Marvell International Ltd.
4 OCTEON TX2 Poll Mode driver
5 ===========================
7 The OCTEON TX2 ETHDEV PMD (**librte_pmd_octeontx2**) provides poll mode ethdev
8 driver support for the inbuilt network device found in **Marvell OCTEON TX2**
9 SoC family as well as for their virtual functions (VF) in SR-IOV context.
11 More information can be found at `Marvell Official Website
12 <https://www.marvell.com/embedded-processors/infrastructure-processors>`_.
17 Features of the OCTEON TX2 Ethdev PMD are:
23 See :doc:`../platform/octeontx2` for setup information.
25 Compile time Config Options
26 ---------------------------
28 The following options may be modified in the ``config`` file.
30 - ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)
32 Toggle compilation of the ``librte_pmd_octeontx2`` driver.
34 Runtime Config Options
35 ----------------------
37 - ``HW offload ptype parsing disable`` (default ``0``)
39 Packet type parsing is HW offloaded by default and this feature may be toggled
40 using ``ptype_disable`` ``devargs`` parameter.
42 - ``Rx&Tx scalar mode enable`` (default ``0``)
44 Ethdev supports both scalar and vector mode, it may be selected at runtime
45 using ``scalar_enable`` ``devargs`` parameter.
47 - ``RSS reta size`` (default ``64``)
49 RSS redirection table size may be configured during runtime using ``reta_size``
50 ``devargs`` parameter.
54 -w 0002:02:00.0,reta_size=256
56 With the above configuration, reta table of size 256 is populated.
58 - ``Flow priority levels`` (default ``3``)
60 RTE Flow priority levels can be configured during runtime using
61 ``flow_max_priority`` ``devargs`` parameter.
65 -w 0002:02:00.0,flow_max_priority=10
67 With the above configuration, priority level was set to 10 (0-9). Max
68 priority level supported is 32.
70 - ``Reserve Flow entries`` (default ``8``)
72 RTE flow entries can be pre allocated and the size of pre allocation can be
73 selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.
77 -w 0002:02:00.0,flow_prealloc_size=4
79 With the above configuration, pre alloc size was set to 4. Max pre alloc
82 - ``Max SQB buffer count`` (default ``512``)
84 Send queue descriptor buffer count may be limited during runtime using
85 ``max_sqb_count`` ``devargs`` parameter.
89 -w 0002:02:00.0,max_sqb_count=64
91 With the above configuration, each send queue's decscriptor buffer count is
92 limited to a maximum of 64 buffers.
97 Above devarg parameters are configurable per device, user needs to pass the
98 parameters to all the PCIe devices if application requires to configure on