1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2019 Marvell International Ltd.
4 Marvell OCTEON TX2 Platform Guide
5 =================================
7 This document gives an overview of **Marvell OCTEON TX2** RVU H/W block,
8 packet flow and procedure to build DPDK on OCTEON TX2 platform.
10 More information about OCTEON TX2 SoC can be found at `Marvell Official Website
11 <https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.
13 Supported OCTEON TX2 SoCs
14 -------------------------
19 OCTEON TX2 Resource Virtualization Unit architecture
20 ----------------------------------------------------
22 The :numref:`figure_octeontx2_resource_virtualization` diagram depicts the
23 RVU architecture and a resource provisioning example.
25 .. _figure_octeontx2_resource_virtualization:
27 .. figure:: img/octeontx2_resource_virtualization.*
29 OCTEON TX2 Resource virtualization architecture and provisioning example
32 Resource Virtualization Unit (RVU) on Marvell's OCTEON TX2 SoC maps HW
33 resources belonging to the network, crypto and other functional blocks onto
34 PCI-compatible physical and virtual functions.
36 Each functional block has multiple local functions (LFs) for
37 provisioning to different PCIe devices. RVU supports multiple PCIe SRIOV
38 physical functions (PFs) and virtual functions (VFs).
40 The :numref:`table_octeontx2_rvu_dpdk_mapping` shows the various local
41 functions (LFs) provided by the RVU and its functional mapping to
44 .. _table_octeontx2_rvu_dpdk_mapping:
46 .. table:: RVU managed functional blocks and its mapping to DPDK subsystem
48 +---+-----+--------------------------------------------------------------+
49 | # | LF | DPDK subsystem mapping |
50 +===+=====+==============================================================+
51 | 1 | NIX | rte_ethdev, rte_tm, rte_event_eth_[rt]x_adapter, rte_security|
52 +---+-----+--------------------------------------------------------------+
53 | 2 | NPA | rte_mempool |
54 +---+-----+--------------------------------------------------------------+
55 | 3 | NPC | rte_flow |
56 +---+-----+--------------------------------------------------------------+
57 | 4 | CPT | rte_cryptodev, rte_event_crypto_adapter |
58 +---+-----+--------------------------------------------------------------+
59 | 5 | SSO | rte_eventdev |
60 +---+-----+--------------------------------------------------------------+
61 | 6 | TIM | rte_event_timer_adapter |
62 +---+-----+--------------------------------------------------------------+
63 | 7 | LBK | rte_ethdev |
64 +---+-----+--------------------------------------------------------------+
65 | 8 | DPI | rte_rawdev |
66 +---+-----+--------------------------------------------------------------+
68 PF0 is called the administrative / admin function (AF) and has exclusive
69 privileges to provision RVU functional block's LFs to each of the PF/VF.
71 PF/VFs communicates with AF via a shared memory region (mailbox).Upon receiving
72 requests from PF/VF, AF does resource provisioning and other HW configuration.
74 AF is always attached to host, but PF/VFs may be used by host kernel itself,
75 or attached to VMs or to userspace applications like DPDK, etc. So, AF has to
76 handle provisioning/configuration requests sent by any device from any domain.
78 The AF driver does not receive or process any data.
79 It is only a configuration driver used in control path.
81 The :numref:`figure_octeontx2_resource_virtualization` diagram also shows a
82 resource provisioning example where,
84 1. PFx and PFx-VF0 bound to Linux netdev driver.
85 2. PFx-VF1 ethdev driver bound to the first DPDK application.
86 3. PFy ethdev driver, PFy-VF0 ethdev driver, PFz eventdev driver, PFm-VF0 cryptodev driver bound to the second DPDK application.
91 Loopback HW Unit (LBK) receives packets from NIX-RX and sends packets back to NIX-TX.
92 The loopback block has N channels and contains data buffering that is shared across
93 all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0's
94 VFs are exposed as ethdev device and odd-even pairs of VFs are tied together,
95 that is, packets sent on odd VF end up received on even VF and vice versa.
96 This would enable HW accelerated means of communication between two domains
97 where even VF bound to the first domain and odd VF bound to the second domain.
99 Typical application usage models are,
101 #. Communication between the Linux kernel and DPDK application.
102 #. Exception path to Linux kernel from DPDK application as SW ``KNI`` replacement.
103 #. Communication between two different DPDK applications.
105 OCTEON TX2 packet flow
106 ----------------------
108 The :numref:`figure_octeontx2_packet_flow_hw_accelerators` diagram depicts
109 the packet flow on OCTEON TX2 SoC in conjunction with use of various HW accelerators.
111 .. _figure_octeontx2_packet_flow_hw_accelerators:
113 .. figure:: img/octeontx2_packet_flow_hw_accelerators.*
115 OCTEON TX2 packet flow in conjunction with use of HW accelerators
120 This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
123 See :doc:`../nics/octeontx2` for NIX Ethdev driver information.
125 #. **Mempool Driver**
126 See :doc:`../mempool/octeontx2` for NPA mempool driver information.
128 #. **Event Device Driver**
129 See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
131 #. **DMA Rawdev Driver**
132 See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
134 Procedure to Setup Platform
135 ---------------------------
137 There are three main prerequisites for setting up DPDK on OCTEON TX2
140 1. **OCTEON TX2 Linux kernel driver**
142 The dependent kernel drivers can be obtained from the
143 `kernel.org <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/marvell/octeontx2>`_.
145 Alternatively, the Marvell SDK also provides the required kernel drivers.
147 Linux kernel should be configured with the following features enabled:
149 .. code-block:: console
151 # 64K pages enabled for better performance
152 CONFIG_ARM64_64K_PAGES=y
153 CONFIG_ARM64_VA_BITS_48=y
154 # huge pages support enabled
156 CONFIG_HUGETLB_PAGE=y
157 # VFIO enabled with TYPE1 IOMMU at minimum
158 CONFIG_VFIO_IOMMU_TYPE1=y
161 CONFIG_VFIO_NOIOMMU=y
163 CONFIG_VFIO_PCI_MMAP=y
166 # ARMv8.1 LSE atomics
167 CONFIG_ARM64_LSE_ATOMICS=y
169 CONFIG_OCTEONTX2_MBOX=y
170 CONFIG_OCTEONTX2_AF=y
171 # Enable if netdev PF driver required
172 CONFIG_OCTEONTX2_PF=y
173 # Enable if netdev VF driver required
174 CONFIG_OCTEONTX2_VF=y
175 CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y
176 # Enable if OCTEONTX2 DMA PF driver required
177 CONFIG_OCTEONTX2_DPI_PF=n
179 2. **ARM64 Linux Tool Chain**
181 For example, the *aarch64* Linaro Toolchain, which can be obtained from
182 `here <https://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/aarch64-linux-gnu/>`_.
184 Alternatively, the Marvell SDK also provides GNU GCC toolchain, which is
185 optimized for OCTEON TX2 CPU.
187 3. **Rootfile system**
189 Any *aarch64* supporting filesystem may be used. For example,
190 Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained
191 from `<http://cdimage.ubuntu.com/ubuntu-base/releases/16.04/release/ubuntu-base-16.04.1-base-arm64.tar.gz>`_.
193 Alternatively, the Marvell SDK provides the buildroot based root filesystem.
194 The SDK includes all the above prerequisites necessary to bring up the OCTEON TX2 board.
196 - Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment.
202 .. _table_octeontx2_common_debug_options:
204 .. table:: OCTEON TX2 common debug options
206 +---+------------+-------------------------------------------------------+
207 | # | Component | EAL log command |
208 +===+============+=======================================================+
209 | 1 | Common | --log-level='pmd\.octeontx2\.base,8' |
210 +---+------------+-------------------------------------------------------+
211 | 2 | Mailbox | --log-level='pmd\.octeontx2\.mbox,8' |
212 +---+------------+-------------------------------------------------------+
217 The **OCTEON TX2 Linux kernel driver** provides support to dump RVU blocks
218 context or stats using debugfs.
220 Enable ``debugfs`` by:
222 1. Compile kernel with debugfs enabled, i.e ``CONFIG_DEBUGFS=y``.
223 2. Boot OCTEON TX2 with debugfs supported kernel.
224 3. Verify ``debugfs`` mounted by default "mount | grep -i debugfs" or mount it manually by using.
226 .. code-block:: console
228 # mount -t debugfs none /sys/kernel/debug
230 Currently ``debugfs`` supports the following RVU blocks NIX, NPA, NPC, NDC,
233 The file structure under ``/sys/kernel/debug`` is as follows
235 .. code-block:: console
251 | |-- cpt_engines_info
252 | |-- cpt_engines_sts
259 | |-- ndc_rx_hits_miss
261 | |-- ndc_tx_hits_miss
265 | '-- tx_stall_hwissue
274 | '-- rx_miss_act_stats
280 |-- sso_hwgrp_aq_thresh
281 |-- sso_hwgrp_iaq_walk
283 |-- sso_hwgrp_free_list_walk
284 |-- sso_hwgrp_ient_walk
285 '-- sso_hwgrp_taq_walk
287 RVU block LF allocation:
289 .. code-block:: console
291 cat /sys/kernel/debug/octeontx2/rsrc_alloc
293 pcifunc NPA NIX SSO GROUP SSOWS TIM CPT
300 .. code-block:: console
302 cat /sys/kernel/debug/octeontx2/cgx/cgx2/lmac0/stats
304 =======Link Status======
305 Link is UP 40000 Mbps
306 =======RX_STATS======
308 Octets of received packets: 0
309 Received PAUSE packets: 0
310 Received PAUSE and control packets: 0
311 Filtered DMAC0 (NIX-bound) packets: 0
312 Filtered DMAC0 (NIX-bound) octets: 0
313 Packets dropped due to RX FIFO full: 0
314 Octets dropped due to RX FIFO full: 0
316 Filtered DMAC1 (NCSI-bound) packets: 0
317 Filtered DMAC1 (NCSI-bound) octets: 0
318 NCSI-bound packets dropped: 0
319 NCSI-bound octets dropped: 0
320 =======TX_STATS======
321 Packets dropped due to excessive collisions: 0
322 Packets dropped due to excessive deferral: 0
323 Multiple collisions before successful transmission: 0
324 Single collisions before successful transmission: 0
325 Total octets sent on the interface: 0
326 Total frames sent on the interface: 0
327 Packets sent with an octet count < 64: 0
328 Packets sent with an octet count == 64: 0
329 Packets sent with an octet count of 65127: 0
330 Packets sent with an octet count of 128-255: 0
331 Packets sent with an octet count of 256-511: 0
332 Packets sent with an octet count of 512-1023: 0
333 Packets sent with an octet count of 1024-1518: 0
334 Packets sent with an octet count of > 1518: 0
335 Packets sent to a broadcast DMAC: 0
336 Packets sent to the multicast DMAC: 0
337 Transmit underflow and were truncated: 0
338 Control/PAUSE packets sent: 0
342 .. code-block:: console
344 cat /sys/kernel/debug/octeontx2/cpt/cpt_pc
346 CPT instruction requests 0
347 CPT instruction latency 0
348 CPT NCB read requests 0
349 CPT NCB read latency 0
350 CPT read requests caused by UC fills 0
351 CPT active cycles pc 1395642
352 CPT clock count pc 5579867595493
356 .. code-block:: console
358 Usage: echo <nixlf> [cq number/all] > /sys/kernel/debug/octeontx2/nix/cq_ctx
359 cat /sys/kernel/debug/octeontx2/nix/cq_ctx
360 echo 0 0 > /sys/kernel/debug/octeontx2/nix/cq_ctx
361 cat /sys/kernel/debug/octeontx2/nix/cq_ctx
363 =====cq_ctx for nixlf:0 and qidx:0 is=====
374 W2: update_time 31043
391 .. code-block:: console
393 Usage: echo <npalf> [pool number/all] > /sys/kernel/debug/octeontx2/npa/pool_ctx
394 cat /sys/kernel/debug/octeontx2/npa/pool_ctx
395 echo 0 0 > /sys/kernel/debug/octeontx2/npa/pool_ctx
396 cat /sys/kernel/debug/octeontx2/npa/pool_ctx
398 ======POOL : 0=======
399 W0: Stack base 1375bff00
406 W2: stack_max_pages 24315
407 W2: stack_pages 24314
417 W4: update_time 62993
419 W6: ptr_start 1593adf00
420 W7: ptr_end 180000000
426 W8: thresh_qint_idx 0
431 .. code-block:: console
433 cat /sys/kernel/debug/octeontx2/npc/mcam_info
436 RX keywidth : 224bits
437 TX keywidth : 224bits
449 .. code-block:: console
451 Usage: echo [<hws>/all] > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info
452 echo 0 > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info
454 ==================================================
455 SSOW HWS[0] Arbitration State 0x0
456 SSOW HWS[0] Guest Machine Control 0x0
457 SSOW HWS[0] SET[0] Group Mask[0] 0xffffffffffffffff
458 SSOW HWS[0] SET[0] Group Mask[1] 0xffffffffffffffff
459 SSOW HWS[0] SET[0] Group Mask[2] 0xffffffffffffffff
460 SSOW HWS[0] SET[0] Group Mask[3] 0xffffffffffffffff
461 SSOW HWS[0] SET[1] Group Mask[0] 0xffffffffffffffff
462 SSOW HWS[0] SET[1] Group Mask[1] 0xffffffffffffffff
463 SSOW HWS[0] SET[1] Group Mask[2] 0xffffffffffffffff
464 SSOW HWS[0] SET[1] Group Mask[3] 0xffffffffffffffff
465 ==================================================
470 DPDK may be compiled either natively on OCTEON TX2 platform or cross-compiled on
471 an x86 based platform.
479 .. code-block:: console
481 make config T=arm64-octeontx2-linux-gcc
484 The example applications can be compiled using the following:
486 .. code-block:: console
490 export RTE_TARGET=build
491 cd examples/<application>
497 .. code-block:: console
505 Refer to :doc:`../linux_gsg/cross_build_dpdk_for_arm64` for generic arm64 details.
510 .. code-block:: console
512 make config T=arm64-octeontx2-linux-gcc
513 make -j CROSS=aarch64-marvell-linux-gnu- CONFIG_RTE_KNI_KMOD=n
518 .. code-block:: console
520 meson build --cross-file config/arm/arm64_octeontx2_linux_gcc
525 By default, meson cross compilation uses ``aarch64-linux-gnu-gcc`` toolchain,
526 if Marvell toolchain is available then it can be used by overriding the
527 c, cpp, ar, strip ``binaries`` attributes to respective Marvell
528 toolchain binaries in ``config/arm/arm64_octeontx2_linux_gcc`` file.