2 Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions
9 * Redistributions of source code must retain the above copyright
10 notice, this list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright
12 notice, this list of conditions and the following disclaimer in
13 the documentation and/or other materials provided with the
15 * Neither the name of Intel Corporation nor the names of its
16 contributors may be used to endorse or promote products derived
17 from this software without specific prior written permission.
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 =============== =========================================================================================================
36 =============== =========================================================================================================
37 ACL Access Control List
39 API Application Programming Interface
41 ASLR Linux* kernel Address-Space Layout Randomization
43 BSD Berkeley Software Distribution
47 CIDR Classless Inter-Domain Routing
49 Control Plane The control plane is concerned with the routing of packets and with providing a start or end point.
51 Core A core may include several lcores or threads if the processor supports hyperthreading.
53 Core Components A set of libraries provided by the Intel® DPDK, including eal, ring, mempool, mbuf, timers, and so on.
55 CPU Central Processing Unit
57 CRC Cyclic Redundancy Check
59 ctrlmbuf An *mbuf* carrying control data.
61 Data Plane In contrast to the control plane,
62 the data plane in a network architecture are the layers involved when forwarding packets.
63 These layers must be highly optimized to achieve good performance.
65 DIMM Dual In-line Memory Module
67 Doxygen A documentation generator used in the Intel® DPDK to generate the API reference.
69 DPDK Data Plane Development Kit
71 DRAM Dynamic Random Access Memory
73 EAL The Environment Abstraction Layer (EAL) provides a generic interface that hides the environment specifics
74 from the applications and libraries.
75 The services expected from the EAL are:
76 development kit loading and launching, core affinity/ assignment procedures,
77 system memory allocation/description, PCI bus access, inter-partition communication.
79 FIFO First In First Out
81 FPGA Field Programmable Gate Array
87 HPET High Precision Event Timer;
88 a hardware timer that provides a precise time reference on x86 platforms.
92 IOCTL Input/Output Control
98 IPv4 Internet Protocol version 4
100 IPv6 Internet Protocol version 6
102 lcore A logical execution unit of the processor, sometimes called a *hardware thread*.
104 KNI Kernel Network Interface
114 LAN Local Area Network
116 LPM Longest Prefix Match
118 master lcore The execution unit that executes the main() function and that launches other lcores.
120 mbuf An mbuf is a data structure used internally to carry messages (mainly network packets).
121 The name is derived from BSD stacks.
122 To understand the concepts of packet buffers or mbuf,
123 refer to *TCP/IP Illustrated, Volume 2: The Implementation*.
125 MESI Modified Exclusive Shared Invalid (CPU cache coherency protocol)
127 MTU Maximum Transfer Unit
129 NIC Network Interface Card
131 OOO Out Of Order (execution of instructions within the CPU pipeline)
133 NUMA Non-uniform Memory Access
135 PCI Peripheral Connect Interface
137 PHY An abbreviation for the physical layer of the OSI model.
139 pktmbuf An *mbuf* carrying a network packet.
143 QoS Quality of Service
145 RCU Read-Copy-Update algorithm, an alternative to simple rwlocks.
149 RED Random Early Detection
151 RSS Receive Side Scaling
153 RTE Run Time Environment.
154 Provides a fast and simple framework for fast packet processing,
155 in a lightweight environment as a Linux* application and
156 using Poll Mode Drivers (PMDs) to increase speed.
160 Slave lcore Any *lcore* that is not the *master lcore*.
162 Socket A physical CPU, that includes several *cores*.
164 SLA Service Level Agreement
166 srTCM Single Rate Three Color Marking
168 SRTD Scheduler Round Trip Delay
172 Target In the Intel® DPDK, the target is a combination of architecture,
173 machine, executive environment and toolchain.
174 For example: i686-native-linuxapp-gcc.
176 TCP Transmission Control Protocol
180 TLB Translation Lookaside Buffer
182 TLS Thread Local Storage
184 trTCM Two Rate Three Color Marking
186 TSC Time Stamp Counter
190 TUN/TAP TUN and TAP are virtual network kernel devices.
192 VLAN Virtual Local Area Network
196 WRED Weighted Random Early Detection
198 WRR Weighted Round Robin
199 =============== =========================================================================================================