1 .. SPDX-License-Identifier: BSD-3-Clause
2 Copyright(c) 2010-2014 Intel Corporation.
4 Profile Your Application
5 ========================
7 The following sections describe methods of profiling DPDK applications on
8 different architectures.
14 Intel processors provide performance counters to monitor events.
15 Some tools provided by Intel, such as Intel® VTune™ Amplifier, can be used
16 to profile and benchmark an application.
17 See the *VTune Performance Analyzer Essentials* publication from Intel Press for more information.
19 For a DPDK application, this can be done in a Linux* application environment only.
21 The main situations that should be monitored through event counters are:
29 * Long latency instructions and exceptions
32 `Intel Performance Analysis Guide <http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf>`_
33 for details about application profiling.
39 To allow VTune attaching to the DPDK application, reconfigure and recompile
40 the DPDK with ``CONFIG_RTE_ETHDEV_RXTX_CALLBACKS`` and
41 ``CONFIG_RTE_ETHDEV_PROFILE_WITH_VTUNE`` enabled.
50 The ARM64 architecture provide performance counters to monitor events. The
51 Linux ``perf`` tool can be used to profile and benchmark an application. In
52 addition to the standard events, ``perf`` can be used to profile arm64
53 specific PMU (Performance Monitor Unit) events through raw events (``-e``
56 For more derails refer to the
57 `ARM64 specific PMU events enumeration <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100095_0002_04_en/way1382543438508.html>`_.
60 Low-resolution generic counter
61 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
63 The default ``cntvct_el0`` based ``rte_rdtsc()`` provides a portable means to
64 get a wall clock counter in user space. Typically it runs at a lower clock frequency than the CPU clock frequency.
65 Cycles counted using this method should be scaled to CPU clock frequency.
68 High-resolution cycle counter
69 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
71 The alternative method to enable ``rte_rdtsc()`` for a high resolution wall
72 clock counter is through the ARMv8 PMU subsystem. The PMU cycle counter runs
73 at CPU frequency. However, access to the PMU cycle counter from user space is
74 not enabled by default in the arm64 linux kernel. It is possible to enable
75 cycle counter for user space access by configuring the PMU from the privileged
78 By default the ``rte_rdtsc()`` implementation uses a portable ``cntvct_el0``
79 scheme. Application can choose the PMU based implementation with
80 ``CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU``.
82 The example below shows the steps to configure the PMU based cycle counter on
85 .. code-block:: console
87 git clone https://github.com/jerinjacobk/armv8_pmu_cycle_counter_el0
88 cd armv8_pmu_cycle_counter_el0
90 sudo insmod pmu_el0_cycle_counter.ko
92 make config T=arm64-armv8a-linux-gcc
93 echo "CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU=y" >> build/.config
98 The PMU based scheme is useful for high accuracy performance profiling with
99 ``rte_rdtsc()``. However, this method can not be used in conjunction with
100 Linux userspace profiling tools like ``perf`` as this scheme alters the PMU