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5 * Copyright (c) 2016 NXP. All rights reserved.
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34 #ifndef _DPAA2_HW_PVT_H_
35 #define _DPAA2_HW_PVT_H_
37 #include <mc/fsl_mc_sys.h>
38 #include <fsl_qbman_portal.h>
46 #define lower_32_bits(x) ((uint32_t)(x))
47 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
50 #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */
53 #define MAX_TX_RING_SLOTS 8
54 /** <Maximum number of slots available in TX ring*/
56 #define DPAA2_DQRR_RING_SIZE 16
57 /** <Maximum number of slots available in RX ring*/
59 #define MC_PORTAL_INDEX 0
60 #define NUM_DPIO_REGIONS 2
61 #define NUM_DQS_PER_QUEUE 2
63 /* Maximum release/acquire from QBMAN */
64 #define DPAA2_MBUF_MAX_ACQ_REL 7
67 #define DPAA2_MBUF_HW_ANNOTATION 64
68 #define DPAA2_FD_PTA_SIZE 0
70 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
71 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
74 /* we will re-use the HEADROOM for annotation in RX */
75 #define DPAA2_HW_BUF_RESERVE 0
76 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
78 struct dpaa2_dpio_dev {
79 TAILQ_ENTRY(dpaa2_dpio_dev) next;
80 /**< Pointer to Next device instance */
81 uint16_t index; /**< Index of a instance in the list */
82 rte_atomic16_t ref_count;
83 /**< How many thread contexts are sharing this.*/
84 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
86 struct qbman_swp *sw_portal; /** SW portal object */
87 const struct qbman_result *dqrr[4];
88 /**< DQRR Entry for this SW portal */
89 void *mc_portal; /**< MC Portal for configuring this device */
90 uintptr_t qbman_portal_ce_paddr;
91 /**< Physical address of Cache Enabled Area */
92 uintptr_t ce_size; /**< Size of the CE region */
93 uintptr_t qbman_portal_ci_paddr;
94 /**< Physical address of Cache Inhibit Area */
95 uintptr_t ci_size; /**< Size of the CI region */
96 int32_t vfio_fd; /**< File descriptor received via VFIO */
97 int32_t hw_id; /**< An unique ID of this DPIO device instance */
100 struct dpaa2_dpbp_dev {
101 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
102 /**< Pointer to Next device instance */
103 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
105 rte_atomic16_t in_use;
106 uint32_t dpbp_id; /*HW ID for DPBP object */
109 struct queue_storage_info_t {
110 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
114 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
116 int32_t eventfd; /*!< Event Fd of this queue */
117 uint32_t fqid; /*!< Unique ID of this queue */
118 uint8_t tc_index; /*!< traffic class identifier */
119 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
123 struct queue_storage_info_t *q_storage;
126 /*! Global MCP list */
127 extern void *(*rte_mcp_ptr_list);
129 /* Refer to Table 7-3 in SEC BG */
134 /* FMT must be 00, MSB is final bit */
135 uint32_t fin_bpid_offset;
137 uint32_t reserved[3]; /* Not used currently */
140 /*Macros to define operations on FD*/
141 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
142 fd->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
143 fd->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
145 #define DPAA2_SET_FD_LEN(fd, length) (fd)->simple.len = length
146 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
147 #define DPAA2_SET_FD_IVP(fd) ((fd->simple.bpid_offset |= 0x00004000))
148 #define DPAA2_SET_FD_OFFSET(fd, offset) \
149 ((fd->simple.bpid_offset |= (uint32_t)(offset) << 16))
150 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) fd->simple.frc = (0x80000000 | (len))
151 #define DPAA2_SET_FD_FRC(fd, frc) fd->simple.frc = frc
152 #define DPAA2_RESET_FD_CTRL(fd) (fd)->simple.ctrl = 0
154 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
155 #define DPAA2_SET_FD_FLC(fd, addr) do { \
156 fd->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
157 fd->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
159 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) (fle->frc = (0x80000000 | (len)))
160 #define DPAA2_GET_FLE_ADDR(fle) \
161 (uint64_t)((((uint64_t)(fle->addr_hi)) << 32) + fle->addr_lo)
162 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
163 fle->addr_lo = lower_32_bits((uint64_t)addr); \
164 fle->addr_hi = upper_32_bits((uint64_t)addr); \
166 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
167 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
168 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
169 #define DPAA2_GET_FLE_BPID(fle, bpid) (fle->fin_bpid_offset & 0x000000ff)
170 #define DPAA2_SET_FLE_FIN(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 31)
171 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
172 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
173 (fd->simple.bpid_offset |= (uint32_t)1 << 28)
174 #define DPAA2_GET_FD_ADDR(fd) \
175 ((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
177 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
178 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
179 #define DPAA2_GET_FD_IVP(fd) ((fd->simple.bpid_offset & 0x00004000) >> 14)
180 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
181 #define DPAA2_SET_FLE_SG_EXT(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 29)
182 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
183 ((fle->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
185 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
186 ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
188 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
190 /* Only Enqueue Error responses will be
191 * pushed on FQID_ERR of Enqueue FQ
193 #define DPAA2_EQ_RESP_ERR_FQ 0
194 /* All Enqueue responses will be pushed on address
195 * set with qbman_eq_desc_set_response
197 #define DPAA2_EQ_RESP_ALWAYS 1
199 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
200 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
201 /* todo - this is costly, need to write a fast coversion routine */
202 static void *dpaa2_mem_ptov(phys_addr_t paddr)
204 const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
207 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
208 if (paddr >= memseg[i].phys_addr &&
209 (char *)paddr < (char *)memseg[i].phys_addr + memseg[i].len)
210 return (void *)(memseg[i].addr_64
211 + (paddr - memseg[i].phys_addr));
216 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
217 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
219 const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
222 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
223 if (vaddr >= memseg[i].addr_64 &&
224 vaddr < memseg[i].addr_64 + memseg[i].len)
225 return memseg[i].phys_addr
226 + (vaddr - memseg[i].addr_64);
228 return (phys_addr_t)(NULL);
232 * When we are using Physical addresses as IO Virtual Addresses,
233 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
234 * whereever required.
235 * These routines are called with help of below MACRO's
238 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_physaddr)
239 #define DPAA2_OP_VADDR_TO_IOVA(op) (op->phys_addr)
242 * macro to convert Virtual address to IOVA
244 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
247 * macro to convert IOVA to Virtual address
249 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
252 * macro to convert modify the memory containing IOVA to Virtual address
254 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
255 {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
257 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
259 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
260 #define DPAA2_OP_VADDR_TO_IOVA(op) (op)
261 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
262 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
263 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
265 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
267 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
268 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);