drivers/baseband/acc100/acc100_vf_enum.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef ACC100_VF_ENUM_H
   6 #define ACC100_VF_ENUM_H
   7
   8 /*
   9  * ACC100 Register mapping on VF BAR0
  10  * This is automatically generated from RDL, format may change with new RDL
  11  */
  12 enum {
  13         HWVfQmgrIngressAq             =  0x00000000,
  14         HWVfHiVfToPfDbellVf           =  0x00000800,
  15         HWVfHiPfToVfDbellVf           =  0x00000808,
  16         HWVfHiInfoRingBaseLoVf        =  0x00000810,
  17         HWVfHiInfoRingBaseHiVf        =  0x00000814,
  18         HWVfHiInfoRingPointerVf       =  0x00000818,
  19         HWVfHiInfoRingIntWrEnVf       =  0x00000820,
  20         HWVfHiInfoRingPf2VfWrEnVf     =  0x00000824,
  21         HWVfHiMsixVectorMapperVf      =  0x00000860,
  22         HWVfDmaFec5GulDescBaseLoRegVf =  0x00000920,
  23         HWVfDmaFec5GulDescBaseHiRegVf =  0x00000924,
  24         HWVfDmaFec5GulRespPtrLoRegVf  =  0x00000928,
  25         HWVfDmaFec5GulRespPtrHiRegVf  =  0x0000092C,
  26         HWVfDmaFec5GdlDescBaseLoRegVf =  0x00000940,
  27         HWVfDmaFec5GdlDescBaseHiRegVf =  0x00000944,
  28         HWVfDmaFec5GdlRespPtrLoRegVf  =  0x00000948,
  29         HWVfDmaFec5GdlRespPtrHiRegVf  =  0x0000094C,
  30         HWVfDmaFec4GulDescBaseLoRegVf =  0x00000960,
  31         HWVfDmaFec4GulDescBaseHiRegVf =  0x00000964,
  32         HWVfDmaFec4GulRespPtrLoRegVf  =  0x00000968,
  33         HWVfDmaFec4GulRespPtrHiRegVf  =  0x0000096C,
  34         HWVfDmaFec4GdlDescBaseLoRegVf =  0x00000980,
  35         HWVfDmaFec4GdlDescBaseHiRegVf =  0x00000984,
  36         HWVfDmaFec4GdlRespPtrLoRegVf  =  0x00000988,
  37         HWVfDmaFec4GdlRespPtrHiRegVf  =  0x0000098C,
  38         HWVfDmaDdrBaseRangeRoVf       =  0x000009A0,
  39         HWVfQmgrAqResetVf             =  0x00000E00,
  40         HWVfQmgrRingSizeVf            =  0x00000E04,
  41         HWVfQmgrGrpDepthLog20Vf       =  0x00000E08,
  42         HWVfQmgrGrpDepthLog21Vf       =  0x00000E0C,
  43         HWVfQmgrGrpFunction0Vf        =  0x00000E10,
  44         HWVfQmgrGrpFunction1Vf        =  0x00000E14,
  45         HWVfPmACntrlRegVf             =  0x00000F40,
  46         HWVfPmACountVf                =  0x00000F48,
  47         HWVfPmAKCntLoVf               =  0x00000F50,
  48         HWVfPmAKCntHiVf               =  0x00000F54,
  49         HWVfPmADeltaCntLoVf           =  0x00000F60,
  50         HWVfPmADeltaCntHiVf           =  0x00000F64,
  51         HWVfPmBCntrlRegVf             =  0x00000F80,
  52         HWVfPmBCountVf                =  0x00000F88,
  53         HWVfPmBKCntLoVf               =  0x00000F90,
  54         HWVfPmBKCntHiVf               =  0x00000F94,
  55         HWVfPmBDeltaCntLoVf           =  0x00000FA0,
  56         HWVfPmBDeltaCntHiVf           =  0x00000FA4
  57 };
  58
  59 /* TIP VF Interrupt numbers */
  60 enum {
  61         ACC100_VF_INT_QMGR_AQ_OVERFLOW = 0,
  62         ACC100_VF_INT_DOORBELL_VF_2_PF = 1,
  63         ACC100_VF_INT_DMA_DL_DESC_IRQ = 2,
  64         ACC100_VF_INT_DMA_UL_DESC_IRQ = 3,
  65         ACC100_VF_INT_DMA_MLD_DESC_IRQ = 4,
  66         ACC100_VF_INT_DMA_UL5G_DESC_IRQ = 5,
  67         ACC100_VF_INT_DMA_DL5G_DESC_IRQ = 6,
  68         ACC100_VF_INT_ILLEGAL_FORMAT = 7,
  69         ACC100_VF_INT_QMGR_DISABLED_ACCESS = 8,
  70         ACC100_VF_INT_QMGR_AQ_OVERTHRESHOLD = 9,
  71 };
  72
  73 #endif /* ACC100_VF_ENUM_H */