1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
5 #ifndef _RTE_ACC100_PMD_H_
6 #define _RTE_ACC100_PMD_H_
8 #include "acc100_pf_enum.h"
9 #include "acc100_vf_enum.h"
10 #include "rte_acc100_cfg.h"
12 /* Helper macro for logging */
13 #define rte_bbdev_log(level, fmt, ...) \
14 rte_log(RTE_LOG_ ## level, acc100_logtype, fmt "\n", \
17 #ifdef RTE_LIBRTE_BBDEV_DEBUG
18 #define rte_bbdev_log_debug(fmt, ...) \
19 rte_bbdev_log(DEBUG, "acc100_pmd: " fmt, \
22 #define rte_bbdev_log_debug(fmt, ...)
25 /* ACC100 PF and VF driver names */
26 #define ACC100PF_DRIVER_NAME intel_acc100_pf
27 #define ACC100VF_DRIVER_NAME intel_acc100_vf
29 /* ACC100 PCI vendor & device IDs */
30 #define RTE_ACC100_VENDOR_ID (0x8086)
31 #define RTE_ACC100_PF_DEVICE_ID (0x0d5c)
32 #define RTE_ACC100_VF_DEVICE_ID (0x0d5d)
34 /* Define as 1 to use only a single FEC engine */
35 #ifndef RTE_ACC100_SINGLE_FEC
36 #define RTE_ACC100_SINGLE_FEC 0
39 /* Values used in filling in descriptors */
40 #define ACC100_DMA_DESC_TYPE 2
41 #define ACC100_DMA_CODE_BLK_MODE 0
42 #define ACC100_DMA_BLKID_FCW 1
43 #define ACC100_DMA_BLKID_IN 2
44 #define ACC100_DMA_BLKID_OUT_ENC 1
45 #define ACC100_DMA_BLKID_OUT_HARD 1
46 #define ACC100_DMA_BLKID_OUT_SOFT 2
47 #define ACC100_DMA_BLKID_OUT_HARQ 3
48 #define ACC100_DMA_BLKID_IN_HARQ 3
50 /* Values used in filling in decode FCWs */
51 #define ACC100_FCW_TD_VER 1
52 #define ACC100_FCW_TD_EXT_COLD_REG_EN 1
53 #define ACC100_FCW_TD_AUTOMAP 0x0f
54 #define ACC100_FCW_TD_RVIDX_0 2
55 #define ACC100_FCW_TD_RVIDX_1 26
56 #define ACC100_FCW_TD_RVIDX_2 50
57 #define ACC100_FCW_TD_RVIDX_3 74
59 /* Values used in writing to the registers */
60 #define ACC100_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
62 /* ACC100 Specific Dimensioning */
63 #define ACC100_SIZE_64MBYTE (64*1024*1024)
64 /* Number of elements in an Info Ring */
65 #define ACC100_INFO_RING_NUM_ENTRIES 1024
66 /* Number of elements in HARQ layout memory */
67 #define ACC100_HARQ_LAYOUT (64*1024*1024)
68 /* Assume offset for HARQ in memory */
69 #define ACC100_HARQ_OFFSET (32*1024)
70 /* Mask used to calculate an index in an Info Ring array (not a byte offset) */
71 #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
72 /* Number of Virtual Functions ACC100 supports */
73 #define ACC100_NUM_VFS 16
74 #define ACC100_NUM_QGRPS 8
75 #define ACC100_NUM_QGRPS_PER_WORD 8
76 #define ACC100_NUM_AQS 16
77 #define MAX_ENQ_BATCH_SIZE 255
78 /* All ACC100 Registers alignment are 32bits = 4B */
79 #define ACC100_BYTES_IN_WORD 4
80 #define ACC100_MAX_E_MBUF 64000
82 #define ACC100_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
83 #define ACC100_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
84 #define ACC100_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */
85 #define ACC100_TMPL_PRI_0 0x03020100
86 #define ACC100_TMPL_PRI_1 0x07060504
87 #define ACC100_TMPL_PRI_2 0x0b0a0908
88 #define ACC100_TMPL_PRI_3 0x0f0e0d0c
89 #define ACC100_QUEUE_ENABLE 0x80000000 /* Bit to mark Queue as Enabled */
90 #define ACC100_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
91 #define ACC100_FDONE 0x80000000
92 #define ACC100_SDONE 0x40000000
94 #define ACC100_NUM_TMPL 32
95 /* Mapping of signals for the available engines */
96 #define ACC100_SIG_UL_5G 0
97 #define ACC100_SIG_UL_5G_LAST 7
98 #define ACC100_SIG_DL_5G 13
99 #define ACC100_SIG_DL_5G_LAST 15
100 #define ACC100_SIG_UL_4G 16
101 #define ACC100_SIG_UL_4G_LAST 21
102 #define ACC100_SIG_DL_4G 27
103 #define ACC100_SIG_DL_4G_LAST 31
104 #define ACC100_NUM_ACCS 5
105 #define ACC100_ACCMAP_0 0
106 #define ACC100_ACCMAP_1 2
107 #define ACC100_ACCMAP_2 1
108 #define ACC100_ACCMAP_3 3
109 #define ACC100_ACCMAP_4 4
110 #define ACC100_PF_VAL 2
112 /* max number of iterations to allocate memory block for all rings */
113 #define ACC100_SW_RING_MEM_ALLOC_ATTEMPTS 5
114 #define ACC100_MAX_QUEUE_DEPTH 1024
115 #define ACC100_DMA_MAX_NUM_POINTERS 14
116 #define ACC100_DMA_DESC_PADDING 8
117 #define ACC100_FCW_PADDING 12
118 #define ACC100_DESC_FCW_OFFSET 192
119 #define ACC100_DESC_SIZE 256
120 #define ACC100_DESC_OFFSET (ACC100_DESC_SIZE / 64)
121 #define ACC100_FCW_TE_BLEN 32
122 #define ACC100_FCW_TD_BLEN 24
123 #define ACC100_FCW_LE_BLEN 32
124 #define ACC100_FCW_LD_BLEN 36
125 #define ACC100_5GUL_SIZE_0 16
126 #define ACC100_5GUL_SIZE_1 40
127 #define ACC100_5GUL_OFFSET_0 36
129 #define ACC100_FCW_VER 2
130 #define ACC100_MUX_5GDL_DESC 6
131 #define ACC100_CMP_ENC_SIZE 20
132 #define ACC100_CMP_DEC_SIZE 24
133 #define ACC100_ENC_OFFSET (32)
134 #define ACC100_DEC_OFFSET (80)
135 #define ACC100_EXT_MEM /* Default option with memory external to CPU */
136 #define ACC100_HARQ_OFFSET_THRESHOLD 1024
138 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
139 #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */
140 #define ACC100_N_ZC_2 50 /* N = 50 Zc for BG 2 */
141 #define ACC100_K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
142 #define ACC100_K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
143 #define ACC100_K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
144 #define ACC100_K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
145 #define ACC100_K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
146 #define ACC100_K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
148 /* ACC100 Configuration */
149 #define ACC100_DDR_ECC_ENABLE
150 #define ACC100_CFG_DMA_ERROR 0x3D7
151 #define ACC100_CFG_AXI_CACHE 0x11
152 #define ACC100_CFG_QMGR_HI_P 0x0F0F
153 #define ACC100_CFG_PCI_AXI 0xC003
154 #define ACC100_CFG_PCI_BRIDGE 0x40006033
155 #define ACC100_ENGINE_OFFSET 0x1000
156 #define ACC100_RESET_HI 0x20100
157 #define ACC100_RESET_LO 0x20000
158 #define ACC100_RESET_HARD 0x1FF
159 #define ACC100_ENGINES_MAX 9
160 #define ACC100_LONG_WAIT 1000
161 #define ACC100_GPEX_AXIMAP_NUM 17
163 /* ACC100 DMA Descriptor triplet */
164 struct acc100_dma_triplet {
174 /* ACC100 DMA Response Descriptor */
175 union acc100_dma_rsp_desc {
178 uint32_t crc_status:1,
197 /* ACC100 Queue Manager Enqueue PCI Register */
198 union acc100_enqueue_reg_fmt {
208 /* FEC 4G Uplink Frame Control Word */
209 struct __rte_packed acc100_fcw_td {
211 num_maps:4; /* Unused */
212 uint8_t filler:6, /* Unused */
216 uint16_t k_neg; /* Unused */
217 uint8_t c_neg; /* Unused */
218 uint8_t c; /* Unused */
219 uint32_t ea; /* Unused */
220 uint32_t eb; /* Unused */
221 uint8_t cab; /* Unused */
222 uint8_t k0_start_col; /* Unused */
224 uint8_t code_block_mode:1, /* Unused */
227 bypass_teq:1, /* Unused */
228 soft_output_en:1, /* Unused */
229 ext_td_cold_reg_en:1;
230 union { /* External Cold register */
231 uint32_t ext_td_cold_reg;
233 uint32_t min_iter:4, /* Unused */
235 ext_scale:5, /* Unused */
237 early_stop_en:1, /* Unused */
238 sw_soft_out_dis:1, /* Unused */
239 sw_et_cont:1, /* Unused */
240 sw_soft_out_saturation:1, /* Unused */
241 half_iter_on:1, /* Unused */
242 raw_decoder_input_on:1, /* Unused */
248 /* FEC 5GNR Uplink Frame Control Word */
249 struct __rte_packed acc100_fcw_ld {
250 uint32_t FCWversion:4,
269 uint32_t hcin_offset:16,
271 uint32_t hcin_size1:16,
283 uint32_t hcout_size0:16,
288 uint32_t negstop_it:7,
293 /* FEC 4G Downlink Frame Control Word */
294 struct __rte_packed acc100_fcw_te {
311 uint8_t bypass_rv_idx0:1,
319 uint8_t code_block_mode:1,
324 /* FEC 5GNR Downlink Frame Control Word */
325 struct __rte_packed acc100_fcw_le {
326 uint32_t FCWversion:4,
349 /* ACC100 DMA Request Descriptor */
350 struct __rte_packed acc100_dma_req_desc {
359 uint32_t pass_param:8,
376 struct acc100_dma_triplet data_ptrs[ACC100_DMA_MAX_NUM_POINTERS];
378 /* Virtual addresses used to retrieve SW context info */
381 uint64_t pad1; /* pad to 64 bits */
384 * Stores additional information needed for driver processing:
385 * - last_desc_in_batch - flag used to mark last descriptor (CB)
387 * - cbs_in_tb - stores information about total number of Code Blocks
388 * in currently processed Transport Block
393 struct acc100_fcw_ld fcw_ld;
394 struct acc100_fcw_td fcw_td;
395 struct acc100_fcw_le fcw_le;
396 struct acc100_fcw_te fcw_te;
397 uint32_t pad2[ACC100_FCW_PADDING];
399 uint32_t last_desc_in_batch :8,
403 uint64_t pad3[ACC100_DMA_DESC_PADDING]; /* pad to 64 bits */
407 /* ACC100 DMA Descriptor */
408 union acc100_dma_desc {
409 struct acc100_dma_req_desc req;
410 union acc100_dma_rsp_desc rsp;
415 /* Union describing Info Ring entry */
416 union acc100_harq_layout_data {
425 /* Union describing Info Ring entry */
426 union acc100_info_ring_data {
430 uint16_t detailed_info;
435 uint16_t reserved: 2;
446 struct acc100_registry_addr {
447 unsigned int dma_ring_dl5g_hi;
448 unsigned int dma_ring_dl5g_lo;
449 unsigned int dma_ring_ul5g_hi;
450 unsigned int dma_ring_ul5g_lo;
451 unsigned int dma_ring_dl4g_hi;
452 unsigned int dma_ring_dl4g_lo;
453 unsigned int dma_ring_ul4g_hi;
454 unsigned int dma_ring_ul4g_lo;
455 unsigned int ring_size;
456 unsigned int info_ring_hi;
457 unsigned int info_ring_lo;
458 unsigned int info_ring_en;
459 unsigned int info_ring_ptr;
460 unsigned int tail_ptrs_dl5g_hi;
461 unsigned int tail_ptrs_dl5g_lo;
462 unsigned int tail_ptrs_ul5g_hi;
463 unsigned int tail_ptrs_ul5g_lo;
464 unsigned int tail_ptrs_dl4g_hi;
465 unsigned int tail_ptrs_dl4g_lo;
466 unsigned int tail_ptrs_ul4g_hi;
467 unsigned int tail_ptrs_ul4g_lo;
468 unsigned int depth_log0_offset;
469 unsigned int depth_log1_offset;
470 unsigned int qman_group_func;
471 unsigned int ddr_range;
474 /* Structure holding registry addresses for PF */
475 static const struct acc100_registry_addr pf_reg_addr = {
476 .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
477 .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
478 .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
479 .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
480 .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
481 .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
482 .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
483 .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
484 .ring_size = HWPfQmgrRingSizeVf,
485 .info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
486 .info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
487 .info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
488 .info_ring_ptr = HWPfHiInfoRingPointerRegPf,
489 .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
490 .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
491 .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
492 .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
493 .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
494 .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
495 .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
496 .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
497 .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
498 .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
499 .qman_group_func = HWPfQmgrGrpFunction0,
500 .ddr_range = HWPfDmaVfDdrBaseRw,
503 /* Structure holding registry addresses for VF */
504 static const struct acc100_registry_addr vf_reg_addr = {
505 .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
506 .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
507 .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
508 .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
509 .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
510 .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
511 .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
512 .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
513 .ring_size = HWVfQmgrRingSizeVf,
514 .info_ring_hi = HWVfHiInfoRingBaseHiVf,
515 .info_ring_lo = HWVfHiInfoRingBaseLoVf,
516 .info_ring_en = HWVfHiInfoRingIntWrEnVf,
517 .info_ring_ptr = HWVfHiInfoRingPointerVf,
518 .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
519 .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
520 .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
521 .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
522 .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
523 .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
524 .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
525 .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
526 .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
527 .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
528 .qman_group_func = HWVfQmgrGrpFunction0Vf,
529 .ddr_range = HWVfDmaDdrBaseRangeRoVf,
532 /* Structure associated with each queue. */
533 struct __rte_cache_aligned acc100_queue {
534 union acc100_dma_desc *ring_addr; /* Virtual address of sw ring */
535 rte_iova_t ring_addr_iova; /* IOVA address of software ring */
536 uint32_t sw_ring_head; /* software ring head */
537 uint32_t sw_ring_tail; /* software ring tail */
538 /* software ring size (descriptors, not bytes) */
539 uint32_t sw_ring_depth;
540 /* mask used to wrap enqueued descriptors on the sw ring */
541 uint32_t sw_ring_wrap_mask;
542 /* MMIO register used to enqueue descriptors */
543 void *mmio_reg_enqueue;
544 uint8_t vf_id; /* VF ID (max = 63) */
545 uint8_t qgrp_id; /* Queue Group ID */
546 uint16_t aq_id; /* Atomic Queue ID */
547 uint16_t aq_depth; /* Depth of atomic queue */
548 uint32_t aq_enqueued; /* Count how many "batches" have been enqueued */
549 uint32_t aq_dequeued; /* Count how many "batches" have been dequeued */
550 uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */
551 struct rte_mempool *fcw_mempool; /* FCW mempool */
552 enum rte_bbdev_op_type op_type; /* Type of this Queue: TE or TD */
553 /* Internal Buffers for loopback input */
556 rte_iova_t lb_in_addr_iova;
557 rte_iova_t lb_out_addr_iova;
558 struct acc100_device *d;
561 /* Private data structure for each ACC100 device */
562 struct acc100_device {
563 void *mmio_base; /**< Base address of MMIO registers (BAR0) */
564 void *sw_rings_base; /* Base addr of un-aligned memory for sw rings */
565 void *sw_rings; /* 64MBs of 64MB aligned memory for sw rings */
566 rte_iova_t sw_rings_iova; /* IOVA address of sw_rings */
567 /* Virtual address of the info memory routed to the this function under
568 * operation, whether it is PF or VF.
569 * HW may DMA information data at this location asynchronously
571 union acc100_info_ring_data *info_ring;
573 union acc100_harq_layout_data *harq_layout;
574 /* Virtual Info Ring head */
575 uint16_t info_ring_head;
576 /* Number of bytes available for each queue in device, depending on
577 * how many queues are enabled with configure()
579 uint32_t sw_ring_size;
580 uint32_t ddr_size; /* Size in kB */
581 uint32_t *tail_ptrs; /* Base address of response tail pointer buffer */
582 rte_iova_t tail_ptr_iova; /* IOVA address of tail pointers */
583 /* Max number of entries available for each queue in device, depending
584 * on how many queues are enabled with configure()
586 uint32_t sw_ring_max_depth;
587 struct rte_acc100_conf acc100_conf; /* ACC100 Initial configuration */
588 /* Bitmap capturing which Queues have already been assigned */
589 uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
590 bool pf_device; /**< True if this is a PF ACC100 device */
591 bool configured; /**< True if this ACC100 device is configured */
595 * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to
596 * the callback function.
598 struct acc100_deq_intr_details {
602 #endif /* _RTE_ACC100_PMD_H_ */