1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
5 #ifndef _FPGA_5GNR_FEC_H_
6 #define _FPGA_5GNR_FEC_H_
11 /* Helper macro for logging */
12 #define rte_bbdev_log(level, fmt, ...) \
13 rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \
16 #ifdef RTE_LIBRTE_BBDEV_DEBUG
17 #define rte_bbdev_log_debug(fmt, ...) \
18 rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \
21 #define rte_bbdev_log_debug(fmt, ...)
24 /* FPGA 5GNR FEC driver names */
25 #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf
26 #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf
28 /* FPGA 5GNR FEC PCI vendor & device IDs */
29 #define FPGA_5GNR_FEC_VENDOR_ID (0x8086)
30 #define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)
31 #define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)
33 /* Align DMA descriptors to 256 bytes - cache-aligned */
34 #define FPGA_RING_DESC_ENTRY_LENGTH (8)
35 /* Ring size is in 256 bits (32 bytes) units */
36 #define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
37 /* Maximum size of queue */
38 #define FPGA_RING_MAX_SIZE (1024)
39 #define FPGA_FLR_TIMEOUT_UNIT (16.384)
41 #define FPGA_NUM_UL_QUEUES (32)
42 #define FPGA_NUM_DL_QUEUES (32)
43 #define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)
44 #define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)
46 #define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)
48 #define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)
49 #define FPGA_HARQ_RDY_TIMEOUT (10)
50 #define FPGA_TIMEOUT_CHECK_INTERVAL (5)
51 #define FPGA_DDR_OVERFLOW (0x10)
53 #define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
54 #define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
57 /* FPGA 5GNR FEC Register mapping on BAR0 */
59 FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */
60 FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */
61 FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
62 FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
63 FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
64 FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
65 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
66 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
67 FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */
68 FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */
69 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */
70 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */
71 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */
72 FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */
73 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */
74 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */
75 FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */
76 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */
77 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */
78 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48 /* len: 4B */
81 /* FPGA 5GNR FEC Ring Control Registers */
83 FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008,
84 FPGA_5GNR_FEC_RING_SIZE = 0x00000010,
85 FPGA_5GNR_FEC_RING_MISC = 0x00000014,
86 FPGA_5GNR_FEC_RING_ENABLE = 0x00000015,
87 FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,
88 FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018,
89 FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C
92 /* FPGA 5GNR FEC DESCRIPTOR ERROR */
94 DESC_ERR_NO_ERR = 0x0,
95 DESC_ERR_K_P_OUT_OF_RANGE = 0x1,
96 DESC_ERR_Z_C_NOT_LEGAL = 0x2,
97 DESC_ERR_DESC_OFFSET_ERR = 0x3,
98 DESC_ERR_DESC_READ_FAIL = 0x8,
99 DESC_ERR_DESC_READ_TIMEOUT = 0x9,
100 DESC_ERR_DESC_READ_TLP_POISONED = 0xA,
101 DESC_ERR_CB_READ_FAIL = 0xC,
102 DESC_ERR_CB_READ_TIMEOUT = 0xD,
103 DESC_ERR_CB_READ_TLP_POISONED = 0xE,
104 DESC_ERR_HBSTORE_ERR = 0xF
108 /* FPGA 5GNR FEC DMA Encoding Request Descriptor */
109 struct __rte_packed fpga_dma_enc_desc {
129 uint32_t out_addr_lw;
130 uint32_t out_addr_hi;
136 /* Virtual addresses used to retrieve SW context info */
138 /* Stores information about total number of Code Blocks
139 * in currently processed Transport Block
144 uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
145 (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
150 /* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */
151 struct __rte_packed fpga_dma_dec_desc {
163 uint32_t hbstroe_offset:22,
173 uint32_t harq_input_length:16,
174 rm_e:16;/*the inbound data byte length*/
175 uint32_t out_addr_lw;
176 uint32_t out_addr_hi;
182 /* Virtual addresses used to retrieve SW context info */
184 /* Stores information about total number of Code Blocks
185 * in currently processed Transport Block
190 uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
194 /* FPGA 5GNR DMA Descriptor */
195 union fpga_dma_desc {
196 struct fpga_dma_enc_desc enc_req;
197 struct fpga_dma_dec_desc dec_req;
200 /* FPGA 5GNR FEC Ring Control Register */
201 struct __rte_packed fpga_ring_ctrl_reg {
202 uint64_t ring_base_addr;
203 uint64_t ring_head_addr;
204 uint16_t ring_size:11;
206 union { /* Miscellaneous register */
208 uint8_t max_ul_dec:5,
213 uint8_t flush_queue_en;
215 uint16_t shadow_tail;
222 /* Private data structure for each FPGA FEC device */
223 struct fpga_5gnr_fec_device {
224 /** Base address of MMIO registers (BAR0) */
226 /** True if this is a PF FPGA FEC device */
230 #endif /* _FPGA_5GNR_FEC_H_ */