1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
7 #include <rte_common.h>
10 #include <rte_malloc.h>
11 #include <rte_mempool.h>
12 #include <rte_errno.h>
14 #include <rte_bus_pci.h>
15 #include <rte_byteorder.h>
16 #ifdef RTE_BBDEV_OFFLOAD_COST
17 #include <rte_cycles.h>
20 #include <rte_bbdev.h>
21 #include <rte_bbdev_pmd.h>
23 #include "fpga_5gnr_fec.h"
24 #include "rte_pmd_fpga_5gnr_fec.h"
26 /* 5GNR SW PMD logging ID */
27 static int fpga_5gnr_fec_logtype;
29 #ifdef RTE_LIBRTE_BBDEV_DEBUG
31 /* Read Ring Control Register of FPGA 5GNR FEC device */
33 print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
36 "FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
37 PRIx32, mmio_base, offset);
39 "RING_BASE_ADDR = 0x%016"PRIx64,
40 fpga_reg_read_64(mmio_base, offset));
42 "RING_HEAD_ADDR = 0x%016"PRIx64,
43 fpga_reg_read_64(mmio_base, offset +
44 FPGA_5GNR_FEC_RING_HEAD_ADDR));
46 "RING_SIZE = 0x%04"PRIx16,
47 fpga_reg_read_16(mmio_base, offset +
48 FPGA_5GNR_FEC_RING_SIZE));
50 "RING_MISC = 0x%02"PRIx8,
51 fpga_reg_read_8(mmio_base, offset +
52 FPGA_5GNR_FEC_RING_MISC));
54 "RING_ENABLE = 0x%02"PRIx8,
55 fpga_reg_read_8(mmio_base, offset +
56 FPGA_5GNR_FEC_RING_ENABLE));
58 "RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
59 fpga_reg_read_8(mmio_base, offset +
60 FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));
62 "RING_SHADOW_TAIL = 0x%04"PRIx16,
63 fpga_reg_read_16(mmio_base, offset +
64 FPGA_5GNR_FEC_RING_SHADOW_TAIL));
66 "RING_HEAD_POINT = 0x%04"PRIx16,
67 fpga_reg_read_16(mmio_base, offset +
68 FPGA_5GNR_FEC_RING_HEAD_POINT));
71 /* Read Static Register of FPGA 5GNR FEC device */
73 print_static_reg_debug_info(void *mmio_base)
75 uint16_t config = fpga_reg_read_16(mmio_base,
76 FPGA_5GNR_FEC_CONFIGURATION);
77 uint8_t qmap_done = fpga_reg_read_8(mmio_base,
78 FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
79 uint16_t lb_factor = fpga_reg_read_16(mmio_base,
80 FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
81 uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
82 FPGA_5GNR_FEC_RING_DESC_LEN);
83 uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
84 FPGA_5GNR_FEC_FLR_TIME_OUT);
86 rte_bbdev_log_debug("UL.DL Weights = %u.%u",
87 ((uint8_t)config), ((uint8_t)(config >> 8)));
88 rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
89 ((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
90 rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
91 (qmap_done > 0) ? "READY" : "NOT-READY");
92 rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
93 ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
94 rte_bbdev_log_debug("FLR Timeout = %f usec",
95 (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
98 /* Print decode DMA Descriptor of FPGA 5GNR Decoder device */
100 print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
102 rte_bbdev_log_debug("DMA response desc %p\n"
103 "\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")"
104 " | crcb_pass (%"PRIu32") | error(%"PRIu32")\n"
105 "\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | "
106 "bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n"
107 "\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") "
108 "| irq_en(%"PRIu32")\n"
109 "\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | "
110 "drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n"
111 "\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n"
112 "\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n"
113 "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")"
114 "| out_add (0x%08"PRIx32"%08"PRIx32")",
116 (uint32_t)desc->dec_req.done,
117 (uint32_t)desc->dec_req.iter,
118 (uint32_t)desc->dec_req.et_pass,
119 (uint32_t)desc->dec_req.crcb_pass,
120 (uint32_t)desc->dec_req.error,
121 (uint32_t)desc->dec_req.qm_idx,
122 (uint32_t)desc->dec_req.max_iter,
123 (uint32_t)desc->dec_req.bg_idx,
124 (uint32_t)desc->dec_req.harqin_en,
125 (uint32_t)desc->dec_req.zc,
126 (uint32_t)desc->dec_req.hbstroe_offset,
127 (uint32_t)desc->dec_req.num_null,
128 (uint32_t)desc->dec_req.irq_en,
129 (uint32_t)desc->dec_req.ncb,
130 (uint32_t)desc->dec_req.desc_idx,
131 (uint32_t)desc->dec_req.drop_crc24b,
132 (uint32_t)desc->dec_req.rv,
133 (uint32_t)desc->dec_req.crc24b_ind,
134 (uint32_t)desc->dec_req.et_dis,
135 (uint32_t)desc->dec_req.harq_input_length,
136 (uint32_t)desc->dec_req.rm_e,
137 (uint32_t)desc->dec_req.cbs_in_op,
138 (uint32_t)desc->dec_req.in_addr_hi,
139 (uint32_t)desc->dec_req.in_addr_lw,
140 (uint32_t)desc->dec_req.out_addr_hi,
141 (uint32_t)desc->dec_req.out_addr_lw);
142 uint32_t *word = (uint32_t *) desc;
143 rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
144 "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
145 word[0], word[1], word[2], word[3],
146 word[4], word[5], word[6], word[7]);
149 /* Print decode DMA Descriptor of FPGA 5GNR encoder device */
151 print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)
153 rte_bbdev_log_debug("DMA response desc %p\n"
154 "%"PRIu32" %"PRIu32"\n"
155 "K' %"PRIu32" E %"PRIu32" desc %"PRIu32" Z %"PRIu32"\n"
156 "BG %"PRIu32" Qm %"PRIu32" CRC %"PRIu32" IRQ %"PRIu32"\n"
157 "k0 %"PRIu32" Ncb %"PRIu32" F %"PRIu32"\n",
159 (uint32_t)desc->enc_req.done,
160 (uint32_t)desc->enc_req.error,
162 (uint32_t)desc->enc_req.k_,
163 (uint32_t)desc->enc_req.rm_e,
164 (uint32_t)desc->enc_req.desc_idx,
165 (uint32_t)desc->enc_req.zc,
167 (uint32_t)desc->enc_req.bg_idx,
168 (uint32_t)desc->enc_req.qm_idx,
169 (uint32_t)desc->enc_req.crc_en,
170 (uint32_t)desc->enc_req.irq_en,
172 (uint32_t)desc->enc_req.k0,
173 (uint32_t)desc->enc_req.ncb,
174 (uint32_t)desc->enc_req.num_null);
175 uint32_t *word = (uint32_t *) desc;
176 rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
177 "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
178 word[0], word[1], word[2], word[3],
179 word[4], word[5], word[6], word[7]);
185 fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
187 /* Number of queues bound to a PF/VF */
188 uint32_t hw_q_num = 0;
189 uint32_t ring_size, payload, address, q_id, offset;
190 rte_iova_t phys_addr;
191 struct fpga_ring_ctrl_reg ring_reg;
192 struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
194 address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;
195 if (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) {
197 "Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?",
202 /* Clear queue registers structure */
203 memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
206 * If a queue is valid and mapped to a calling PF/VF the read value is
207 * replaced with a queue ID and if it's not then
208 * FPGA_INVALID_HW_QUEUE_ID is returned.
210 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
211 uint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base,
212 FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));
214 rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u",
215 dev->device->name, q_id, hw_q_id);
217 if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) {
218 fpga_dev->q_bound_bit_map |= (1ULL << q_id);
219 /* Clear queue register of found queue */
220 offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
221 (sizeof(struct fpga_ring_ctrl_reg) * q_id);
222 fpga_ring_reg_write(fpga_dev->mmio_base,
229 "No HW queues assigned to this device. Probably this is a VF configured for PF mode. Check device configuration!");
233 if (num_queues > hw_q_num) {
235 "Not enough queues for device %s! Requested: %u, available: %u",
236 dev->device->name, num_queues, hw_q_num);
240 ring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);
242 /* Enforce 32 byte alignment */
243 RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);
245 /* Allocate memory for SW descriptor rings */
246 fpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name,
247 num_queues * ring_size, RTE_CACHE_LINE_SIZE,
249 if (fpga_dev->sw_rings == NULL) {
251 "Failed to allocate memory for %s:%u sw_rings",
252 dev->device->driver->name, dev->data->dev_id);
256 fpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings);
257 fpga_dev->sw_ring_size = ring_size;
258 fpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE;
260 /* Allocate memory for ring flush status */
261 fpga_dev->flush_queue_status = rte_zmalloc_socket(NULL,
262 sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);
263 if (fpga_dev->flush_queue_status == NULL) {
265 "Failed to allocate memory for %s:%u flush_queue_status",
266 dev->device->driver->name, dev->data->dev_id);
270 /* Set the flush status address registers */
271 phys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status);
273 address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW;
274 payload = (uint32_t)(phys_addr);
275 fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
277 address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI;
278 payload = (uint32_t)(phys_addr >> 32);
279 fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
285 fpga_dev_close(struct rte_bbdev *dev)
287 struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
289 rte_free(fpga_dev->sw_rings);
290 rte_free(fpga_dev->flush_queue_status);
296 fpga_dev_info_get(struct rte_bbdev *dev,
297 struct rte_bbdev_driver_info *dev_info)
299 struct fpga_5gnr_fec_device *d = dev->data->dev_private;
302 static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
304 .type = RTE_BBDEV_OP_LDPC_ENC,
307 RTE_BBDEV_LDPC_RATE_MATCH |
308 RTE_BBDEV_LDPC_ENC_INTERRUPTS |
309 RTE_BBDEV_LDPC_CRC_24B_ATTACH,
311 RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
313 RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
317 .type = RTE_BBDEV_OP_LDPC_DEC,
320 RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |
321 RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP |
322 RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |
323 RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
324 RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE |
325 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE |
326 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE |
327 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK |
328 RTE_BBDEV_LDPC_DEC_INTERRUPTS |
329 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS,
333 RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
334 .num_buffers_hard_out =
335 RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
336 .num_buffers_soft_out = 0,
339 RTE_BBDEV_END_OF_CAPABILITIES_LIST()
342 /* Check the HARQ DDR size available */
343 uint8_t timeout_counter = 0;
344 uint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base,
345 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);
346 while (harq_buf_ready != 1) {
347 usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
349 harq_buf_ready = fpga_reg_read_32(d->mmio_base,
350 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);
351 if (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) {
352 rte_bbdev_log(ERR, "HARQ Buffer not ready %d",
357 uint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base,
358 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
360 static struct rte_bbdev_queue_conf default_queue_conf;
361 default_queue_conf.socket = dev->data->socket_id;
362 default_queue_conf.queue_size = FPGA_RING_MAX_SIZE;
364 dev_info->driver_name = dev->device->driver->name;
365 dev_info->queue_size_lim = FPGA_RING_MAX_SIZE;
366 dev_info->hardware_accelerated = true;
367 dev_info->min_alignment = 64;
368 dev_info->harq_buffer_size = (harq_buf_size >> 10) + 1;
369 dev_info->default_queue_conf = default_queue_conf;
370 dev_info->capabilities = bbdev_capabilities;
371 dev_info->cpu_flag_reqs = NULL;
373 /* Calculates number of queues assigned to device */
374 dev_info->max_num_queues = 0;
375 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
376 uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,
377 FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));
378 if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)
379 dev_info->max_num_queues++;
384 * Find index of queue bound to current PF/VF which is unassigned. Return -1
385 * when there is no available queue
388 fpga_find_free_queue_idx(struct rte_bbdev *dev,
389 const struct rte_bbdev_queue_conf *conf)
391 struct fpga_5gnr_fec_device *d = dev->data->dev_private;
394 uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1;
396 if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) {
397 i = FPGA_NUM_DL_QUEUES;
398 range = FPGA_TOTAL_NUM_QUEUES;
401 for (; i < range; ++i) {
403 /* Check if index of queue is bound to current PF/VF */
404 if (d->q_bound_bit_map & q_idx)
405 /* Check if found queue was not already assigned */
406 if (!(d->q_assigned_bit_map & q_idx)) {
407 d->q_assigned_bit_map |= q_idx;
412 rte_bbdev_log(INFO, "Failed to find free queue on %s", dev->data->name);
418 fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
419 const struct rte_bbdev_queue_conf *conf)
421 uint32_t address, ring_offset;
422 struct fpga_5gnr_fec_device *d = dev->data->dev_private;
423 struct fpga_queue *q;
426 /* Check if there is a free queue to assign */
427 q_idx = fpga_find_free_queue_idx(dev, conf);
431 /* Allocate the queue data structure. */
432 q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
433 RTE_CACHE_LINE_SIZE, conf->socket);
435 /* Mark queue as un-assigned */
436 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
437 rte_bbdev_log(ERR, "Failed to allocate queue memory");
444 /* Set ring_base_addr */
445 q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
446 q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys +
447 (d->sw_ring_size * queue_id);
449 /* Allocate memory for Completion Head variable*/
450 q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,
451 sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket);
452 if (q->ring_head_addr == NULL) {
453 /* Mark queue as un-assigned */
454 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
457 "Failed to allocate memory for %s:%u completion_head",
458 dev->device->driver->name, dev->data->dev_id);
461 /* Set ring_head_addr */
462 q->ring_ctrl_reg.ring_head_addr =
463 rte_malloc_virt2iova(q->ring_head_addr);
465 /* Clear shadow_completion_head */
466 q->shadow_completion_head = 0;
469 if (conf->queue_size > FPGA_RING_MAX_SIZE) {
470 /* Mark queue as un-assigned */
471 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
472 rte_free(q->ring_head_addr);
475 "Size of queue is too big %d (MAX: %d ) for %s:%u",
476 conf->queue_size, FPGA_RING_MAX_SIZE,
477 dev->device->driver->name, dev->data->dev_id);
480 q->ring_ctrl_reg.ring_size = conf->queue_size;
482 /* Set Miscellaneous FPGA register*/
483 /* Max iteration number for TTI mitigation - todo */
484 q->ring_ctrl_reg.max_ul_dec = 0;
485 /* Enable max iteration number for TTI - todo */
486 q->ring_ctrl_reg.max_ul_dec_en = 0;
488 /* Enable the ring */
489 q->ring_ctrl_reg.enable = 1;
491 /* Set FPGA head_point and tail registers */
492 q->ring_ctrl_reg.head_point = q->tail = 0;
494 /* Set FPGA shadow_tail register */
495 q->ring_ctrl_reg.shadow_tail = q->tail;
497 /* Calculates the ring offset for found queue */
498 ring_offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
499 (sizeof(struct fpga_ring_ctrl_reg) * q_idx);
501 /* Set FPGA Ring Control Registers */
502 fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);
504 /* Store MMIO register of shadow_tail */
505 address = ring_offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL;
506 q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address);
508 q->head_free_desc = q->tail;
511 q->sw_ring_wrap_mask = conf->queue_size - 1;
513 rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u",
514 dev->data->dev_id, queue_id, q->q_idx);
516 dev->data->queues[queue_id].queue_private = q;
518 rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]",
521 #ifdef RTE_LIBRTE_BBDEV_DEBUG
522 /* Read FPGA Ring Control Registers after configuration*/
523 print_ring_reg_debug_info(d->mmio_base, ring_offset);
529 fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)
531 struct fpga_5gnr_fec_device *d = dev->data->dev_private;
532 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
533 struct fpga_ring_ctrl_reg ring_reg;
536 rte_bbdev_log_debug("FPGA Queue[%d] released", queue_id);
539 memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
540 offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
541 (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
543 fpga_reg_write_8(d->mmio_base,
544 offset + FPGA_5GNR_FEC_RING_ENABLE, 0x00);
545 /* Clear queue registers */
546 fpga_ring_reg_write(d->mmio_base, offset, ring_reg);
548 /* Mark the Queue as un-assigned */
549 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx));
550 rte_free(q->ring_head_addr);
552 dev->data->queues[queue_id].queue_private = NULL;
558 /* Function starts a device queue. */
560 fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)
562 struct fpga_5gnr_fec_device *d = dev->data->dev_private;
563 #ifdef RTE_LIBRTE_BBDEV_DEBUG
565 rte_bbdev_log(ERR, "Invalid device pointer");
569 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
570 uint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
571 (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
572 uint8_t enable = 0x01;
573 uint16_t zero = 0x0000;
575 /* Clear queue head and tail variables */
576 q->tail = q->head_free_desc = 0;
578 /* Clear FPGA head_point and tail registers */
579 fpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
581 fpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
585 fpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
588 rte_bbdev_log_debug("FPGA Queue[%d] started", queue_id);
592 /* Function stops a device queue. */
594 fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)
596 struct fpga_5gnr_fec_device *d = dev->data->dev_private;
597 #ifdef RTE_LIBRTE_BBDEV_DEBUG
599 rte_bbdev_log(ERR, "Invalid device pointer");
603 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
604 uint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
605 (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
606 uint8_t payload = 0x01;
608 uint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US /
609 FPGA_TIMEOUT_CHECK_INTERVAL;
611 /* Set flush_queue_en bit to trigger queue flushing */
612 fpga_reg_write_8(d->mmio_base,
613 offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, payload);
615 /** Check if queue flush is completed.
616 * FPGA will update the completion flag after queue flushing is
617 * completed. If completion flag is not updated within 1ms it is
618 * considered as a failure.
620 while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx)
622 if (counter > timeout) {
623 rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
627 usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
633 fpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
636 rte_bbdev_log_debug("FPGA Queue[%d] stopped", queue_id);
640 static inline uint16_t
641 get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)
645 for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
646 struct fpga_queue *q = data->queues[queue_id].queue_private;
647 if (q != NULL && q->q_idx == q_idx)
654 /* Interrupt handler triggered by FPGA dev for handling specific interrupt */
656 fpga_dev_interrupt_handler(void *cb_arg)
658 struct rte_bbdev *dev = cb_arg;
659 struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
660 struct fpga_queue *q;
666 /* Scan queue assigned to this device */
667 for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {
669 if (fpga_dev->q_bound_bit_map & q_idx) {
670 queue_id = get_queue_id(dev->data, i);
671 if (queue_id == (uint16_t) -1)
674 /* Check if completion head was changed */
675 q = dev->data->queues[queue_id].queue_private;
676 ring_head = *q->ring_head_addr;
677 if (q->shadow_completion_head != ring_head &&
678 q->irq_enable == 1) {
679 q->shadow_completion_head = ring_head;
680 rte_bbdev_pmd_callback_process(
682 RTE_BBDEV_EVENT_DEQUEUE,
690 fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)
692 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
694 if (!rte_intr_cap_multiple(dev->intr_handle))
703 fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)
705 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
712 fpga_intr_enable(struct rte_bbdev *dev)
717 if (!rte_intr_cap_multiple(dev->intr_handle)) {
718 rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)",
723 /* Create event file descriptors for each of 64 queue. Event fds will be
724 * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where
725 * the IRQ number is a direct translation to the queue number.
727 * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()
728 * mapped the first IRQ to already created interrupt event file
729 * descriptor (intr_handle->fd).
731 if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {
732 rte_bbdev_log(ERR, "Failed to create fds for %u queues",
733 dev->data->num_queues);
737 /* TODO Each event file descriptor is overwritten by interrupt event
738 * file descriptor. That descriptor is added to epoll observed list.
739 * It ensures that callback function assigned to that descriptor will
740 * invoked when any FPGA queue issues interrupt.
742 for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
743 dev->intr_handle->efds[i] = dev->intr_handle->fd;
745 if (!dev->intr_handle->intr_vec) {
746 dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
747 dev->data->num_queues * sizeof(int), 0);
748 if (!dev->intr_handle->intr_vec) {
749 rte_bbdev_log(ERR, "Failed to allocate %u vectors",
750 dev->data->num_queues);
755 ret = rte_intr_enable(dev->intr_handle);
758 "Couldn't enable interrupts for device: %s",
763 ret = rte_intr_callback_register(dev->intr_handle,
764 fpga_dev_interrupt_handler, dev);
767 "Couldn't register interrupt callback for device: %s",
775 static const struct rte_bbdev_ops fpga_ops = {
776 .setup_queues = fpga_setup_queues,
777 .intr_enable = fpga_intr_enable,
778 .close = fpga_dev_close,
779 .info_get = fpga_dev_info_get,
780 .queue_setup = fpga_queue_setup,
781 .queue_stop = fpga_queue_stop,
782 .queue_start = fpga_queue_start,
783 .queue_release = fpga_queue_release,
784 .queue_intr_enable = fpga_queue_intr_enable,
785 .queue_intr_disable = fpga_queue_intr_disable
789 fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
790 struct rte_bbdev_stats *queue_stats)
792 #ifdef RTE_BBDEV_OFFLOAD_COST
793 uint64_t start_time = 0;
794 queue_stats->acc_offload_cycles = 0;
796 RTE_SET_USED(queue_stats);
799 /* Update tail and shadow_tail register */
800 q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;
804 #ifdef RTE_BBDEV_OFFLOAD_COST
805 /* Start time measurement for enqueue function offload. */
806 start_time = rte_rdtsc_precise();
808 mmio_write_16(q->shadow_tail_addr, q->tail);
810 #ifdef RTE_BBDEV_OFFLOAD_COST
812 queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;
816 /* Read flag value 0/1/ from bitmap */
818 check_bit(uint32_t bitmap, uint32_t bitmask)
820 return bitmap & bitmask;
823 /* Print an error if a descriptor error has occurred.
824 * Return 0 on success, 1 on failure
827 check_desc_error(uint32_t error_code) {
828 switch (error_code) {
829 case DESC_ERR_NO_ERR:
831 case DESC_ERR_K_P_OUT_OF_RANGE:
832 rte_bbdev_log(ERR, "Encode block size K' is out of range");
834 case DESC_ERR_Z_C_NOT_LEGAL:
835 rte_bbdev_log(ERR, "Zc is illegal");
837 case DESC_ERR_DESC_OFFSET_ERR:
839 "Queue offset does not meet the expectation in the FPGA"
842 case DESC_ERR_DESC_READ_FAIL:
843 rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read");
845 case DESC_ERR_DESC_READ_TIMEOUT:
846 rte_bbdev_log(ERR, "Descriptor read time-out");
848 case DESC_ERR_DESC_READ_TLP_POISONED:
849 rte_bbdev_log(ERR, "Descriptor read TLP poisoned");
851 case DESC_ERR_CB_READ_FAIL:
852 rte_bbdev_log(ERR, "Unsuccessful completion for code block");
854 case DESC_ERR_CB_READ_TIMEOUT:
855 rte_bbdev_log(ERR, "Code block read time-out");
857 case DESC_ERR_CB_READ_TLP_POISONED:
858 rte_bbdev_log(ERR, "Code block read TLP poisoned");
860 case DESC_ERR_HBSTORE_ERR:
861 rte_bbdev_log(ERR, "Hbstroe exceeds HARQ buffer size.");
864 rte_bbdev_log(ERR, "Descriptor error unknown error code %u",
871 /* Compute value of k0.
872 * Based on 3GPP 38.212 Table 5.4.2.1-2
873 * Starting position of different redundancy versions, k0
875 static inline uint16_t
876 get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)
880 uint16_t n = (bg == 1 ? N_ZC_1 : N_ZC_2) * z_c;
883 return (bg == 1 ? K0_1_1 : K0_1_2) * z_c;
884 else if (rv_index == 2)
885 return (bg == 1 ? K0_2_1 : K0_2_2) * z_c;
887 return (bg == 1 ? K0_3_1 : K0_3_2) * z_c;
889 /* LBRM case - includes a division by N */
891 return (((bg == 1 ? K0_1_1 : K0_1_2) * n_cb)
893 else if (rv_index == 2)
894 return (((bg == 1 ? K0_2_1 : K0_2_2) * n_cb)
897 return (((bg == 1 ? K0_3_1 : K0_3_2) * n_cb)
902 * Set DMA descriptor for encode operation (1 Code Block)
905 * Pointer to a single encode operation.
907 * Pointer to DMA descriptor.
909 * Pointer to pointer to input data which will be decoded.
911 * E value (length of output in bits).
913 * Ncb value (size of the soft buffer).
915 * Length of output buffer
917 * Input offset in rte_mbuf structure. It is used for calculating the point
918 * where data is starting.
920 * Output offset in rte_mbuf structure. It is used for calculating the point
921 * where hard output data will be stored.
923 * Number of CBs contained in one operation.
926 fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,
927 struct fpga_dma_enc_desc *desc, struct rte_mbuf *input,
928 struct rte_mbuf *output, uint16_t k_, uint16_t e,
929 uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
937 desc->desc_idx = desc_offset;
938 desc->zc = op->ldpc_enc.z_c;
939 desc->bg_idx = op->ldpc_enc.basegraph - 1;
940 desc->qm_idx = op->ldpc_enc.q_m / 2;
941 desc->crc_en = check_bit(op->ldpc_enc.op_flags,
942 RTE_BBDEV_LDPC_CRC_24B_ATTACH);
944 desc->k0 = get_k0(op->ldpc_enc.n_cb, op->ldpc_enc.z_c,
945 op->ldpc_enc.basegraph, op->ldpc_enc.rv_index);
946 desc->ncb = op->ldpc_enc.n_cb;
947 desc->num_null = op->ldpc_enc.n_filler;
948 /* Set inbound data buffer address */
949 desc->in_addr_hi = (uint32_t)(
950 rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
951 desc->in_addr_lw = (uint32_t)(
952 rte_pktmbuf_mtophys_offset(input, in_offset));
954 desc->out_addr_hi = (uint32_t)(
955 rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
956 desc->out_addr_lw = (uint32_t)(
957 rte_pktmbuf_mtophys_offset(output, out_offset));
958 /* Save software context needed for dequeue */
960 /* Set total number of CBs in an op */
961 desc->cbs_in_op = cbs_in_op;
966 * Set DMA descriptor for decode operation (1 Code Block)
969 * Pointer to a single encode operation.
971 * Pointer to DMA descriptor.
973 * Pointer to pointer to input data which will be decoded.
975 * Input offset in rte_mbuf structure. It is used for calculating the point
976 * where data is starting.
978 * Output offset in rte_mbuf structure. It is used for calculating the point
979 * where hard output data will be stored.
981 * Number of CBs contained in one operation.
984 fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
985 struct fpga_dma_dec_desc *desc,
986 struct rte_mbuf *input, struct rte_mbuf *output,
987 uint16_t harq_in_length,
988 uint32_t in_offset, uint32_t out_offset,
989 uint32_t harq_offset,
990 uint16_t desc_offset,
996 /* Set inbound data buffer address */
997 desc->in_addr_hi = (uint32_t)(
998 rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
999 desc->in_addr_lw = (uint32_t)(
1000 rte_pktmbuf_mtophys_offset(input, in_offset));
1001 desc->rm_e = op->ldpc_dec.cb_params.e;
1002 desc->harq_input_length = harq_in_length;
1003 desc->et_dis = !check_bit(op->ldpc_dec.op_flags,
1004 RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
1005 desc->rv = op->ldpc_dec.rv_index;
1006 desc->crc24b_ind = check_bit(op->ldpc_dec.op_flags,
1007 RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
1008 desc->drop_crc24b = check_bit(op->ldpc_dec.op_flags,
1009 RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP);
1010 desc->desc_idx = desc_offset;
1011 desc->ncb = op->ldpc_dec.n_cb;
1012 desc->num_null = op->ldpc_dec.n_filler;
1013 desc->hbstroe_offset = harq_offset >> 10;
1014 desc->zc = op->ldpc_dec.z_c;
1015 desc->harqin_en = check_bit(op->ldpc_dec.op_flags,
1016 RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
1017 desc->bg_idx = op->ldpc_dec.basegraph - 1;
1018 desc->max_iter = op->ldpc_dec.iter_max;
1019 desc->qm_idx = op->ldpc_dec.q_m / 2;
1020 desc->out_addr_hi = (uint32_t)(
1021 rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
1022 desc->out_addr_lw = (uint32_t)(
1023 rte_pktmbuf_mtophys_offset(output, out_offset));
1024 /* Save software context needed for dequeue */
1026 /* Set total number of CBs in an op */
1027 desc->cbs_in_op = cbs_in_op;
1032 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1033 /* Validates LDPC encoder parameters */
1035 validate_enc_op(struct rte_bbdev_enc_op *op __rte_unused)
1037 struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
1038 struct rte_bbdev_op_enc_ldpc_cb_params *cb = NULL;
1039 struct rte_bbdev_op_enc_ldpc_tb_params *tb = NULL;
1042 if (ldpc_enc->input.length >
1043 RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) {
1044 rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d",
1045 ldpc_enc->input.length,
1046 RTE_BBDEV_LDPC_MAX_CB_SIZE);
1050 if (op->mempool == NULL) {
1051 rte_bbdev_log(ERR, "Invalid mempool pointer");
1054 if (ldpc_enc->input.data == NULL) {
1055 rte_bbdev_log(ERR, "Invalid input pointer");
1058 if (ldpc_enc->output.data == NULL) {
1059 rte_bbdev_log(ERR, "Invalid output pointer");
1062 if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) {
1064 "basegraph (%u) is out of range 1 <= value <= 2",
1065 ldpc_enc->basegraph);
1068 if (ldpc_enc->code_block_mode > 1) {
1070 "code_block_mode (%u) is out of range 0:Tb 1:CB",
1071 ldpc_enc->code_block_mode);
1075 if (ldpc_enc->code_block_mode == 0) {
1076 tb = &ldpc_enc->tb_params;
1079 "c (%u) is out of range 1 <= value <= %u",
1080 tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
1083 if (tb->cab > tb->c) {
1085 "cab (%u) is greater than c (%u)",
1089 if ((tb->ea < RTE_BBDEV_LDPC_MIN_CB_SIZE)
1090 && tb->r < tb->cab) {
1092 "ea (%u) is less than %u or it is not even",
1093 tb->ea, RTE_BBDEV_LDPC_MIN_CB_SIZE);
1096 if ((tb->eb < RTE_BBDEV_LDPC_MIN_CB_SIZE)
1097 && tb->c > tb->cab) {
1099 "eb (%u) is less than %u",
1100 tb->eb, RTE_BBDEV_LDPC_MIN_CB_SIZE);
1103 if (tb->r > (tb->c - 1)) {
1105 "r (%u) is greater than c - 1 (%u)",
1110 cb = &ldpc_enc->cb_params;
1111 if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
1113 "e (%u) is less than %u or it is not even",
1114 cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE);
1122 static inline char *
1123 mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
1125 if (unlikely(len > rte_pktmbuf_tailroom(m)))
1128 char *tail = (char *)m->buf_addr + m->data_off + m->data_len;
1129 m->data_len = (uint16_t)(m->data_len + len);
1130 m_head->pkt_len = (m_head->pkt_len + len);
1134 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1135 /* Validates LDPC decoder parameters */
1137 validate_dec_op(struct rte_bbdev_dec_op *op __rte_unused)
1139 struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
1140 struct rte_bbdev_op_dec_ldpc_cb_params *cb = NULL;
1141 struct rte_bbdev_op_dec_ldpc_tb_params *tb = NULL;
1143 if (op->mempool == NULL) {
1144 rte_bbdev_log(ERR, "Invalid mempool pointer");
1147 if (ldpc_dec->rv_index > 3) {
1149 "rv_index (%u) is out of range 0 <= value <= 3",
1150 ldpc_dec->rv_index);
1154 if (ldpc_dec->iter_max == 0) {
1156 "iter_max (%u) is equal to 0",
1157 ldpc_dec->iter_max);
1161 if (ldpc_dec->code_block_mode > 1) {
1163 "code_block_mode (%u) is out of range 0 <= value <= 1",
1164 ldpc_dec->code_block_mode);
1168 if (ldpc_dec->code_block_mode == 0) {
1169 tb = &ldpc_dec->tb_params;
1172 "c (%u) is out of range 1 <= value <= %u",
1173 tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
1176 if (tb->cab > tb->c) {
1178 "cab (%u) is greater than c (%u)",
1183 cb = &ldpc_dec->cb_params;
1184 if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
1186 "e (%u) is out of range %u <= value <= %u",
1187 cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE,
1188 RTE_BBDEV_LDPC_MAX_CB_SIZE);
1198 fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev,
1199 struct rte_mbuf *harq_input, uint16_t harq_in_length,
1200 uint32_t harq_in_offset, uint32_t harq_out_offset)
1202 uint32_t out_offset = harq_out_offset;
1203 uint32_t in_offset = harq_in_offset;
1204 uint32_t left_length = harq_in_length;
1205 uint32_t reg_32, increment = 0;
1206 uint64_t *input = NULL;
1207 uint32_t last_transaction = left_length
1208 % FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
1211 if (last_transaction > 0)
1212 left_length -= last_transaction;
1215 * Get HARQ buffer size for each VF/PF: When 0x00, there is no
1216 * available DDR space for the corresponding VF/PF.
1218 reg_32 = fpga_reg_read_32(fpga_dev->mmio_base,
1219 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
1220 if (reg_32 < harq_in_length) {
1221 left_length = reg_32;
1222 rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
1225 input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input,
1226 uint8_t *, in_offset);
1228 while (left_length > 0) {
1229 if (fpga_reg_read_8(fpga_dev->mmio_base,
1230 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) {
1231 fpga_reg_write_32(fpga_dev->mmio_base,
1232 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
1234 fpga_reg_write_64(fpga_dev->mmio_base,
1235 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
1237 left_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
1238 out_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
1240 fpga_reg_write_8(fpga_dev->mmio_base,
1241 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
1244 while (last_transaction > 0) {
1245 if (fpga_reg_read_8(fpga_dev->mmio_base,
1246 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) {
1247 fpga_reg_write_32(fpga_dev->mmio_base,
1248 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
1250 last_word = input[increment];
1251 last_word &= (uint64_t)(1 << (last_transaction * 4))
1253 fpga_reg_write_64(fpga_dev->mmio_base,
1254 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
1256 fpga_reg_write_8(fpga_dev->mmio_base,
1257 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
1258 last_transaction = 0;
1265 fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev,
1266 struct rte_mbuf *harq_output, uint16_t harq_in_length,
1267 uint32_t harq_in_offset, uint32_t harq_out_offset)
1269 uint32_t left_length, in_offset = harq_in_offset;
1271 uint32_t increment = 0;
1272 uint64_t *input = NULL;
1273 uint32_t last_transaction = harq_in_length
1274 % FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
1276 if (last_transaction > 0)
1277 harq_in_length += (8 - last_transaction);
1279 reg = fpga_reg_read_32(fpga_dev->mmio_base,
1280 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
1281 if (reg < harq_in_length) {
1282 harq_in_length = reg;
1283 rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
1286 if (!mbuf_append(harq_output, harq_output, harq_in_length)) {
1287 rte_bbdev_log(ERR, "HARQ output buffer warning %d %d\n",
1288 harq_output->buf_len -
1289 rte_pktmbuf_headroom(harq_output),
1291 harq_in_length = harq_output->buf_len -
1292 rte_pktmbuf_headroom(harq_output);
1293 if (!mbuf_append(harq_output, harq_output, harq_in_length)) {
1294 rte_bbdev_log(ERR, "HARQ output buffer issue %d %d\n",
1295 harq_output->buf_len, harq_in_length);
1299 left_length = harq_in_length;
1301 input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output,
1302 uint8_t *, harq_out_offset);
1304 while (left_length > 0) {
1305 fpga_reg_write_32(fpga_dev->mmio_base,
1306 FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset);
1307 fpga_reg_write_8(fpga_dev->mmio_base,
1308 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1);
1309 reg = fpga_reg_read_8(fpga_dev->mmio_base,
1310 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);
1312 reg = fpga_reg_read_8(fpga_dev->mmio_base,
1313 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);
1314 if (reg == FPGA_DDR_OVERFLOW) {
1316 "Read address is overflow!\n");
1320 input[increment] = fpga_reg_read_64(fpga_dev->mmio_base,
1321 FPGA_5GNR_FEC_DDR4_RD_DATA_REGS);
1322 left_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES;
1323 in_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
1325 fpga_reg_write_8(fpga_dev->mmio_base,
1326 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0);
1332 enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
1333 uint16_t desc_offset)
1335 union fpga_dma_desc *desc;
1337 uint8_t c, crc24_bits = 0;
1338 struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;
1339 uint16_t in_offset = enc->input.offset;
1340 uint16_t out_offset = enc->output.offset;
1341 struct rte_mbuf *m_in = enc->input.data;
1342 struct rte_mbuf *m_out = enc->output.data;
1343 struct rte_mbuf *m_out_head = enc->output.data;
1344 uint32_t in_length, out_length, e;
1345 uint16_t total_left = enc->input.length;
1346 uint16_t ring_offset;
1349 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1350 /* Validate op structure */
1352 if (validate_enc_op(op) == -1) {
1353 rte_bbdev_log(ERR, "LDPC encoder validation failed");
1358 /* Clear op status */
1361 if (m_in == NULL || m_out == NULL) {
1362 rte_bbdev_log(ERR, "Invalid mbuf pointer");
1363 op->status = 1 << RTE_BBDEV_DATA_ERROR;
1367 if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)
1370 if (enc->code_block_mode == 0) {
1371 /* For Transport Block mode */
1373 c = enc->tb_params.c;
1374 e = enc->tb_params.ea;
1375 } else { /* For Code Block mode */
1377 e = enc->cb_params.e;
1380 /* Update total_left */
1381 K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c;
1382 k_ = K - enc->n_filler;
1383 in_length = (k_ - crc24_bits) >> 3;
1384 out_length = (e + 7) >> 3;
1386 total_left = rte_pktmbuf_data_len(m_in) - in_offset;
1388 /* Update offsets */
1389 if (total_left != in_length) {
1390 op->status |= 1 << RTE_BBDEV_DATA_ERROR;
1392 "Mismatch between mbuf length and included CBs sizes %d",
1396 mbuf_append(m_out_head, m_out, out_length);
1398 /* Offset into the ring */
1399 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1400 /* Setup DMA Descriptor */
1401 desc = q->ring_addr + ring_offset;
1403 ret = fpga_dma_desc_te_fill(op, &desc->enc_req, m_in, m_out,
1404 k_, e, in_offset, out_offset, ring_offset, c);
1405 if (unlikely(ret < 0))
1408 /* Update lengths */
1409 total_left -= in_length;
1410 op->ldpc_enc.output.length += out_length;
1412 if (total_left > 0) {
1414 "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
1415 total_left, in_length);
1419 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1420 print_dma_enc_desc_debug_info(desc);
1426 enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
1427 uint16_t desc_offset)
1429 union fpga_dma_desc *desc;
1431 uint16_t ring_offset;
1433 uint16_t e, in_length, out_length, k0, l, seg_total_left, sys_cols;
1434 uint16_t K, parity_offset, harq_in_length = 0, harq_out_length = 0;
1435 uint16_t crc24_overlap = 0;
1436 struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
1437 struct rte_mbuf *m_in = dec->input.data;
1438 struct rte_mbuf *m_out = dec->hard_output.data;
1439 struct rte_mbuf *m_out_head = dec->hard_output.data;
1440 uint16_t in_offset = dec->input.offset;
1441 uint16_t out_offset = dec->hard_output.offset;
1442 uint32_t harq_offset = 0;
1444 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1445 /* Validate op structure */
1446 if (validate_dec_op(op) == -1) {
1447 rte_bbdev_log(ERR, "LDPC decoder validation failed");
1452 /* Clear op status */
1455 /* Setup DMA Descriptor */
1456 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1457 desc = q->ring_addr + ring_offset;
1459 if (check_bit(dec->op_flags,
1460 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
1461 struct rte_mbuf *harq_in = dec->harq_combined_input.data;
1462 struct rte_mbuf *harq_out = dec->harq_combined_output.data;
1463 harq_in_length = dec->harq_combined_input.length;
1464 uint32_t harq_in_offset = dec->harq_combined_input.offset;
1465 uint32_t harq_out_offset = dec->harq_combined_output.offset;
1467 if (check_bit(dec->op_flags,
1468 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE
1470 ret = fpga_harq_write_loopback(q->d, harq_in,
1471 harq_in_length, harq_in_offset,
1473 } else if (check_bit(dec->op_flags,
1474 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE
1476 ret = fpga_harq_read_loopback(q->d, harq_out,
1477 harq_in_length, harq_in_offset,
1479 dec->harq_combined_output.length = harq_in_length;
1481 rte_bbdev_log(ERR, "OP flag Err!");
1484 /* Set descriptor for dequeue */
1485 desc->dec_req.done = 1;
1486 desc->dec_req.error = 0;
1487 desc->dec_req.op_addr = op;
1488 desc->dec_req.cbs_in_op = 1;
1489 /* Mark this dummy descriptor to be dropped by HW */
1490 desc->dec_req.desc_idx = (ring_offset + 1)
1491 & q->sw_ring_wrap_mask;
1492 return ret; /* Error or number of CB */
1495 if (m_in == NULL || m_out == NULL) {
1496 rte_bbdev_log(ERR, "Invalid mbuf pointer");
1497 op->status = 1 << RTE_BBDEV_DATA_ERROR;
1502 e = dec->cb_params.e;
1504 if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP))
1507 sys_cols = (dec->basegraph == 1) ? 22 : 10;
1508 K = sys_cols * dec->z_c;
1509 parity_offset = K - 2 * dec->z_c;
1511 out_length = ((K - crc24_overlap - dec->n_filler) >> 3);
1513 seg_total_left = dec->input.length;
1515 if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) {
1516 harq_in_length = RTE_MIN(dec->harq_combined_input.length,
1517 (uint32_t)dec->n_cb);
1520 if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {
1521 k0 = get_k0(dec->n_cb, dec->z_c,
1522 dec->basegraph, dec->rv_index);
1523 if (k0 > parity_offset)
1526 l = k0 + e + dec->n_filler;
1527 harq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l),
1528 dec->n_cb - dec->n_filler);
1529 dec->harq_combined_output.length = harq_out_length;
1532 mbuf_append(m_out_head, m_out, out_length);
1533 if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE))
1534 harq_offset = dec->harq_combined_input.offset;
1535 else if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))
1536 harq_offset = dec->harq_combined_output.offset;
1538 if ((harq_offset & 0x3FF) > 0) {
1539 rte_bbdev_log(ERR, "Invalid HARQ offset %d", harq_offset);
1540 op->status = 1 << RTE_BBDEV_DATA_ERROR;
1544 ret = fpga_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out,
1545 harq_in_length, in_offset, out_offset, harq_offset,
1547 if (unlikely(ret < 0))
1549 /* Update lengths */
1550 seg_total_left -= in_length;
1551 op->ldpc_dec.hard_output.length += out_length;
1552 if (seg_total_left > 0) {
1554 "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
1555 seg_total_left, in_length);
1559 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1560 print_dma_dec_desc_debug_info(desc);
1567 fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
1568 struct rte_bbdev_enc_op **ops, uint16_t num)
1570 uint16_t i, total_enqueued_cbs = 0;
1573 struct fpga_queue *q = q_data->queue_private;
1574 union fpga_dma_desc *desc;
1576 /* Check if queue is not full */
1577 if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
1581 /* Calculates available space */
1582 avail = (q->head_free_desc > q->tail) ?
1583 q->head_free_desc - q->tail - 1 :
1584 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
1586 for (i = 0; i < num; ++i) {
1588 /* Check if there is available space for further
1591 if (unlikely(avail - 1 < 0))
1594 enqueued_cbs = enqueue_ldpc_enc_one_op_cb(q, ops[i],
1595 total_enqueued_cbs);
1597 if (enqueued_cbs < 0)
1600 total_enqueued_cbs += enqueued_cbs;
1602 rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d",
1603 total_enqueued_cbs, num,
1604 q->head_free_desc, q->tail);
1607 /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
1608 * only when all previous CBs were already processed.
1610 desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
1611 & q->sw_ring_wrap_mask);
1612 desc->enc_req.irq_en = q->irq_enable;
1614 fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
1617 q_data->queue_stats.enqueued_count += i;
1618 q_data->queue_stats.enqueue_err_count += num - i;
1624 fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
1625 struct rte_bbdev_dec_op **ops, uint16_t num)
1627 uint16_t i, total_enqueued_cbs = 0;
1630 struct fpga_queue *q = q_data->queue_private;
1631 union fpga_dma_desc *desc;
1633 /* Check if queue is not full */
1634 if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
1638 /* Calculates available space */
1639 avail = (q->head_free_desc > q->tail) ?
1640 q->head_free_desc - q->tail - 1 :
1641 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
1643 for (i = 0; i < num; ++i) {
1645 /* Check if there is available space for further
1648 if (unlikely(avail - 1 < 0))
1651 enqueued_cbs = enqueue_ldpc_dec_one_op_cb(q, ops[i],
1652 total_enqueued_cbs);
1654 if (enqueued_cbs < 0)
1657 total_enqueued_cbs += enqueued_cbs;
1659 rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d",
1660 total_enqueued_cbs, num,
1661 q->head_free_desc, q->tail);
1665 q_data->queue_stats.enqueued_count += i;
1666 q_data->queue_stats.enqueue_err_count += num - i;
1668 /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
1669 * only when all previous CBs were already processed.
1671 desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
1672 & q->sw_ring_wrap_mask);
1673 desc->enc_req.irq_en = q->irq_enable;
1674 fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
1680 dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q,
1681 struct rte_bbdev_enc_op **op,
1682 uint16_t desc_offset)
1684 union fpga_dma_desc *desc;
1686 /* Set current desc */
1687 desc = q->ring_addr + ((q->head_free_desc + desc_offset)
1688 & q->sw_ring_wrap_mask);
1691 if (desc->enc_req.done == 0)
1694 /* make sure the response is read atomically */
1697 rte_bbdev_log_debug("DMA response desc %p", desc);
1699 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1700 print_dma_enc_desc_debug_info(desc);
1703 *op = desc->enc_req.op_addr;
1704 /* Check the descriptor error field, return 1 on error */
1705 desc_error = check_desc_error(desc->enc_req.error);
1706 (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
1713 dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
1714 uint16_t desc_offset)
1716 union fpga_dma_desc *desc;
1718 /* Set descriptor */
1719 desc = q->ring_addr + ((q->head_free_desc + desc_offset)
1720 & q->sw_ring_wrap_mask);
1722 /* Verify done bit is set */
1723 if (desc->dec_req.done == 0)
1726 /* make sure the response is read atomically */
1729 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1730 print_dma_dec_desc_debug_info(desc);
1733 *op = desc->dec_req.op_addr;
1735 if (check_bit((*op)->ldpc_dec.op_flags,
1736 RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
1741 /* FPGA reports iterations based on round-up minus 1 */
1742 (*op)->ldpc_dec.iter_count = desc->dec_req.iter + 1;
1743 /* CRC Check criteria */
1744 if (desc->dec_req.crc24b_ind && !(desc->dec_req.crcb_pass))
1745 (*op)->status = 1 << RTE_BBDEV_CRC_ERROR;
1746 /* et_pass = 0 when decoder fails */
1747 (*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;
1748 /* Check the descriptor error field, return 1 on error */
1749 desc_error = check_desc_error(desc->dec_req.error);
1750 (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
1755 fpga_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
1756 struct rte_bbdev_enc_op **ops, uint16_t num)
1758 struct fpga_queue *q = q_data->queue_private;
1759 uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
1761 uint16_t dequeued_cbs = 0;
1764 for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
1765 ret = dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs);
1770 dequeued_cbs += ret;
1772 rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d",
1773 dequeued_cbs, num, q->head_free_desc, q->tail);
1777 q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
1778 q->sw_ring_wrap_mask;
1781 q_data->queue_stats.dequeued_count += i;
1787 fpga_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
1788 struct rte_bbdev_dec_op **ops, uint16_t num)
1790 struct fpga_queue *q = q_data->queue_private;
1791 uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
1793 uint16_t dequeued_cbs = 0;
1796 for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
1797 ret = dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs);
1802 dequeued_cbs += ret;
1804 rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d",
1805 dequeued_cbs, num, q->head_free_desc, q->tail);
1809 q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
1810 q->sw_ring_wrap_mask;
1813 q_data->queue_stats.dequeued_count += i;
1819 /* Initialization Function */
1821 fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
1823 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1825 dev->dev_ops = &fpga_ops;
1826 dev->enqueue_ldpc_enc_ops = fpga_enqueue_ldpc_enc;
1827 dev->enqueue_ldpc_dec_ops = fpga_enqueue_ldpc_dec;
1828 dev->dequeue_ldpc_enc_ops = fpga_dequeue_ldpc_enc;
1829 dev->dequeue_ldpc_dec_ops = fpga_dequeue_ldpc_dec;
1831 ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =
1832 !strcmp(drv->driver.name,
1833 RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));
1834 ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =
1835 pci_dev->mem_resource[0].addr;
1837 rte_bbdev_log_debug(
1838 "Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
1839 dev->device->driver->name, dev->data->name,
1840 (void *)pci_dev->mem_resource[0].addr,
1841 pci_dev->mem_resource[0].phys_addr);
1845 fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,
1846 struct rte_pci_device *pci_dev)
1848 struct rte_bbdev *bbdev = NULL;
1849 char dev_name[RTE_BBDEV_NAME_MAX_LEN];
1851 if (pci_dev == NULL) {
1852 rte_bbdev_log(ERR, "NULL PCI device");
1856 rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));
1858 /* Allocate memory to be used privately by drivers */
1859 bbdev = rte_bbdev_allocate(pci_dev->device.name);
1863 /* allocate device private memory */
1864 bbdev->data->dev_private = rte_zmalloc_socket(dev_name,
1865 sizeof(struct fpga_5gnr_fec_device),
1866 RTE_CACHE_LINE_SIZE,
1867 pci_dev->device.numa_node);
1869 if (bbdev->data->dev_private == NULL) {
1871 "Allocate of %zu bytes for device \"%s\" failed",
1872 sizeof(struct fpga_5gnr_fec_device), dev_name);
1873 rte_bbdev_release(bbdev);
1877 /* Fill HW specific part of device structure */
1878 bbdev->device = &pci_dev->device;
1879 bbdev->intr_handle = &pci_dev->intr_handle;
1880 bbdev->data->socket_id = pci_dev->device.numa_node;
1882 /* Invoke FEC FPGA device initialization function */
1883 fpga_5gnr_fec_init(bbdev, pci_drv);
1885 rte_bbdev_log_debug("bbdev id = %u [%s]",
1886 bbdev->data->dev_id, dev_name);
1888 struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
1889 uint32_t version_id = fpga_reg_read_32(d->mmio_base,
1890 FPGA_5GNR_FEC_VERSION_ID);
1891 rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u",
1892 ((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
1894 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1895 if (!strcmp(bbdev->device->driver->name,
1896 RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)))
1897 print_static_reg_debug_info(d->mmio_base);
1903 fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)
1905 struct rte_bbdev *bbdev;
1909 if (pci_dev == NULL)
1913 bbdev = rte_bbdev_get_named_dev(pci_dev->device.name);
1914 if (bbdev == NULL) {
1916 "Couldn't find HW dev \"%s\" to uninitialise it",
1917 pci_dev->device.name);
1920 dev_id = bbdev->data->dev_id;
1922 /* free device private memory before close */
1923 rte_free(bbdev->data->dev_private);
1926 ret = rte_bbdev_close(dev_id);
1929 "Device %i failed to close during uninit: %i",
1932 /* release bbdev from library */
1933 ret = rte_bbdev_release(bbdev);
1935 rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id,
1938 rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id);
1944 set_default_fpga_conf(struct fpga_5gnr_fec_conf *def_conf)
1946 /* clear default configuration before initialization */
1947 memset(def_conf, 0, sizeof(struct fpga_5gnr_fec_conf));
1948 /* Set pf mode to true */
1949 def_conf->pf_mode_en = true;
1951 /* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */
1952 def_conf->ul_bandwidth = 3;
1953 def_conf->dl_bandwidth = 3;
1955 /* Set Load Balance Factor to 64 */
1956 def_conf->dl_load_balance = 64;
1957 def_conf->ul_load_balance = 64;
1960 /* Initial configuration of FPGA 5GNR FEC device */
1962 fpga_5gnr_fec_configure(const char *dev_name,
1963 const struct fpga_5gnr_fec_conf *conf)
1965 uint32_t payload_32, address;
1966 uint16_t payload_16;
1968 uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;
1969 struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
1970 struct fpga_5gnr_fec_conf def_conf;
1972 if (bbdev == NULL) {
1974 "Invalid dev_name (%s), or device is not yet initialised",
1979 struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
1983 "FPGA Configuration was not provided. Default configuration will be loaded.");
1984 set_default_fpga_conf(&def_conf);
1989 * Configure UL:DL ratio.
1993 payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;
1994 address = FPGA_5GNR_FEC_CONFIGURATION;
1995 fpga_reg_write_16(d->mmio_base, address, payload_16);
1997 /* Clear all queues registers */
1998 payload_32 = FPGA_INVALID_HW_QUEUE_ID;
1999 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
2000 address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
2001 fpga_reg_write_32(d->mmio_base, address, payload_32);
2005 * If PF mode is enabled allocate all queues for PF only.
2007 * For VF mode each VF can have different number of UL and DL queues.
2008 * Total number of queues to configure cannot exceed FPGA
2009 * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.
2010 * Queues mapping is done according to configuration:
2016 * | conf->vf_dl_queues_number[0] - 1 | 0 |
2017 * | conf->vf_dl_queues_number[0] | 1 |
2019 * | conf->vf_dl_queues_number[1] - 1 | 1 |
2021 * | conf->vf_dl_queues_number[7] - 1 | 7 |
2027 * | conf->vf_ul_queues_number[0] - 1 | 0 |
2028 * | conf->vf_ul_queues_number[0] | 1 |
2030 * | conf->vf_ul_queues_number[1] - 1 | 1 |
2032 * | conf->vf_ul_queues_number[7] - 1 | 7 |
2034 * Example of configuration:
2035 * conf->vf_ul_queues_number[0] = 4; -> 4 UL queues for VF0
2036 * conf->vf_dl_queues_number[0] = 4; -> 4 DL queues for VF0
2037 * conf->vf_ul_queues_number[1] = 2; -> 2 UL queues for VF1
2038 * conf->vf_dl_queues_number[1] = 2; -> 2 DL queues for VF1
2058 if (conf->pf_mode_en) {
2060 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
2061 address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
2062 fpga_reg_write_32(d->mmio_base, address, payload_32);
2065 /* Calculate total number of UL and DL queues to configure */
2066 total_ul_q_id = total_dl_q_id = 0;
2067 for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
2068 total_ul_q_id += conf->vf_ul_queues_number[vf_id];
2069 total_dl_q_id += conf->vf_dl_queues_number[vf_id];
2071 total_q_id = total_dl_q_id + total_ul_q_id;
2073 * Check if total number of queues to configure does not exceed
2074 * FPGA capabilities (64 queues - 32 UL and 32 DL queues)
2076 if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||
2077 (total_dl_q_id > FPGA_NUM_DL_QUEUES) ||
2078 (total_q_id > FPGA_TOTAL_NUM_QUEUES)) {
2080 "FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u",
2081 total_ul_q_id, total_dl_q_id,
2082 FPGA_TOTAL_NUM_QUEUES);
2086 for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
2087 for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];
2088 ++q_id, ++total_ul_q_id) {
2089 address = (total_ul_q_id << 2) +
2090 FPGA_5GNR_FEC_QUEUE_MAP;
2091 payload_32 = ((0x80 + vf_id) << 16) | 0x1;
2092 fpga_reg_write_32(d->mmio_base, address,
2097 for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
2098 for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];
2099 ++q_id, ++total_dl_q_id) {
2100 address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)
2101 << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
2102 payload_32 = ((0x80 + vf_id) << 16) | 0x1;
2103 fpga_reg_write_32(d->mmio_base, address,
2109 /* Setting Load Balance Factor */
2110 payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);
2111 address = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;
2112 fpga_reg_write_16(d->mmio_base, address, payload_16);
2114 /* Setting length of ring descriptor entry */
2115 payload_16 = FPGA_RING_DESC_ENTRY_LENGTH;
2116 address = FPGA_5GNR_FEC_RING_DESC_LEN;
2117 fpga_reg_write_16(d->mmio_base, address, payload_16);
2119 /* Setting FLR timeout value */
2120 payload_16 = conf->flr_time_out;
2121 address = FPGA_5GNR_FEC_FLR_TIME_OUT;
2122 fpga_reg_write_16(d->mmio_base, address, payload_16);
2124 /* Queue PF/VF mapping table is ready */
2126 address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;
2127 fpga_reg_write_8(d->mmio_base, address, payload_8);
2129 rte_bbdev_log_debug("PF FPGA 5GNR FEC configuration complete for %s",
2132 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2133 print_static_reg_debug_info(d->mmio_base);
2138 /* FPGA 5GNR FEC PCI PF address map */
2139 static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {
2141 RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
2142 FPGA_5GNR_FEC_PF_DEVICE_ID)
2147 static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {
2148 .probe = fpga_5gnr_fec_probe,
2149 .remove = fpga_5gnr_fec_remove,
2150 .id_table = pci_id_fpga_5gnr_fec_pf_map,
2151 .drv_flags = RTE_PCI_DRV_NEED_MAPPING
2154 /* FPGA 5GNR FEC PCI VF address map */
2155 static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {
2157 RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
2158 FPGA_5GNR_FEC_VF_DEVICE_ID)
2163 static struct rte_pci_driver fpga_5gnr_fec_pci_vf_driver = {
2164 .probe = fpga_5gnr_fec_probe,
2165 .remove = fpga_5gnr_fec_remove,
2166 .id_table = pci_id_fpga_5gnr_fec_vf_map,
2167 .drv_flags = RTE_PCI_DRV_NEED_MAPPING
2171 RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_PF_DRIVER_NAME, fpga_5gnr_fec_pci_pf_driver);
2172 RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME,
2173 pci_id_fpga_5gnr_fec_pf_map);
2174 RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver);
2175 RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME,
2176 pci_id_fpga_5gnr_fec_vf_map);
2178 RTE_INIT(fpga_5gnr_fec_init_log)
2180 fpga_5gnr_fec_logtype = rte_log_register("pmd.bb.fpga_5gnr_fec");
2181 if (fpga_5gnr_fec_logtype >= 0)
2182 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2183 rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG);
2185 rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE);