1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
7 #include <rte_common.h>
10 #include <rte_malloc.h>
11 #include <rte_mempool.h>
12 #include <rte_errno.h>
14 #include <rte_bus_pci.h>
15 #include <rte_byteorder.h>
16 #ifdef RTE_BBDEV_OFFLOAD_COST
17 #include <rte_cycles.h>
20 #include <rte_bbdev.h>
21 #include <rte_bbdev_pmd.h>
23 #include "fpga_lte_fec.h"
25 /* Turbo SW PMD logging ID */
26 static int fpga_lte_fec_logtype;
28 /* Helper macro for logging */
29 #define rte_bbdev_log(level, fmt, ...) \
30 rte_log(RTE_LOG_ ## level, fpga_lte_fec_logtype, fmt "\n", \
33 #ifdef RTE_LIBRTE_BBDEV_DEBUG
34 #define rte_bbdev_log_debug(fmt, ...) \
35 rte_bbdev_log(DEBUG, "fpga_lte_fec: " fmt, \
38 #define rte_bbdev_log_debug(fmt, ...)
41 /* FPGA LTE FEC driver names */
42 #define FPGA_LTE_FEC_PF_DRIVER_NAME intel_fpga_lte_fec_pf
43 #define FPGA_LTE_FEC_VF_DRIVER_NAME intel_fpga_lte_fec_vf
45 /* FPGA LTE FEC PCI vendor & device IDs */
46 #define FPGA_LTE_FEC_VENDOR_ID (0x1172)
47 #define FPGA_LTE_FEC_PF_DEVICE_ID (0x5052)
48 #define FPGA_LTE_FEC_VF_DEVICE_ID (0x5050)
50 /* Align DMA descriptors to 256 bytes - cache-aligned */
51 #define FPGA_RING_DESC_ENTRY_LENGTH (8)
52 /* Ring size is in 256 bits (32 bytes) units */
53 #define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
54 /* Maximum size of queue */
55 #define FPGA_RING_MAX_SIZE (1024)
56 #define FPGA_FLR_TIMEOUT_UNIT (16.384)
58 #define FPGA_NUM_UL_QUEUES (32)
59 #define FPGA_NUM_DL_QUEUES (32)
60 #define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)
61 #define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)
63 #define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)
65 #define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)
66 #define FPGA_TIMEOUT_CHECK_INTERVAL (5)
68 /* FPGA LTE FEC Register mapping on BAR0 */
70 FPGA_LTE_FEC_VERSION_ID = 0x00000000, /* len: 4B */
71 FPGA_LTE_FEC_CONFIGURATION = 0x00000004, /* len: 2B */
72 FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
73 FPGA_LTE_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
74 FPGA_LTE_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
75 FPGA_LTE_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
76 FPGA_LTE_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
77 FPGA_LTE_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
78 FPGA_LTE_FEC_VF0_DEBUG = 0x00000020, /* len: 4B */
79 FPGA_LTE_FEC_VF1_DEBUG = 0x00000024, /* len: 4B */
80 FPGA_LTE_FEC_VF2_DEBUG = 0x00000028, /* len: 4B */
81 FPGA_LTE_FEC_VF3_DEBUG = 0x0000002c, /* len: 4B */
82 FPGA_LTE_FEC_VF4_DEBUG = 0x00000030, /* len: 4B */
83 FPGA_LTE_FEC_VF5_DEBUG = 0x00000034, /* len: 4B */
84 FPGA_LTE_FEC_VF6_DEBUG = 0x00000038, /* len: 4B */
85 FPGA_LTE_FEC_VF7_DEBUG = 0x0000003c, /* len: 4B */
86 FPGA_LTE_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */
87 FPGA_LTE_FEC_RING_CTRL_REGS = 0x00000200 /* len: 2048B */
90 /* FPGA LTE FEC Ring Control Registers */
92 FPGA_LTE_FEC_RING_HEAD_ADDR = 0x00000008,
93 FPGA_LTE_FEC_RING_SIZE = 0x00000010,
94 FPGA_LTE_FEC_RING_MISC = 0x00000014,
95 FPGA_LTE_FEC_RING_ENABLE = 0x00000015,
96 FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,
97 FPGA_LTE_FEC_RING_SHADOW_TAIL = 0x00000018,
98 FPGA_LTE_FEC_RING_HEAD_POINT = 0x0000001C
101 /* FPGA LTE FEC DESCRIPTOR ERROR */
103 DESC_ERR_NO_ERR = 0x0,
104 DESC_ERR_K_OUT_OF_RANGE = 0x1,
105 DESC_ERR_K_NOT_NORMAL = 0x2,
106 DESC_ERR_KPAI_NOT_NORMAL = 0x3,
107 DESC_ERR_DESC_OFFSET_ERR = 0x4,
108 DESC_ERR_DESC_READ_FAIL = 0x8,
109 DESC_ERR_DESC_READ_TIMEOUT = 0x9,
110 DESC_ERR_DESC_READ_TLP_POISONED = 0xA,
111 DESC_ERR_CB_READ_FAIL = 0xC,
112 DESC_ERR_CB_READ_TIMEOUT = 0xD,
113 DESC_ERR_CB_READ_TLP_POISONED = 0xE
116 /* FPGA LTE FEC DMA Encoding Request Descriptor */
117 struct __attribute__((__packed__)) fpga_dma_enc_desc {
125 uint32_t bypass_rm:1,
133 uint32_t out_addr_lw;
134 uint32_t out_addr_hi;
140 /* Virtual addresses used to retrieve SW context info */
142 /* Stores information about total number of Code Blocks
143 * in currently processed Transport Block
148 uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
149 (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
153 /* FPGA LTE FEC DMA Decoding Request Descriptor */
154 struct __attribute__((__packed__)) fpga_dma_dec_desc {
166 uint32_t bypass_rm:1,
174 uint32_t out_addr_lw;
175 uint32_t out_addr_hi;
181 /* Virtual addresses used to retrieve SW context info */
183 /* Stores information about total number of Code Blocks
184 * in currently processed Transport Block
189 uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
193 /* FPGA LTE DMA Descriptor */
194 union fpga_dma_desc {
195 struct fpga_dma_enc_desc enc_req;
196 struct fpga_dma_dec_desc dec_req;
199 /* FPGA LTE FEC Ring Control Register */
200 struct __attribute__((__packed__)) fpga_ring_ctrl_reg {
201 uint64_t ring_base_addr;
202 uint64_t ring_head_addr;
203 uint16_t ring_size:11;
205 union { /* Miscellaneous register */
207 uint8_t max_ul_dec:5,
212 uint8_t flush_queue_en;
214 uint16_t shadow_tail;
221 /* Private data structure for each FPGA FEC device */
222 struct fpga_lte_fec_device {
223 /** Base address of MMIO registers (BAR0) */
225 /** Base address of memory for sw rings */
227 /** Physical address of sw_rings */
228 rte_iova_t sw_rings_phys;
229 /** Number of bytes available for each queue in device. */
230 uint32_t sw_ring_size;
231 /** Max number of entries available for each queue in device */
232 uint32_t sw_ring_max_depth;
233 /** Base address of response tail pointer buffer */
235 /** Physical address of tail pointers */
236 rte_iova_t tail_ptr_phys;
237 /** Queues flush completion flag */
238 uint64_t *flush_queue_status;
239 /* Bitmap capturing which Queues are bound to the PF/VF */
240 uint64_t q_bound_bit_map;
241 /* Bitmap capturing which Queues have already been assigned */
242 uint64_t q_assigned_bit_map;
243 /** True if this is a PF FPGA FEC device */
247 /* Structure associated with each queue. */
248 struct __rte_cache_aligned fpga_queue {
249 struct fpga_ring_ctrl_reg ring_ctrl_reg; /* Ring Control Register */
250 union fpga_dma_desc *ring_addr; /* Virtual address of software ring */
251 uint64_t *ring_head_addr; /* Virtual address of completion_head */
252 uint64_t shadow_completion_head; /* Shadow completion head value */
253 uint16_t head_free_desc; /* Ring head */
254 uint16_t tail; /* Ring tail */
255 /* Mask used to wrap enqueued descriptors on the sw ring */
256 uint32_t sw_ring_wrap_mask;
257 uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */
258 uint8_t q_idx; /* Queue index */
259 struct fpga_lte_fec_device *d;
260 /* MMIO register of shadow_tail used to enqueue descriptors */
261 void *shadow_tail_addr;
264 /* Write to 16 bit MMIO register address */
266 mmio_write_16(void *addr, uint16_t value)
268 *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);
271 /* Write to 32 bit MMIO register address */
273 mmio_write_32(void *addr, uint32_t value)
275 *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
278 /* Write to 64 bit MMIO register address */
280 mmio_write_64(void *addr, uint64_t value)
282 *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);
285 /* Write a 8 bit register of a FPGA LTE FEC device */
287 fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)
289 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
290 *((volatile uint8_t *)(reg_addr)) = payload;
293 /* Write a 16 bit register of a FPGA LTE FEC device */
295 fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)
297 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
298 mmio_write_16(reg_addr, payload);
301 /* Write a 32 bit register of a FPGA LTE FEC device */
303 fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)
305 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
306 mmio_write_32(reg_addr, payload);
309 /* Write a 64 bit register of a FPGA LTE FEC device */
311 fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)
313 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
314 mmio_write_64(reg_addr, payload);
317 /* Write a ring control register of a FPGA LTE FEC device */
319 fpga_ring_reg_write(void *mmio_base, uint32_t offset,
320 struct fpga_ring_ctrl_reg payload)
322 fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);
323 fpga_reg_write_64(mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_ADDR,
324 payload.ring_head_addr);
325 fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_SIZE,
327 fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_POINT,
329 fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN,
330 payload.flush_queue_en);
331 fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_SHADOW_TAIL,
332 payload.shadow_tail);
333 fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_MISC,
335 fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE,
339 /* Read a register of FPGA LTE FEC device */
341 fpga_reg_read_32(void *mmio_base, uint32_t offset)
343 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
344 uint32_t ret = *((volatile uint32_t *)(reg_addr));
345 return rte_le_to_cpu_32(ret);
348 #ifdef RTE_LIBRTE_BBDEV_DEBUG
349 /* Read a register of FPGA LTE FEC device */
351 fpga_reg_read_8(void *mmio_base, uint32_t offset)
353 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
354 return *((volatile uint8_t *)(reg_addr));
357 /* Read a register of FPGA LTE FEC device */
359 fpga_reg_read_16(void *mmio_base, uint32_t offset)
361 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
362 uint16_t ret = *((volatile uint16_t *)(reg_addr));
363 return rte_le_to_cpu_16(ret);
366 /* Read a register of FPGA LTE FEC device */
368 fpga_reg_read_64(void *mmio_base, uint32_t offset)
370 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
371 uint64_t ret = *((volatile uint64_t *)(reg_addr));
372 return rte_le_to_cpu_64(ret);
375 /* Read Ring Control Register of FPGA LTE FEC device */
377 print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
380 "FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
381 PRIx32, mmio_base, offset);
383 "RING_BASE_ADDR = 0x%016"PRIx64,
384 fpga_reg_read_64(mmio_base, offset));
386 "RING_HEAD_ADDR = 0x%016"PRIx64,
387 fpga_reg_read_64(mmio_base, offset +
388 FPGA_LTE_FEC_RING_HEAD_ADDR));
390 "RING_SIZE = 0x%04"PRIx16,
391 fpga_reg_read_16(mmio_base, offset +
392 FPGA_LTE_FEC_RING_SIZE));
394 "RING_MISC = 0x%02"PRIx8,
395 fpga_reg_read_8(mmio_base, offset +
396 FPGA_LTE_FEC_RING_MISC));
398 "RING_ENABLE = 0x%02"PRIx8,
399 fpga_reg_read_8(mmio_base, offset +
400 FPGA_LTE_FEC_RING_ENABLE));
402 "RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
403 fpga_reg_read_8(mmio_base, offset +
404 FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN));
406 "RING_SHADOW_TAIL = 0x%04"PRIx16,
407 fpga_reg_read_16(mmio_base, offset +
408 FPGA_LTE_FEC_RING_SHADOW_TAIL));
410 "RING_HEAD_POINT = 0x%04"PRIx16,
411 fpga_reg_read_16(mmio_base, offset +
412 FPGA_LTE_FEC_RING_HEAD_POINT));
415 /* Read Static Register of FPGA LTE FEC device */
417 print_static_reg_debug_info(void *mmio_base)
419 uint16_t config = fpga_reg_read_16(mmio_base,
420 FPGA_LTE_FEC_CONFIGURATION);
421 uint8_t qmap_done = fpga_reg_read_8(mmio_base,
422 FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE);
423 uint16_t lb_factor = fpga_reg_read_16(mmio_base,
424 FPGA_LTE_FEC_LOAD_BALANCE_FACTOR);
425 uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
426 FPGA_LTE_FEC_RING_DESC_LEN);
427 uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
428 FPGA_LTE_FEC_FLR_TIME_OUT);
430 rte_bbdev_log_debug("UL.DL Weights = %u.%u",
431 ((uint8_t)config), ((uint8_t)(config >> 8)));
432 rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
433 ((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
434 rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
435 (qmap_done > 0) ? "READY" : "NOT-READY");
436 rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
437 ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
438 rte_bbdev_log_debug("FLR Timeout = %f usec",
439 (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
442 /* Print decode DMA Descriptor of FPGA LTE FEC device */
444 print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
446 rte_bbdev_log_debug("DMA response desc %p\n"
447 "\t-- done(%"PRIu32") | iter(%"PRIu32") | crc_pass(%"PRIu32")"
448 " | error (%"PRIu32") | crc_type(%"PRIu32")\n"
449 "\t-- max_iter(%"PRIu32") | bypass_rm(%"PRIu32") | "
450 "irq_en (%"PRIu32") | drop_crc(%"PRIu32") | offset(%"PRIu32")\n"
451 "\t-- k(%"PRIu32") | in_len (%"PRIu16") | op_add(%p)\n"
452 "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32") | "
453 "out_add (0x%08"PRIx32"%08"PRIx32")",
455 (uint32_t)desc->dec_req.done,
456 (uint32_t)desc->dec_req.iter,
457 (uint32_t)desc->dec_req.crc_pass,
458 (uint32_t)desc->dec_req.error,
459 (uint32_t)desc->dec_req.crc_type,
460 (uint32_t)desc->dec_req.max_iter,
461 (uint32_t)desc->dec_req.bypass_rm,
462 (uint32_t)desc->dec_req.irq_en,
463 (uint32_t)desc->dec_req.drop_crc,
464 (uint32_t)desc->dec_req.offset,
465 (uint32_t)desc->dec_req.k,
466 (uint16_t)desc->dec_req.in_len,
467 desc->dec_req.op_addr,
468 (uint32_t)desc->dec_req.cbs_in_op,
469 (uint32_t)desc->dec_req.in_addr_hi,
470 (uint32_t)desc->dec_req.in_addr_lw,
471 (uint32_t)desc->dec_req.out_addr_hi,
472 (uint32_t)desc->dec_req.out_addr_lw);
477 fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
479 /* Number of queues bound to a PF/VF */
480 uint32_t hw_q_num = 0;
481 uint32_t ring_size, payload, address, q_id, offset;
482 rte_iova_t phys_addr;
483 struct fpga_ring_ctrl_reg ring_reg;
484 struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private;
486 address = FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE;
487 if (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) {
489 "Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?",
494 /* Clear queue registers structure */
495 memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
498 * If a queue is valid and mapped to a calling PF/VF the read value is
499 * replaced with a queue ID and if it's not then
500 * FPGA_INVALID_HW_QUEUE_ID is returned.
502 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
503 uint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base,
504 FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2));
506 rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u",
507 dev->device->name, q_id, hw_q_id);
509 if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) {
510 fpga_dev->q_bound_bit_map |= (1ULL << q_id);
511 /* Clear queue register of found queue */
512 offset = FPGA_LTE_FEC_RING_CTRL_REGS +
513 (sizeof(struct fpga_ring_ctrl_reg) * q_id);
514 fpga_ring_reg_write(fpga_dev->mmio_base,
521 "No HW queues assigned to this device. Probably this is a VF configured for PF mode. Check device configuration!");
525 if (num_queues > hw_q_num) {
527 "Not enough queues for device %s! Requested: %u, available: %u",
528 dev->device->name, num_queues, hw_q_num);
532 ring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);
534 /* Enforce 32 byte alignment */
535 RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);
537 /* Allocate memory for SW descriptor rings */
538 fpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name,
539 num_queues * ring_size, RTE_CACHE_LINE_SIZE,
541 if (fpga_dev->sw_rings == NULL) {
543 "Failed to allocate memory for %s:%u sw_rings",
544 dev->device->driver->name, dev->data->dev_id);
548 fpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings);
549 fpga_dev->sw_ring_size = ring_size;
550 fpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE;
552 /* Allocate memory for ring flush status */
553 fpga_dev->flush_queue_status = rte_zmalloc_socket(NULL,
554 sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);
555 if (fpga_dev->flush_queue_status == NULL) {
557 "Failed to allocate memory for %s:%u flush_queue_status",
558 dev->device->driver->name, dev->data->dev_id);
562 /* Set the flush status address registers */
563 phys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status);
565 address = FPGA_LTE_FEC_VFQ_FLUSH_STATUS_LW;
566 payload = (uint32_t)(phys_addr);
567 fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
569 address = FPGA_LTE_FEC_VFQ_FLUSH_STATUS_HI;
570 payload = (uint32_t)(phys_addr >> 32);
571 fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
577 fpga_dev_close(struct rte_bbdev *dev)
579 struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private;
581 rte_free(fpga_dev->sw_rings);
582 rte_free(fpga_dev->flush_queue_status);
588 fpga_dev_info_get(struct rte_bbdev *dev,
589 struct rte_bbdev_driver_info *dev_info)
591 struct fpga_lte_fec_device *d = dev->data->dev_private;
594 /* TODO RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN and numbers of buffers are set
595 * to temporary values as they are required by test application while
598 static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
600 .type = RTE_BBDEV_OP_TURBO_DEC,
603 RTE_BBDEV_TURBO_CRC_TYPE_24B |
604 RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE |
605 RTE_BBDEV_TURBO_DEC_INTERRUPTS |
606 RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |
607 RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP,
608 .max_llr_modulus = INT8_MAX,
610 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
611 .num_buffers_hard_out =
612 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
613 .num_buffers_soft_out = 0
617 .type = RTE_BBDEV_OP_TURBO_ENC,
620 RTE_BBDEV_TURBO_CRC_24B_ATTACH |
621 RTE_BBDEV_TURBO_RATE_MATCH |
622 RTE_BBDEV_TURBO_ENC_INTERRUPTS,
624 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
626 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS
629 RTE_BBDEV_END_OF_CAPABILITIES_LIST()
632 static struct rte_bbdev_queue_conf default_queue_conf;
633 default_queue_conf.socket = dev->data->socket_id;
634 default_queue_conf.queue_size = FPGA_RING_MAX_SIZE;
637 dev_info->driver_name = dev->device->driver->name;
638 dev_info->queue_size_lim = FPGA_RING_MAX_SIZE;
639 dev_info->hardware_accelerated = true;
640 dev_info->min_alignment = 64;
641 dev_info->default_queue_conf = default_queue_conf;
642 dev_info->capabilities = bbdev_capabilities;
643 dev_info->cpu_flag_reqs = NULL;
645 /* Calculates number of queues assigned to device */
646 dev_info->max_num_queues = 0;
647 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
648 uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,
649 FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2));
650 if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)
651 dev_info->max_num_queues++;
656 * Find index of queue bound to current PF/VF which is unassigned. Return -1
657 * when there is no available queue
660 fpga_find_free_queue_idx(struct rte_bbdev *dev,
661 const struct rte_bbdev_queue_conf *conf)
663 struct fpga_lte_fec_device *d = dev->data->dev_private;
666 uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1;
668 if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) {
669 i = FPGA_NUM_DL_QUEUES;
670 range = FPGA_TOTAL_NUM_QUEUES;
673 for (; i < range; ++i) {
675 /* Check if index of queue is bound to current PF/VF */
676 if (d->q_bound_bit_map & q_idx)
677 /* Check if found queue was not already assigned */
678 if (!(d->q_assigned_bit_map & q_idx)) {
679 d->q_assigned_bit_map |= q_idx;
684 rte_bbdev_log(INFO, "Failed to find free queue on %s", dev->data->name);
690 fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
691 const struct rte_bbdev_queue_conf *conf)
693 uint32_t address, ring_offset;
694 struct fpga_lte_fec_device *d = dev->data->dev_private;
695 struct fpga_queue *q;
698 /* Check if there is a free queue to assign */
699 q_idx = fpga_find_free_queue_idx(dev, conf);
703 /* Allocate the queue data structure. */
704 q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
705 RTE_CACHE_LINE_SIZE, conf->socket);
707 /* Mark queue as un-assigned */
708 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
709 rte_bbdev_log(ERR, "Failed to allocate queue memory");
716 /* Set ring_base_addr */
717 q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
718 q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys +
719 (d->sw_ring_size * queue_id);
721 /* Allocate memory for Completion Head variable*/
722 q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,
723 sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket);
724 if (q->ring_head_addr == NULL) {
725 /* Mark queue as un-assigned */
726 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
729 "Failed to allocate memory for %s:%u completion_head",
730 dev->device->driver->name, dev->data->dev_id);
733 /* Set ring_head_addr */
734 q->ring_ctrl_reg.ring_head_addr =
735 rte_malloc_virt2iova(q->ring_head_addr);
737 /* Clear shadow_completion_head */
738 q->shadow_completion_head = 0;
741 if (conf->queue_size > FPGA_RING_MAX_SIZE) {
742 /* Mark queue as un-assigned */
743 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
744 rte_free(q->ring_head_addr);
747 "Size of queue is too big %d (MAX: %d ) for %s:%u",
748 conf->queue_size, FPGA_RING_MAX_SIZE,
749 dev->device->driver->name, dev->data->dev_id);
752 q->ring_ctrl_reg.ring_size = conf->queue_size;
754 /* Set Miscellaneous FPGA register*/
755 /* Max iteration number for TTI mitigation - todo */
756 q->ring_ctrl_reg.max_ul_dec = 0;
757 /* Enable max iteration number for TTI - todo */
758 q->ring_ctrl_reg.max_ul_dec_en = 0;
760 /* Enable the ring */
761 q->ring_ctrl_reg.enable = 1;
763 /* Set FPGA head_point and tail registers */
764 q->ring_ctrl_reg.head_point = q->tail = 0;
766 /* Set FPGA shadow_tail register */
767 q->ring_ctrl_reg.shadow_tail = q->tail;
769 /* Calculates the ring offset for found queue */
770 ring_offset = FPGA_LTE_FEC_RING_CTRL_REGS +
771 (sizeof(struct fpga_ring_ctrl_reg) * q_idx);
773 /* Set FPGA Ring Control Registers */
774 fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);
776 /* Store MMIO register of shadow_tail */
777 address = ring_offset + FPGA_LTE_FEC_RING_SHADOW_TAIL;
778 q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address);
780 q->head_free_desc = q->tail;
783 q->sw_ring_wrap_mask = conf->queue_size - 1;
785 rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u",
786 dev->data->dev_id, queue_id, q->q_idx);
788 dev->data->queues[queue_id].queue_private = q;
790 rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]",
793 #ifdef RTE_LIBRTE_BBDEV_DEBUG
794 /* Read FPGA Ring Control Registers after configuration*/
795 print_ring_reg_debug_info(d->mmio_base, ring_offset);
801 fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)
803 struct fpga_lte_fec_device *d = dev->data->dev_private;
804 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
805 struct fpga_ring_ctrl_reg ring_reg;
808 rte_bbdev_log_debug("FPGA Queue[%d] released", queue_id);
811 memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
812 offset = FPGA_LTE_FEC_RING_CTRL_REGS +
813 (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
815 fpga_reg_write_8(d->mmio_base,
816 offset + FPGA_LTE_FEC_RING_ENABLE, 0x00);
817 /* Clear queue registers */
818 fpga_ring_reg_write(d->mmio_base, offset, ring_reg);
820 /* Mark the Queue as un-assigned */
821 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx));
822 rte_free(q->ring_head_addr);
824 dev->data->queues[queue_id].queue_private = NULL;
830 /* Function starts a device queue. */
832 fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)
834 struct fpga_lte_fec_device *d = dev->data->dev_private;
835 #ifdef RTE_LIBRTE_BBDEV_DEBUG
837 rte_bbdev_log(ERR, "Invalid device pointer");
841 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
842 uint32_t offset = FPGA_LTE_FEC_RING_CTRL_REGS +
843 (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
844 uint8_t enable = 0x01;
845 uint16_t zero = 0x0000;
847 /* Clear queue head and tail variables */
848 q->tail = q->head_free_desc = 0;
850 /* Clear FPGA head_point and tail registers */
851 fpga_reg_write_16(d->mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_POINT,
853 fpga_reg_write_16(d->mmio_base, offset + FPGA_LTE_FEC_RING_SHADOW_TAIL,
857 fpga_reg_write_8(d->mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE,
860 rte_bbdev_log_debug("FPGA Queue[%d] started", queue_id);
864 /* Function stops a device queue. */
866 fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)
868 struct fpga_lte_fec_device *d = dev->data->dev_private;
869 #ifdef RTE_LIBRTE_BBDEV_DEBUG
871 rte_bbdev_log(ERR, "Invalid device pointer");
875 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
876 uint32_t offset = FPGA_LTE_FEC_RING_CTRL_REGS +
877 (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
878 uint8_t payload = 0x01;
880 uint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US /
881 FPGA_TIMEOUT_CHECK_INTERVAL;
883 /* Set flush_queue_en bit to trigger queue flushing */
884 fpga_reg_write_8(d->mmio_base,
885 offset + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN, payload);
887 /** Check if queue flush is completed.
888 * FPGA will update the completion flag after queue flushing is
889 * completed. If completion flag is not updated within 1ms it is
890 * considered as a failure.
892 while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {
893 if (counter > timeout) {
894 rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
898 usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
904 fpga_reg_write_8(d->mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE,
907 rte_bbdev_log_debug("FPGA Queue[%d] stopped", queue_id);
911 static inline uint16_t
912 get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)
916 for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
917 struct fpga_queue *q = data->queues[queue_id].queue_private;
918 if (q != NULL && q->q_idx == q_idx)
925 /* Interrupt handler triggered by FPGA dev for handling specific interrupt */
927 fpga_dev_interrupt_handler(void *cb_arg)
929 struct rte_bbdev *dev = cb_arg;
930 struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private;
931 struct fpga_queue *q;
937 /* Scan queue assigned to this device */
938 for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {
940 if (fpga_dev->q_bound_bit_map & q_idx) {
941 queue_id = get_queue_id(dev->data, i);
942 if (queue_id == (uint16_t) -1)
945 /* Check if completion head was changed */
946 q = dev->data->queues[queue_id].queue_private;
947 ring_head = *q->ring_head_addr;
948 if (q->shadow_completion_head != ring_head &&
949 q->irq_enable == 1) {
950 q->shadow_completion_head = ring_head;
951 rte_bbdev_pmd_callback_process(
953 RTE_BBDEV_EVENT_DEQUEUE,
961 fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)
963 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
965 if (!rte_intr_cap_multiple(dev->intr_handle))
974 fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)
976 struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
983 fpga_intr_enable(struct rte_bbdev *dev)
988 if (!rte_intr_cap_multiple(dev->intr_handle)) {
989 rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)",
994 /* Create event file descriptors for each of 64 queue. Event fds will be
995 * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where
996 * the IRQ number is a direct translation to the queue number.
998 * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()
999 * mapped the first IRQ to already created interrupt event file
1000 * descriptor (intr_handle->fd).
1002 if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {
1003 rte_bbdev_log(ERR, "Failed to create fds for %u queues",
1004 dev->data->num_queues);
1008 /* TODO Each event file descriptor is overwritten by interrupt event
1009 * file descriptor. That descriptor is added to epoll observed list.
1010 * It ensures that callback function assigned to that descriptor will
1011 * invoked when any FPGA queue issues interrupt.
1013 for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
1014 dev->intr_handle->efds[i] = dev->intr_handle->fd;
1016 if (!dev->intr_handle->intr_vec) {
1017 dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
1018 dev->data->num_queues * sizeof(int), 0);
1019 if (!dev->intr_handle->intr_vec) {
1020 rte_bbdev_log(ERR, "Failed to allocate %u vectors",
1021 dev->data->num_queues);
1026 ret = rte_intr_enable(dev->intr_handle);
1029 "Couldn't enable interrupts for device: %s",
1034 ret = rte_intr_callback_register(dev->intr_handle,
1035 fpga_dev_interrupt_handler, dev);
1038 "Couldn't register interrupt callback for device: %s",
1046 static const struct rte_bbdev_ops fpga_ops = {
1047 .setup_queues = fpga_setup_queues,
1048 .intr_enable = fpga_intr_enable,
1049 .close = fpga_dev_close,
1050 .info_get = fpga_dev_info_get,
1051 .queue_setup = fpga_queue_setup,
1052 .queue_stop = fpga_queue_stop,
1053 .queue_start = fpga_queue_start,
1054 .queue_release = fpga_queue_release,
1055 .queue_intr_enable = fpga_queue_intr_enable,
1056 .queue_intr_disable = fpga_queue_intr_disable
1060 fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
1061 struct rte_bbdev_stats *queue_stats)
1063 #ifdef RTE_BBDEV_OFFLOAD_COST
1064 uint64_t start_time = 0;
1065 queue_stats->acc_offload_cycles = 0;
1067 RTE_SET_USED(queue_stats);
1070 /* Update tail and shadow_tail register */
1071 q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;
1075 #ifdef RTE_BBDEV_OFFLOAD_COST
1076 /* Start time measurement for enqueue function offload. */
1077 start_time = rte_rdtsc_precise();
1079 mmio_write_16(q->shadow_tail_addr, q->tail);
1081 #ifdef RTE_BBDEV_OFFLOAD_COST
1083 queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;
1087 /* Calculates number of CBs in processed encoder TB based on 'r' and input
1090 static inline uint8_t
1091 get_num_cbs_in_op_enc(struct rte_bbdev_op_turbo_enc *turbo_enc)
1093 uint8_t c, c_neg, r, crc24_bits = 0;
1094 uint16_t k, k_neg, k_pos;
1095 uint8_t cbs_in_op = 0;
1098 length = turbo_enc->input.length;
1099 r = turbo_enc->tb_params.r;
1100 c = turbo_enc->tb_params.c;
1101 c_neg = turbo_enc->tb_params.c_neg;
1102 k_neg = turbo_enc->tb_params.k_neg;
1103 k_pos = turbo_enc->tb_params.k_pos;
1105 while (length > 0 && r < c) {
1106 k = (r < c_neg) ? k_neg : k_pos;
1107 length -= (k - crc24_bits) >> 3;
1115 /* Calculates number of CBs in processed decoder TB based on 'r' and input
1118 static inline uint16_t
1119 get_num_cbs_in_op_dec(struct rte_bbdev_op_turbo_dec *turbo_dec)
1121 uint8_t c, c_neg, r = 0;
1122 uint16_t kw, k, k_neg, k_pos, cbs_in_op = 0;
1125 length = turbo_dec->input.length;
1126 r = turbo_dec->tb_params.r;
1127 c = turbo_dec->tb_params.c;
1128 c_neg = turbo_dec->tb_params.c_neg;
1129 k_neg = turbo_dec->tb_params.k_neg;
1130 k_pos = turbo_dec->tb_params.k_pos;
1131 while (length > 0 && r < c) {
1132 k = (r < c_neg) ? k_neg : k_pos;
1133 kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
1142 /* Read flag value 0/1/ from bitmap */
1144 check_bit(uint32_t bitmap, uint32_t bitmask)
1146 return bitmap & bitmask;
1149 /* Print an error if a descriptor error has occurred.
1150 * Return 0 on success, 1 on failure
1153 check_desc_error(uint32_t error_code) {
1154 switch (error_code) {
1155 case DESC_ERR_NO_ERR:
1157 case DESC_ERR_K_OUT_OF_RANGE:
1158 rte_bbdev_log(ERR, "Block_size_k is out of range (k<40 or k>6144)");
1160 case DESC_ERR_K_NOT_NORMAL:
1161 rte_bbdev_log(ERR, "Block_size_k is not a normal value within normal range");
1163 case DESC_ERR_KPAI_NOT_NORMAL:
1164 rte_bbdev_log(ERR, "Three_kpai is not a normal value for UL only");
1166 case DESC_ERR_DESC_OFFSET_ERR:
1167 rte_bbdev_log(ERR, "Queue offset does not meet the expectation in the FPGA");
1169 case (DESC_ERR_K_OUT_OF_RANGE | DESC_ERR_DESC_OFFSET_ERR):
1170 rte_bbdev_log(ERR, "Block_size_k is out of range (k<40 or k>6144) and queue offset error");
1172 case (DESC_ERR_K_NOT_NORMAL | DESC_ERR_DESC_OFFSET_ERR):
1173 rte_bbdev_log(ERR, "Block_size_k is not a normal value within normal range and queue offset error");
1175 case (DESC_ERR_KPAI_NOT_NORMAL | DESC_ERR_DESC_OFFSET_ERR):
1176 rte_bbdev_log(ERR, "Three_kpai is not a normal value for UL only and queue offset error");
1178 case DESC_ERR_DESC_READ_FAIL:
1179 rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read");
1181 case DESC_ERR_DESC_READ_TIMEOUT:
1182 rte_bbdev_log(ERR, "Descriptor read time-out");
1184 case DESC_ERR_DESC_READ_TLP_POISONED:
1185 rte_bbdev_log(ERR, "Descriptor read TLP poisoned");
1187 case DESC_ERR_CB_READ_FAIL:
1188 rte_bbdev_log(ERR, "Unsuccessful completion for code block");
1190 case DESC_ERR_CB_READ_TIMEOUT:
1191 rte_bbdev_log(ERR, "Code block read time-out");
1193 case DESC_ERR_CB_READ_TLP_POISONED:
1194 rte_bbdev_log(ERR, "Code block read TLP poisoned");
1197 rte_bbdev_log(ERR, "Descriptor error unknown error code %u",
1205 * Set DMA descriptor for encode operation (1 Code Block)
1208 * Pointer to a single encode operation.
1210 * Pointer to DMA descriptor.
1212 * Pointer to pointer to input data which will be decoded.
1214 * K value (length of input in bits).
1216 * E value (length of output in bits).
1218 * Ncb value (size of the soft buffer).
1220 * Length of output buffer
1222 * Input offset in rte_mbuf structure. It is used for calculating the point
1223 * where data is starting.
1225 * Output offset in rte_mbuf structure. It is used for calculating the point
1226 * where hard output data will be stored.
1228 * Number of CBs contained in one operation.
1231 fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,
1232 struct fpga_dma_enc_desc *desc, struct rte_mbuf *input,
1233 struct rte_mbuf *output, uint16_t k, uint16_t e, uint16_t ncb,
1234 uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
1240 desc->crc_en = check_bit(op->turbo_enc.op_flags,
1241 RTE_BBDEV_TURBO_CRC_24B_ATTACH);
1242 desc->bypass_rm = !check_bit(op->turbo_enc.op_flags,
1243 RTE_BBDEV_TURBO_RATE_MATCH);
1247 desc->rv = op->turbo_enc.rv_index;
1248 desc->offset = desc_offset;
1249 /* Set inbound data buffer address */
1250 desc->in_addr_hi = (uint32_t)(
1251 rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
1252 desc->in_addr_lw = (uint32_t)(
1253 rte_pktmbuf_mtophys_offset(input, in_offset));
1255 desc->out_addr_hi = (uint32_t)(
1256 rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
1257 desc->out_addr_lw = (uint32_t)(
1258 rte_pktmbuf_mtophys_offset(output, out_offset));
1260 /* Save software context needed for dequeue */
1263 /* Set total number of CBs in an op */
1264 desc->cbs_in_op = cbs_in_op;
1270 * Set DMA descriptor for encode operation (1 Code Block)
1273 * Pointer to a single encode operation.
1275 * Pointer to DMA descriptor.
1277 * Pointer to pointer to input data which will be decoded.
1279 * Length of an input.
1281 * K value (length of an output in bits).
1283 * Input offset in rte_mbuf structure. It is used for calculating the point
1284 * where data is starting.
1286 * Output offset in rte_mbuf structure. It is used for calculating the point
1287 * where hard output data will be stored.
1289 * Number of CBs contained in one operation.
1292 fpga_dma_desc_td_fill(struct rte_bbdev_dec_op *op,
1293 struct fpga_dma_dec_desc *desc, struct rte_mbuf *input,
1294 struct rte_mbuf *output, uint16_t in_length, uint16_t k,
1295 uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
1300 /* Set inbound data buffer address */
1301 desc->in_addr_hi = (uint32_t)(
1302 rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
1303 desc->in_addr_lw = (uint32_t)(
1304 rte_pktmbuf_mtophys_offset(input, in_offset));
1305 desc->in_len = in_length;
1307 desc->crc_type = !check_bit(op->turbo_dec.op_flags,
1308 RTE_BBDEV_TURBO_CRC_TYPE_24B);
1309 if ((op->turbo_dec.code_block_mode == 0)
1310 && !check_bit(op->turbo_dec.op_flags,
1311 RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP))
1313 desc->max_iter = op->turbo_dec.iter_max * 2;
1314 desc->offset = desc_offset;
1315 desc->out_addr_hi = (uint32_t)(
1316 rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
1317 desc->out_addr_lw = (uint32_t)(
1318 rte_pktmbuf_mtophys_offset(output, out_offset));
1320 /* Save software context needed for dequeue */
1323 /* Set total number of CBs in an op */
1324 desc->cbs_in_op = cbs_in_op;
1329 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1330 /* Validates turbo encoder parameters */
1332 validate_enc_op(struct rte_bbdev_enc_op *op)
1334 struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
1335 struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
1336 struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
1337 uint16_t kw, kw_neg, kw_pos;
1339 if (turbo_enc->input.length >
1340 RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) {
1341 rte_bbdev_log(ERR, "TB size (%u) is too big, max: %d",
1342 turbo_enc->input.length,
1343 RTE_BBDEV_TURBO_MAX_TB_SIZE);
1344 op->status = 1 << RTE_BBDEV_DATA_ERROR;
1348 if (op->mempool == NULL) {
1349 rte_bbdev_log(ERR, "Invalid mempool pointer");
1352 if (turbo_enc->input.data == NULL) {
1353 rte_bbdev_log(ERR, "Invalid input pointer");
1356 if (turbo_enc->output.data == NULL) {
1357 rte_bbdev_log(ERR, "Invalid output pointer");
1360 if (turbo_enc->rv_index > 3) {
1362 "rv_index (%u) is out of range 0 <= value <= 3",
1363 turbo_enc->rv_index);
1366 if (turbo_enc->code_block_mode != 0 &&
1367 turbo_enc->code_block_mode != 1) {
1369 "code_block_mode (%u) is out of range 0 <= value <= 1",
1370 turbo_enc->code_block_mode);
1374 if (turbo_enc->code_block_mode == 0) {
1375 tb = &turbo_enc->tb_params;
1376 if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE
1377 || tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)
1380 "k_neg (%u) is out of range %u <= value <= %u",
1381 tb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1382 RTE_BBDEV_TURBO_MAX_CB_SIZE);
1385 if (tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE
1386 || tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE) {
1388 "k_pos (%u) is out of range %u <= value <= %u",
1389 tb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1390 RTE_BBDEV_TURBO_MAX_CB_SIZE);
1393 if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))
1395 "c_neg (%u) is out of range 0 <= value <= %u",
1397 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1);
1398 if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {
1400 "c (%u) is out of range 1 <= value <= %u",
1401 tb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);
1404 if (tb->cab > tb->c) {
1406 "cab (%u) is greater than c (%u)",
1410 if ((tb->ea < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->ea % 2))
1411 && tb->r < tb->cab) {
1413 "ea (%u) is less than %u or it is not even",
1414 tb->ea, RTE_BBDEV_TURBO_MIN_CB_SIZE);
1417 if ((tb->eb < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->eb % 2))
1418 && tb->c > tb->cab) {
1420 "eb (%u) is less than %u or it is not even",
1421 tb->eb, RTE_BBDEV_TURBO_MIN_CB_SIZE);
1425 kw_neg = 3 * RTE_ALIGN_CEIL(tb->k_neg + 4,
1426 RTE_BBDEV_TURBO_C_SUBBLOCK);
1427 if (tb->ncb_neg < tb->k_neg || tb->ncb_neg > kw_neg) {
1429 "ncb_neg (%u) is out of range (%u) k_neg <= value <= (%u) kw_neg",
1430 tb->ncb_neg, tb->k_neg, kw_neg);
1434 kw_pos = 3 * RTE_ALIGN_CEIL(tb->k_pos + 4,
1435 RTE_BBDEV_TURBO_C_SUBBLOCK);
1436 if (tb->ncb_pos < tb->k_pos || tb->ncb_pos > kw_pos) {
1438 "ncb_pos (%u) is out of range (%u) k_pos <= value <= (%u) kw_pos",
1439 tb->ncb_pos, tb->k_pos, kw_pos);
1442 if (tb->r > (tb->c - 1)) {
1444 "r (%u) is greater than c - 1 (%u)",
1449 cb = &turbo_enc->cb_params;
1450 if (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE
1451 || cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {
1453 "k (%u) is out of range %u <= value <= %u",
1454 cb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1455 RTE_BBDEV_TURBO_MAX_CB_SIZE);
1459 if (cb->e < RTE_BBDEV_TURBO_MIN_CB_SIZE || (cb->e % 2)) {
1461 "e (%u) is less than %u or it is not even",
1462 cb->e, RTE_BBDEV_TURBO_MIN_CB_SIZE);
1466 kw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_TURBO_C_SUBBLOCK) * 3;
1467 if (cb->ncb < cb->k || cb->ncb > kw) {
1469 "ncb (%u) is out of range (%u) k <= value <= (%u) kw",
1470 cb->ncb, cb->k, kw);
1479 static inline char *
1480 mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
1482 if (unlikely(len > rte_pktmbuf_tailroom(m)))
1485 char *tail = (char *)m->buf_addr + m->data_off + m->data_len;
1486 m->data_len = (uint16_t)(m->data_len + len);
1487 m_head->pkt_len = (m_head->pkt_len + len);
1492 enqueue_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
1493 uint16_t desc_offset)
1495 union fpga_dma_desc *desc;
1496 struct rte_mbuf *input;
1497 struct rte_mbuf *output;
1499 uint16_t k, e, ncb, ring_offset;
1500 uint32_t total_left, in_length, out_length, in_offset, out_offset;
1502 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1503 /* Validate op structure */
1504 if (validate_enc_op(op) == -1) {
1505 rte_bbdev_log(ERR, "Turbo encoder validation failed");
1510 input = op->turbo_enc.input.data;
1511 output = op->turbo_enc.output.data;
1512 in_offset = op->turbo_enc.input.offset;
1513 out_offset = op->turbo_enc.output.offset;
1514 total_left = op->turbo_enc.input.length;
1515 k = op->turbo_enc.cb_params.k;
1516 e = op->turbo_enc.cb_params.e;
1517 ncb = op->turbo_enc.cb_params.ncb;
1519 if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_CRC_24B_ATTACH))
1520 in_length = ((k - 24) >> 3);
1524 if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_RATE_MATCH))
1525 out_length = (e + 7) >> 3;
1527 out_length = (k >> 3) * 3 + 2;
1529 mbuf_append(output, output, out_length);
1531 /* Offset into the ring */
1532 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1533 /* Setup DMA Descriptor */
1534 desc = q->ring_addr + ring_offset;
1536 ret = fpga_dma_desc_te_fill(op, &desc->enc_req, input, output, k, e,
1537 ncb, in_offset, out_offset, ring_offset, 1);
1538 if (unlikely(ret < 0))
1541 /* Update lengths */
1542 total_left -= in_length;
1543 op->turbo_enc.output.length += out_length;
1545 if (total_left > 0) {
1547 "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
1548 total_left, in_length);
1556 enqueue_enc_one_op_tb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
1557 uint16_t desc_offset, uint8_t cbs_in_op)
1559 union fpga_dma_desc *desc;
1560 struct rte_mbuf *input, *output_head, *output;
1562 uint8_t r, c, crc24_bits = 0;
1563 uint16_t k, e, ncb, ring_offset;
1564 uint32_t mbuf_total_left, in_length, out_length, in_offset, out_offset;
1565 uint32_t seg_total_left;
1566 uint16_t current_enqueued_cbs = 0;
1568 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1569 /* Validate op structure */
1570 if (validate_enc_op(op) == -1) {
1571 rte_bbdev_log(ERR, "Turbo encoder validation failed");
1576 input = op->turbo_enc.input.data;
1577 output_head = output = op->turbo_enc.output.data;
1578 in_offset = op->turbo_enc.input.offset;
1579 out_offset = op->turbo_enc.output.offset;
1580 mbuf_total_left = op->turbo_enc.input.length;
1582 c = op->turbo_enc.tb_params.c;
1583 r = op->turbo_enc.tb_params.r;
1585 if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_CRC_24B_ATTACH))
1588 while (mbuf_total_left > 0 && r < c && input != NULL) {
1589 seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
1591 e = (r < op->turbo_enc.tb_params.cab) ?
1592 op->turbo_enc.tb_params.ea :
1593 op->turbo_enc.tb_params.eb;
1594 k = (r < op->turbo_enc.tb_params.c_neg) ?
1595 op->turbo_enc.tb_params.k_neg :
1596 op->turbo_enc.tb_params.k_pos;
1597 ncb = (r < op->turbo_enc.tb_params.c_neg) ?
1598 op->turbo_enc.tb_params.ncb_neg :
1599 op->turbo_enc.tb_params.ncb_pos;
1601 in_length = ((k - crc24_bits) >> 3);
1603 if (check_bit(op->turbo_enc.op_flags,
1604 RTE_BBDEV_TURBO_RATE_MATCH))
1605 out_length = (e + 7) >> 3;
1607 out_length = (k >> 3) * 3 + 2;
1609 mbuf_append(output_head, output, out_length);
1611 /* Setup DMA Descriptor */
1612 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1613 desc = q->ring_addr + ring_offset;
1614 ret = fpga_dma_desc_te_fill(op, &desc->enc_req, input, output,
1615 k, e, ncb, in_offset, out_offset, ring_offset,
1617 if (unlikely(ret < 0))
1620 rte_bbdev_log_debug("DMA request desc %p", desc);
1622 /* Update lengths */
1623 op->turbo_enc.output.length += out_length;
1624 mbuf_total_left -= in_length;
1626 /* Update offsets */
1627 if (seg_total_left == in_length) {
1628 /* Go to the next mbuf */
1629 input = input->next;
1630 output = output->next;
1634 in_offset += in_length;
1635 out_offset += out_length;
1640 current_enqueued_cbs++;
1643 if (mbuf_total_left > 0) {
1645 "Some date still left for processing: mbuf_total_left = %u",
1650 return current_enqueued_cbs;
1653 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1654 /* Validates turbo decoder parameters */
1656 validate_dec_op(struct rte_bbdev_dec_op *op)
1658 struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
1659 struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
1660 struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
1662 if (op->mempool == NULL) {
1663 rte_bbdev_log(ERR, "Invalid mempool pointer");
1666 if (turbo_dec->input.data == NULL) {
1667 rte_bbdev_log(ERR, "Invalid input pointer");
1670 if (turbo_dec->hard_output.data == NULL) {
1671 rte_bbdev_log(ERR, "Invalid hard_output pointer");
1674 if (turbo_dec->rv_index > 3) {
1676 "rv_index (%u) is out of range 0 <= value <= 3",
1677 turbo_dec->rv_index);
1680 if (turbo_dec->iter_min < 1) {
1682 "iter_min (%u) is less than 1",
1683 turbo_dec->iter_min);
1686 if (turbo_dec->iter_max <= 2) {
1688 "iter_max (%u) is less than or equal to 2",
1689 turbo_dec->iter_max);
1692 if (turbo_dec->iter_min > turbo_dec->iter_max) {
1694 "iter_min (%u) is greater than iter_max (%u)",
1695 turbo_dec->iter_min, turbo_dec->iter_max);
1698 if (turbo_dec->code_block_mode != 0 &&
1699 turbo_dec->code_block_mode != 1) {
1701 "code_block_mode (%u) is out of range 0 <= value <= 1",
1702 turbo_dec->code_block_mode);
1706 if (turbo_dec->code_block_mode == 0) {
1708 if ((turbo_dec->op_flags &
1709 RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) &&
1710 !(turbo_dec->op_flags & RTE_BBDEV_TURBO_CRC_TYPE_24B)) {
1712 "RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP should accompany RTE_BBDEV_TURBO_CRC_TYPE_24B");
1716 tb = &turbo_dec->tb_params;
1717 if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE
1718 || tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)
1721 "k_neg (%u) is out of range %u <= value <= %u",
1722 tb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1723 RTE_BBDEV_TURBO_MAX_CB_SIZE);
1726 if ((tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE
1727 || tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE)
1728 && tb->c > tb->c_neg) {
1730 "k_pos (%u) is out of range %u <= value <= %u",
1731 tb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1732 RTE_BBDEV_TURBO_MAX_CB_SIZE);
1735 if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))
1737 "c_neg (%u) is out of range 0 <= value <= %u",
1739 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1);
1740 if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {
1742 "c (%u) is out of range 1 <= value <= %u",
1743 tb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);
1746 if (tb->cab > tb->c) {
1748 "cab (%u) is greater than c (%u)",
1754 if (turbo_dec->op_flags & RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) {
1756 "RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP is invalid in CB-mode");
1760 cb = &turbo_dec->cb_params;
1761 if (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE
1762 || cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {
1764 "k (%u) is out of range %u <= value <= %u",
1765 cb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1766 RTE_BBDEV_TURBO_MAX_CB_SIZE);
1776 enqueue_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
1777 uint16_t desc_offset)
1779 union fpga_dma_desc *desc;
1780 struct rte_mbuf *input;
1781 struct rte_mbuf *output;
1783 uint16_t k, kw, ring_offset;
1784 uint32_t total_left, in_length, out_length, in_offset, out_offset;
1786 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1787 /* Validate op structure */
1788 if (validate_dec_op(op) == -1) {
1789 rte_bbdev_log(ERR, "Turbo decoder validation failed");
1794 input = op->turbo_dec.input.data;
1795 output = op->turbo_dec.hard_output.data;
1796 total_left = op->turbo_dec.input.length;
1797 in_offset = op->turbo_dec.input.offset;
1798 out_offset = op->turbo_dec.hard_output.offset;
1800 k = op->turbo_dec.cb_params.k;
1801 kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
1803 out_length = k >> 3;
1805 mbuf_append(output, output, out_length);
1807 /* Setup DMA Descriptor */
1808 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1809 desc = q->ring_addr + ring_offset;
1810 ret = fpga_dma_desc_td_fill(op, &desc->dec_req, input, output,
1811 in_length, k, in_offset, out_offset, ring_offset, 1);
1812 if (unlikely(ret < 0))
1815 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1816 print_dma_dec_desc_debug_info(desc);
1819 /* Update lengths */
1820 total_left -= in_length;
1821 op->turbo_dec.hard_output.length += out_length;
1823 if (total_left > 0) {
1825 "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
1826 total_left, in_length);
1835 enqueue_dec_one_op_tb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
1836 uint16_t desc_offset, uint8_t cbs_in_op)
1838 union fpga_dma_desc *desc;
1839 struct rte_mbuf *input, *output_head, *output;
1842 uint16_t k, kw, in_length, out_length, ring_offset;
1843 uint32_t mbuf_total_left, seg_total_left, in_offset, out_offset;
1844 uint16_t current_enqueued_cbs = 0;
1845 uint16_t crc24_overlap = 0;
1847 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1848 /* Validate op structure */
1849 if (validate_dec_op(op) == -1) {
1850 rte_bbdev_log(ERR, "Turbo decoder validation failed");
1855 input = op->turbo_dec.input.data;
1856 output_head = output = op->turbo_dec.hard_output.data;
1857 mbuf_total_left = op->turbo_dec.input.length;
1858 in_offset = op->turbo_dec.input.offset;
1859 out_offset = op->turbo_dec.hard_output.offset;
1861 if (!check_bit(op->turbo_dec.op_flags,
1862 RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP))
1865 c = op->turbo_dec.tb_params.c;
1866 r = op->turbo_dec.tb_params.r;
1868 while (mbuf_total_left > 0 && r < c && input != NULL) {
1869 seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
1870 k = (r < op->turbo_dec.tb_params.c_neg) ?
1871 op->turbo_dec.tb_params.k_neg :
1872 op->turbo_dec.tb_params.k_pos;
1873 kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
1876 out_length = (k - crc24_overlap) >> 3;
1878 mbuf_append(output_head, output, out_length);
1880 if (seg_total_left < in_length) {
1882 "Partial CB found in a TB. FPGA Driver doesn't support scatter-gather operations!");
1886 /* Setup DMA Descriptor */
1887 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1888 desc = q->ring_addr + ring_offset;
1889 ret = fpga_dma_desc_td_fill(op, &desc->dec_req, input, output,
1890 in_length, k, in_offset, out_offset,
1891 ring_offset, cbs_in_op);
1892 if (unlikely(ret < 0))
1895 /* Update lengths */
1896 ret = rte_pktmbuf_trim(op->turbo_dec.hard_output.data,
1897 (crc24_overlap >> 3));
1898 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1901 "The length to remove is greater than the length of the last segment");
1905 op->turbo_dec.hard_output.length += out_length;
1906 mbuf_total_left -= in_length;
1908 /* Update offsets */
1909 if (seg_total_left == in_length) {
1910 /* Go to the next mbuf */
1911 input = input->next;
1912 output = output->next;
1916 in_offset += in_length;
1917 out_offset += out_length;
1922 current_enqueued_cbs++;
1925 if (mbuf_total_left > 0) {
1927 "Some date still left for processing: mbuf_total_left = %u",
1932 return current_enqueued_cbs;
1936 fpga_enqueue_enc(struct rte_bbdev_queue_data *q_data,
1937 struct rte_bbdev_enc_op **ops, uint16_t num)
1940 uint16_t i, total_enqueued_cbs = 0;
1943 struct fpga_queue *q = q_data->queue_private;
1944 union fpga_dma_desc *desc;
1946 /* Check if queue is not full */
1947 if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
1951 /* Calculates available space */
1952 avail = (q->head_free_desc > q->tail) ?
1953 q->head_free_desc - q->tail - 1 :
1954 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
1956 for (i = 0; i < num; ++i) {
1957 if (ops[i]->turbo_enc.code_block_mode == 0) {
1958 cbs_in_op = get_num_cbs_in_op_enc(&ops[i]->turbo_enc);
1959 /* Check if there is available space for further
1962 if (unlikely(avail - cbs_in_op < 0))
1965 enqueued_cbs = enqueue_enc_one_op_tb(q, ops[i],
1966 total_enqueued_cbs, cbs_in_op);
1968 /* Check if there is available space for further
1971 if (unlikely(avail - 1 < 0))
1974 enqueued_cbs = enqueue_enc_one_op_cb(q, ops[i],
1975 total_enqueued_cbs);
1978 if (enqueued_cbs < 0)
1981 total_enqueued_cbs += enqueued_cbs;
1983 rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d",
1984 total_enqueued_cbs, num,
1985 q->head_free_desc, q->tail);
1988 /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
1989 * only when all previous CBs were already processed.
1991 desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
1992 & q->sw_ring_wrap_mask);
1993 desc->enc_req.irq_en = q->irq_enable;
1995 fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
1998 q_data->queue_stats.enqueued_count += i;
1999 q_data->queue_stats.enqueue_err_count += num - i;
2005 fpga_enqueue_dec(struct rte_bbdev_queue_data *q_data,
2006 struct rte_bbdev_dec_op **ops, uint16_t num)
2009 uint16_t i, total_enqueued_cbs = 0;
2012 struct fpga_queue *q = q_data->queue_private;
2013 union fpga_dma_desc *desc;
2015 /* Check if queue is not full */
2016 if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
2020 /* Calculates available space */
2021 avail = (q->head_free_desc > q->tail) ?
2022 q->head_free_desc - q->tail - 1 :
2023 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
2025 for (i = 0; i < num; ++i) {
2026 if (ops[i]->turbo_dec.code_block_mode == 0) {
2027 cbs_in_op = get_num_cbs_in_op_dec(&ops[i]->turbo_dec);
2028 /* Check if there is available space for further
2031 if (unlikely(avail - cbs_in_op < 0))
2034 enqueued_cbs = enqueue_dec_one_op_tb(q, ops[i],
2035 total_enqueued_cbs, cbs_in_op);
2037 /* Check if there is available space for further
2040 if (unlikely(avail - 1 < 0))
2043 enqueued_cbs = enqueue_dec_one_op_cb(q, ops[i],
2044 total_enqueued_cbs);
2047 if (enqueued_cbs < 0)
2050 total_enqueued_cbs += enqueued_cbs;
2052 rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d",
2053 total_enqueued_cbs, num,
2054 q->head_free_desc, q->tail);
2057 /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
2058 * only when all previous CBs were already processed.
2060 desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
2061 & q->sw_ring_wrap_mask);
2062 desc->dec_req.irq_en = q->irq_enable;
2064 fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
2067 q_data->queue_stats.enqueued_count += i;
2068 q_data->queue_stats.enqueue_err_count += num - i;
2074 dequeue_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,
2075 uint16_t desc_offset)
2077 union fpga_dma_desc *desc;
2080 /* Set current desc */
2081 desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2082 & q->sw_ring_wrap_mask);
2085 if (desc->enc_req.done == 0)
2088 /* make sure the response is read atomically */
2091 rte_bbdev_log_debug("DMA response desc %p", desc);
2093 *op = desc->enc_req.op_addr;
2094 /* Check the decriptor error field, return 1 on error */
2095 desc_error = check_desc_error(desc->enc_req.error);
2096 (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
2102 dequeue_enc_one_op_tb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,
2103 uint16_t desc_offset)
2105 union fpga_dma_desc *desc;
2106 uint8_t cbs_in_op, cb_idx;
2110 /* Set descriptor */
2111 desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2112 & q->sw_ring_wrap_mask);
2114 /* Verify if done bit is set */
2115 if (desc->enc_req.done == 0)
2118 /* Make sure the response is read atomically */
2121 /* Verify if done bit in all CBs is set */
2122 cbs_in_op = desc->enc_req.cbs_in_op;
2123 for (cb_idx = 1; cb_idx < cbs_in_op; ++cb_idx) {
2124 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2125 cb_idx) & q->sw_ring_wrap_mask);
2126 if (desc->enc_req.done == 0)
2130 /* Make sure the response is read atomically */
2133 for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) {
2134 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2135 cb_idx) & q->sw_ring_wrap_mask);
2136 /* Check the decriptor error field, return 1 on error */
2137 desc_error = check_desc_error(desc->enc_req.error);
2138 status |= desc_error << RTE_BBDEV_DATA_ERROR;
2139 rte_bbdev_log_debug("DMA response desc %p", desc);
2142 *op = desc->enc_req.op_addr;
2143 (*op)->status = status;
2148 dequeue_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
2149 uint16_t desc_offset)
2151 union fpga_dma_desc *desc;
2153 /* Set descriptor */
2154 desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2155 & q->sw_ring_wrap_mask);
2157 /* Verify done bit is set */
2158 if (desc->dec_req.done == 0)
2161 /* make sure the response is read atomically */
2164 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2165 print_dma_dec_desc_debug_info(desc);
2169 *op = desc->dec_req.op_addr;
2170 /* FPGA reports in half-iterations, from 0 to 31. get ceiling */
2171 (*op)->turbo_dec.iter_count = (desc->dec_req.iter + 2) >> 1;
2172 /* crc_pass = 0 when decoder fails */
2173 (*op)->status = !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
2174 /* Check the decriptor error field, return 1 on error */
2175 desc_error = check_desc_error(desc->enc_req.error);
2176 (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
2181 dequeue_dec_one_op_tb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
2182 uint16_t desc_offset)
2184 union fpga_dma_desc *desc;
2185 uint8_t cbs_in_op, cb_idx, iter_count = 0;
2188 /* Set descriptor */
2189 desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2190 & q->sw_ring_wrap_mask);
2192 /* Verify if done bit is set */
2193 if (desc->dec_req.done == 0)
2196 /* Make sure the response is read atomically */
2199 /* Verify if done bit in all CBs is set */
2200 cbs_in_op = desc->dec_req.cbs_in_op;
2201 for (cb_idx = 1; cb_idx < cbs_in_op; ++cb_idx) {
2202 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2203 cb_idx) & q->sw_ring_wrap_mask);
2204 if (desc->dec_req.done == 0)
2208 /* Make sure the response is read atomically */
2211 for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) {
2212 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2213 cb_idx) & q->sw_ring_wrap_mask);
2214 /* get max iter_count for all CBs in op */
2215 iter_count = RTE_MAX(iter_count, (uint8_t) desc->dec_req.iter);
2216 /* crc_pass = 0 when decoder fails, one fails all */
2217 status |= !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
2218 /* Check the decriptor error field, return 1 on error */
2219 desc_error = check_desc_error(desc->enc_req.error);
2220 status |= desc_error << RTE_BBDEV_DATA_ERROR;
2221 rte_bbdev_log_debug("DMA response desc %p", desc);
2224 *op = desc->dec_req.op_addr;
2226 /* FPGA reports in half-iterations, get ceiling */
2227 (*op)->turbo_dec.iter_count = (iter_count + 2) >> 1;
2228 (*op)->status = status;
2233 fpga_dequeue_enc(struct rte_bbdev_queue_data *q_data,
2234 struct rte_bbdev_enc_op **ops, uint16_t num)
2236 struct fpga_queue *q = q_data->queue_private;
2237 uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
2239 uint16_t dequeued_cbs = 0;
2240 struct rte_bbdev_enc_op *op;
2243 for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
2244 op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs)
2245 & q->sw_ring_wrap_mask))->enc_req.op_addr;
2246 if (op->turbo_enc.code_block_mode == 0)
2247 ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs);
2249 ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs);
2254 dequeued_cbs += ret;
2256 rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d",
2257 dequeued_cbs, num, q->head_free_desc, q->tail);
2261 q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
2262 q->sw_ring_wrap_mask;
2265 q_data->queue_stats.dequeued_count += i;
2271 fpga_dequeue_dec(struct rte_bbdev_queue_data *q_data,
2272 struct rte_bbdev_dec_op **ops, uint16_t num)
2274 struct fpga_queue *q = q_data->queue_private;
2275 uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
2277 uint16_t dequeued_cbs = 0;
2278 struct rte_bbdev_dec_op *op;
2281 for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
2282 op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs)
2283 & q->sw_ring_wrap_mask))->dec_req.op_addr;
2284 if (op->turbo_dec.code_block_mode == 0)
2285 ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs);
2287 ret = dequeue_dec_one_op_cb(q, &ops[i], dequeued_cbs);
2292 dequeued_cbs += ret;
2294 rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d",
2295 dequeued_cbs, num, q->head_free_desc, q->tail);
2299 q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
2300 q->sw_ring_wrap_mask;
2303 q_data->queue_stats.dequeued_count += i;
2308 /* Initialization Function */
2310 fpga_lte_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
2312 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2314 dev->dev_ops = &fpga_ops;
2315 dev->enqueue_enc_ops = fpga_enqueue_enc;
2316 dev->enqueue_dec_ops = fpga_enqueue_dec;
2317 dev->dequeue_enc_ops = fpga_dequeue_enc;
2318 dev->dequeue_dec_ops = fpga_dequeue_dec;
2320 ((struct fpga_lte_fec_device *) dev->data->dev_private)->pf_device =
2321 !strcmp(drv->driver.name,
2322 RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME));
2323 ((struct fpga_lte_fec_device *) dev->data->dev_private)->mmio_base =
2324 pci_dev->mem_resource[0].addr;
2326 rte_bbdev_log_debug(
2327 "Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
2328 dev->device->driver->name, dev->data->name,
2329 (void *)pci_dev->mem_resource[0].addr,
2330 pci_dev->mem_resource[0].phys_addr);
2334 fpga_lte_fec_probe(struct rte_pci_driver *pci_drv,
2335 struct rte_pci_device *pci_dev)
2337 struct rte_bbdev *bbdev = NULL;
2338 char dev_name[RTE_BBDEV_NAME_MAX_LEN];
2340 if (pci_dev == NULL) {
2341 rte_bbdev_log(ERR, "NULL PCI device");
2345 rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));
2347 /* Allocate memory to be used privately by drivers */
2348 bbdev = rte_bbdev_allocate(pci_dev->device.name);
2352 /* allocate device private memory */
2353 bbdev->data->dev_private = rte_zmalloc_socket(dev_name,
2354 sizeof(struct fpga_lte_fec_device), RTE_CACHE_LINE_SIZE,
2355 pci_dev->device.numa_node);
2357 if (bbdev->data->dev_private == NULL) {
2359 "Allocate of %zu bytes for device \"%s\" failed",
2360 sizeof(struct fpga_lte_fec_device), dev_name);
2361 rte_bbdev_release(bbdev);
2365 /* Fill HW specific part of device structure */
2366 bbdev->device = &pci_dev->device;
2367 bbdev->intr_handle = &pci_dev->intr_handle;
2368 bbdev->data->socket_id = pci_dev->device.numa_node;
2370 /* Invoke FEC FPGA device initialization function */
2371 fpga_lte_fec_init(bbdev, pci_drv);
2373 rte_bbdev_log_debug("bbdev id = %u [%s]",
2374 bbdev->data->dev_id, dev_name);
2376 struct fpga_lte_fec_device *d = bbdev->data->dev_private;
2377 uint32_t version_id = fpga_reg_read_32(d->mmio_base,
2378 FPGA_LTE_FEC_VERSION_ID);
2379 rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u",
2380 ((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
2382 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2383 if (!strcmp(bbdev->device->driver->name,
2384 RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME)))
2385 print_static_reg_debug_info(d->mmio_base);
2391 fpga_lte_fec_remove(struct rte_pci_device *pci_dev)
2393 struct rte_bbdev *bbdev;
2397 if (pci_dev == NULL)
2401 bbdev = rte_bbdev_get_named_dev(pci_dev->device.name);
2402 if (bbdev == NULL) {
2404 "Couldn't find HW dev \"%s\" to uninitialise it",
2405 pci_dev->device.name);
2408 dev_id = bbdev->data->dev_id;
2410 /* free device private memory before close */
2411 rte_free(bbdev->data->dev_private);
2414 ret = rte_bbdev_close(dev_id);
2417 "Device %i failed to close during uninit: %i",
2420 /* release bbdev from library */
2421 ret = rte_bbdev_release(bbdev);
2423 rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id,
2426 rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id);
2432 set_default_fpga_conf(struct fpga_lte_fec_conf *def_conf)
2434 /* clear default configuration before initialization */
2435 memset(def_conf, 0, sizeof(struct fpga_lte_fec_conf));
2436 /* Set pf mode to true */
2437 def_conf->pf_mode_en = true;
2439 /* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */
2440 def_conf->ul_bandwidth = 3;
2441 def_conf->dl_bandwidth = 3;
2443 /* Set Load Balance Factor to 64 */
2444 def_conf->dl_load_balance = 64;
2445 def_conf->ul_load_balance = 64;
2448 /* Initial configuration of FPGA LTE FEC device */
2450 fpga_lte_fec_configure(const char *dev_name,
2451 const struct fpga_lte_fec_conf *conf)
2453 uint32_t payload_32, address;
2454 uint16_t payload_16;
2456 uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;
2457 struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
2458 struct fpga_lte_fec_conf def_conf;
2460 if (bbdev == NULL) {
2462 "Invalid dev_name (%s), or device is not yet initialised",
2467 struct fpga_lte_fec_device *d = bbdev->data->dev_private;
2471 "FPGA Configuration was not provided. Default configuration will be loaded.");
2472 set_default_fpga_conf(&def_conf);
2477 * Configure UL:DL ratio.
2481 payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;
2482 address = FPGA_LTE_FEC_CONFIGURATION;
2483 fpga_reg_write_16(d->mmio_base, address, payload_16);
2485 /* Clear all queues registers */
2486 payload_32 = FPGA_INVALID_HW_QUEUE_ID;
2487 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
2488 address = (q_id << 2) + FPGA_LTE_FEC_QUEUE_MAP;
2489 fpga_reg_write_32(d->mmio_base, address, payload_32);
2493 * If PF mode is enabled allocate all queues for PF only.
2495 * For VF mode each VF can have different number of UL and DL queues.
2496 * Total number of queues to configure cannot exceed FPGA
2497 * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.
2498 * Queues mapping is done according to configuration:
2504 * | conf->vf_dl_queues_number[0] - 1 | 0 |
2505 * | conf->vf_dl_queues_number[0] | 1 |
2507 * | conf->vf_dl_queues_number[1] - 1 | 1 |
2509 * | conf->vf_dl_queues_number[7] - 1 | 7 |
2515 * | conf->vf_ul_queues_number[0] - 1 | 0 |
2516 * | conf->vf_ul_queues_number[0] | 1 |
2518 * | conf->vf_ul_queues_number[1] - 1 | 1 |
2520 * | conf->vf_ul_queues_number[7] - 1 | 7 |
2522 * Example of configuration:
2523 * conf->vf_ul_queues_number[0] = 4; -> 4 UL queues for VF0
2524 * conf->vf_dl_queues_number[0] = 4; -> 4 DL queues for VF0
2525 * conf->vf_ul_queues_number[1] = 2; -> 2 UL queues for VF1
2526 * conf->vf_dl_queues_number[1] = 2; -> 2 DL queues for VF1
2546 if (conf->pf_mode_en) {
2548 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
2549 address = (q_id << 2) + FPGA_LTE_FEC_QUEUE_MAP;
2550 fpga_reg_write_32(d->mmio_base, address, payload_32);
2553 /* Calculate total number of UL and DL queues to configure */
2554 total_ul_q_id = total_dl_q_id = 0;
2555 for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) {
2556 total_ul_q_id += conf->vf_ul_queues_number[vf_id];
2557 total_dl_q_id += conf->vf_dl_queues_number[vf_id];
2559 total_q_id = total_dl_q_id + total_ul_q_id;
2561 * Check if total number of queues to configure does not exceed
2562 * FPGA capabilities (64 queues - 32 UL and 32 DL queues)
2564 if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||
2565 (total_dl_q_id > FPGA_NUM_DL_QUEUES) ||
2566 (total_q_id > FPGA_TOTAL_NUM_QUEUES)) {
2568 "FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u",
2569 total_ul_q_id, total_dl_q_id,
2570 FPGA_TOTAL_NUM_QUEUES);
2574 for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) {
2575 for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];
2576 ++q_id, ++total_ul_q_id) {
2577 address = (total_ul_q_id << 2) +
2578 FPGA_LTE_FEC_QUEUE_MAP;
2579 payload_32 = ((0x80 + vf_id) << 16) | 0x1;
2580 fpga_reg_write_32(d->mmio_base, address,
2585 for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) {
2586 for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];
2587 ++q_id, ++total_dl_q_id) {
2588 address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)
2589 << 2) + FPGA_LTE_FEC_QUEUE_MAP;
2590 payload_32 = ((0x80 + vf_id) << 16) | 0x1;
2591 fpga_reg_write_32(d->mmio_base, address,
2597 /* Setting Load Balance Factor */
2598 payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);
2599 address = FPGA_LTE_FEC_LOAD_BALANCE_FACTOR;
2600 fpga_reg_write_16(d->mmio_base, address, payload_16);
2602 /* Setting length of ring descriptor entry */
2603 payload_16 = FPGA_RING_DESC_ENTRY_LENGTH;
2604 address = FPGA_LTE_FEC_RING_DESC_LEN;
2605 fpga_reg_write_16(d->mmio_base, address, payload_16);
2607 /* Setting FLR timeout value */
2608 payload_16 = conf->flr_time_out;
2609 address = FPGA_LTE_FEC_FLR_TIME_OUT;
2610 fpga_reg_write_16(d->mmio_base, address, payload_16);
2612 /* Queue PF/VF mapping table is ready */
2614 address = FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE;
2615 fpga_reg_write_8(d->mmio_base, address, payload_8);
2617 rte_bbdev_log_debug("PF FPGA LTE FEC configuration complete for %s",
2620 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2621 print_static_reg_debug_info(d->mmio_base);
2626 /* FPGA LTE FEC PCI PF address map */
2627 static struct rte_pci_id pci_id_fpga_lte_fec_pf_map[] = {
2629 RTE_PCI_DEVICE(FPGA_LTE_FEC_VENDOR_ID,
2630 FPGA_LTE_FEC_PF_DEVICE_ID)
2635 static struct rte_pci_driver fpga_lte_fec_pci_pf_driver = {
2636 .probe = fpga_lte_fec_probe,
2637 .remove = fpga_lte_fec_remove,
2638 .id_table = pci_id_fpga_lte_fec_pf_map,
2639 .drv_flags = RTE_PCI_DRV_NEED_MAPPING
2642 /* FPGA LTE FEC PCI VF address map */
2643 static struct rte_pci_id pci_id_fpga_lte_fec_vf_map[] = {
2645 RTE_PCI_DEVICE(FPGA_LTE_FEC_VENDOR_ID,
2646 FPGA_LTE_FEC_VF_DEVICE_ID)
2651 static struct rte_pci_driver fpga_lte_fec_pci_vf_driver = {
2652 .probe = fpga_lte_fec_probe,
2653 .remove = fpga_lte_fec_remove,
2654 .id_table = pci_id_fpga_lte_fec_vf_map,
2655 .drv_flags = RTE_PCI_DRV_NEED_MAPPING
2659 RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_PF_DRIVER_NAME, fpga_lte_fec_pci_pf_driver);
2660 RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_PF_DRIVER_NAME,
2661 pci_id_fpga_lte_fec_pf_map);
2662 RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_VF_DRIVER_NAME, fpga_lte_fec_pci_vf_driver);
2663 RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_VF_DRIVER_NAME,
2664 pci_id_fpga_lte_fec_vf_map);
2666 RTE_INIT(fpga_lte_fec_init_log)
2668 fpga_lte_fec_logtype = rte_log_register("pmd.bb.fpga_lte_fec");
2669 if (fpga_lte_fec_logtype >= 0)
2670 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2671 rte_log_set_level(fpga_lte_fec_logtype, RTE_LOG_DEBUG);
2673 rte_log_set_level(fpga_lte_fec_logtype, RTE_LOG_NOTICE);