drivers/baseband/fpga_lte_fec/fpga_lte_fec.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include <unistd.h>
   6
   7 #include <rte_common.h>
   8 #include <rte_log.h>
   9 #include <rte_dev.h>
  10 #include <rte_malloc.h>
  11 #include <rte_mempool.h>
  12 #include <rte_errno.h>
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_byteorder.h>
  16 #ifdef RTE_BBDEV_OFFLOAD_COST
  17 #include <rte_cycles.h>
  18 #endif
  19
  20 #include <rte_bbdev.h>
  21 #include <rte_bbdev_pmd.h>
  22
  23 #include "fpga_lte_fec.h"
  24
  25 #ifdef RTE_LIBRTE_BBDEV_DEBUG
  26 RTE_LOG_REGISTER_DEFAULT(fpga_lte_fec_logtype, DEBUG);
  27 #else
  28 RTE_LOG_REGISTER_DEFAULT(fpga_lte_fec_logtype, NOTICE);
  29 #endif
  30
  31 /* Helper macro for logging */
  32 #define rte_bbdev_log(level, fmt, ...) \
  33         rte_log(RTE_LOG_ ## level, fpga_lte_fec_logtype, fmt "\n", \
  34                 ##__VA_ARGS__)
  35
  36 #ifdef RTE_LIBRTE_BBDEV_DEBUG
  37 #define rte_bbdev_log_debug(fmt, ...) \
  38                 rte_bbdev_log(DEBUG, "fpga_lte_fec: " fmt, \
  39                 ##__VA_ARGS__)
  40 #else
  41 #define rte_bbdev_log_debug(fmt, ...)
  42 #endif
  43
  44 /* FPGA LTE FEC driver names */
  45 #define FPGA_LTE_FEC_PF_DRIVER_NAME intel_fpga_lte_fec_pf
  46 #define FPGA_LTE_FEC_VF_DRIVER_NAME intel_fpga_lte_fec_vf
  47
  48 /* FPGA LTE FEC PCI vendor & device IDs */
  49 #define FPGA_LTE_FEC_VENDOR_ID (0x1172)
  50 #define FPGA_LTE_FEC_PF_DEVICE_ID (0x5052)
  51 #define FPGA_LTE_FEC_VF_DEVICE_ID (0x5050)
  52
  53 /* Align DMA descriptors to 256 bytes - cache-aligned */
  54 #define FPGA_RING_DESC_ENTRY_LENGTH (8)
  55 /* Ring size is in 256 bits (32 bytes) units */
  56 #define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
  57 /* Maximum size of queue */
  58 #define FPGA_RING_MAX_SIZE (1024)
  59 #define FPGA_FLR_TIMEOUT_UNIT (16.384)
  60
  61 #define FPGA_NUM_UL_QUEUES (32)
  62 #define FPGA_NUM_DL_QUEUES (32)
  63 #define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)
  64 #define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)
  65
  66 #define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)
  67
  68 #define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)
  69 #define FPGA_TIMEOUT_CHECK_INTERVAL (5)
  70
  71 /* FPGA LTE FEC Register mapping on BAR0 */
  72 enum {
  73         FPGA_LTE_FEC_VERSION_ID = 0x00000000, /* len: 4B */
  74         FPGA_LTE_FEC_CONFIGURATION = 0x00000004, /* len: 2B */
  75         FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
  76         FPGA_LTE_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
  77         FPGA_LTE_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
  78         FPGA_LTE_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
  79         FPGA_LTE_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
  80         FPGA_LTE_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
  81         FPGA_LTE_FEC_VF0_DEBUG = 0x00000020, /* len: 4B */
  82         FPGA_LTE_FEC_VF1_DEBUG = 0x00000024, /* len: 4B */
  83         FPGA_LTE_FEC_VF2_DEBUG = 0x00000028, /* len: 4B */
  84         FPGA_LTE_FEC_VF3_DEBUG = 0x0000002c, /* len: 4B */
  85         FPGA_LTE_FEC_VF4_DEBUG = 0x00000030, /* len: 4B */
  86         FPGA_LTE_FEC_VF5_DEBUG = 0x00000034, /* len: 4B */
  87         FPGA_LTE_FEC_VF6_DEBUG = 0x00000038, /* len: 4B */
  88         FPGA_LTE_FEC_VF7_DEBUG = 0x0000003c, /* len: 4B */
  89         FPGA_LTE_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */
  90         FPGA_LTE_FEC_RING_CTRL_REGS = 0x00000200  /* len: 2048B */
  91 };
  92
  93 /* FPGA LTE FEC Ring Control Registers */
  94 enum {
  95         FPGA_LTE_FEC_RING_HEAD_ADDR = 0x00000008,
  96         FPGA_LTE_FEC_RING_SIZE = 0x00000010,
  97         FPGA_LTE_FEC_RING_MISC = 0x00000014,
  98         FPGA_LTE_FEC_RING_ENABLE = 0x00000015,
  99         FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,
 100         FPGA_LTE_FEC_RING_SHADOW_TAIL = 0x00000018,
 101         FPGA_LTE_FEC_RING_HEAD_POINT = 0x0000001C
 102 };
 103
 104 /* FPGA LTE FEC DESCRIPTOR ERROR */
 105 enum {
 106         DESC_ERR_NO_ERR = 0x0,
 107         DESC_ERR_K_OUT_OF_RANGE = 0x1,
 108         DESC_ERR_K_NOT_NORMAL = 0x2,
 109         DESC_ERR_KPAI_NOT_NORMAL = 0x3,
 110         DESC_ERR_DESC_OFFSET_ERR = 0x4,
 111         DESC_ERR_DESC_READ_FAIL = 0x8,
 112         DESC_ERR_DESC_READ_TIMEOUT = 0x9,
 113         DESC_ERR_DESC_READ_TLP_POISONED = 0xA,
 114         DESC_ERR_CB_READ_FAIL = 0xC,
 115         DESC_ERR_CB_READ_TIMEOUT = 0xD,
 116         DESC_ERR_CB_READ_TLP_POISONED = 0xE
 117 };
 118
 119 /* FPGA LTE FEC DMA Encoding Request Descriptor */
 120 struct __rte_packed fpga_dma_enc_desc {
 121         uint32_t done:1,
 122                 rsrvd0:11,
 123                 error:4,
 124                 rsrvd1:16;
 125         uint32_t ncb:16,
 126                 rsrvd2:14,
 127                 rv:2;
 128         uint32_t bypass_rm:1,
 129                 irq_en:1,
 130                 crc_en:1,
 131                 rsrvd3:13,
 132                 offset:10,
 133                 rsrvd4:6;
 134         uint16_t e;
 135         uint16_t k;
 136         uint32_t out_addr_lw;
 137         uint32_t out_addr_hi;
 138         uint32_t in_addr_lw;
 139         uint32_t in_addr_hi;
 140
 141         union {
 142                 struct {
 143                         /* Virtual addresses used to retrieve SW context info */
 144                         void *op_addr;
 145                         /* Stores information about total number of Code Blocks
 146                          * in currently processed Transport Block
 147                          */
 148                         uint64_t cbs_in_op;
 149                 };
 150
 151                 uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
 152                                         (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
 153         };
 154 };
 155
 156 /* FPGA LTE FEC DMA Decoding Request Descriptor */
 157 struct __rte_packed fpga_dma_dec_desc {
 158         uint32_t done:1,
 159                 iter:5,
 160                 rsrvd0:2,
 161                 crc_pass:1,
 162                 rsrvd1:3,
 163                 error:4,
 164                 crc_type:1,
 165                 rsrvd2:7,
 166                 max_iter:5,
 167                 rsrvd3:3;
 168         uint32_t rsrvd4;
 169         uint32_t bypass_rm:1,
 170                 irq_en:1,
 171                 drop_crc:1,
 172                 rsrvd5:13,
 173                 offset:10,
 174                 rsrvd6:6;
 175         uint16_t k;
 176         uint16_t in_len;
 177         uint32_t out_addr_lw;
 178         uint32_t out_addr_hi;
 179         uint32_t in_addr_lw;
 180         uint32_t in_addr_hi;
 181
 182         union {
 183                 struct {
 184                         /* Virtual addresses used to retrieve SW context info */
 185                         void *op_addr;
 186                         /* Stores information about total number of Code Blocks
 187                          * in currently processed Transport Block
 188                          */
 189                         uint8_t cbs_in_op;
 190                 };
 191
 192                 uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
 193         };
 194 };
 195
 196 /* FPGA LTE DMA Descriptor */
 197 union fpga_dma_desc {
 198         struct fpga_dma_enc_desc enc_req;
 199         struct fpga_dma_dec_desc dec_req;
 200 };
 201
 202 /* FPGA LTE FEC Ring Control Register */
 203 struct __rte_packed fpga_ring_ctrl_reg {
 204         uint64_t ring_base_addr;
 205         uint64_t ring_head_addr;
 206         uint16_t ring_size:11;
 207         uint16_t rsrvd0;
 208         union { /* Miscellaneous register */
 209                 uint8_t misc;
 210                 uint8_t max_ul_dec:5,
 211                         max_ul_dec_en:1,
 212                         rsrvd1:2;
 213         };
 214         uint8_t enable;
 215         uint8_t flush_queue_en;
 216         uint8_t rsrvd2;
 217         uint16_t shadow_tail;
 218         uint16_t rsrvd3;
 219         uint16_t head_point;
 220         uint16_t rsrvd4;
 221
 222 };
 223
 224 /* Private data structure for each FPGA FEC device */
 225 struct fpga_lte_fec_device {
 226         /** Base address of MMIO registers (BAR0) */
 227         void *mmio_base;
 228         /** Base address of memory for sw rings */
 229         void *sw_rings;
 230         /** Physical address of sw_rings */
 231         rte_iova_t sw_rings_phys;
 232         /** Number of bytes available for each queue in device. */
 233         uint32_t sw_ring_size;
 234         /** Max number of entries available for each queue in device */
 235         uint32_t sw_ring_max_depth;
 236         /** Base address of response tail pointer buffer */
 237         uint32_t *tail_ptrs;
 238         /** Physical address of tail pointers */
 239         rte_iova_t tail_ptr_phys;
 240         /** Queues flush completion flag */
 241         uint64_t *flush_queue_status;
 242         /* Bitmap capturing which Queues are bound to the PF/VF */
 243         uint64_t q_bound_bit_map;
 244         /* Bitmap capturing which Queues have already been assigned */
 245         uint64_t q_assigned_bit_map;
 246         /** True if this is a PF FPGA FEC device */
 247         bool pf_device;
 248 };
 249
 250 /* Structure associated with each queue. */
 251 struct __rte_cache_aligned fpga_queue {
 252         struct fpga_ring_ctrl_reg ring_ctrl_reg;  /* Ring Control Register */
 253         union fpga_dma_desc *ring_addr;  /* Virtual address of software ring */
 254         uint64_t *ring_head_addr;  /* Virtual address of completion_head */
 255         uint64_t shadow_completion_head; /* Shadow completion head value */
 256         uint16_t head_free_desc;  /* Ring head */
 257         uint16_t tail;  /* Ring tail */
 258         /* Mask used to wrap enqueued descriptors on the sw ring */
 259         uint32_t sw_ring_wrap_mask;
 260         uint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */
 261         uint8_t q_idx;  /* Queue index */
 262         struct fpga_lte_fec_device *d;
 263         /* MMIO register of shadow_tail used to enqueue descriptors */
 264         void *shadow_tail_addr;
 265 };
 266
 267 /* Write to 16 bit MMIO register address */
 268 static inline void
 269 mmio_write_16(void *addr, uint16_t value)
 270 {
 271         *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);
 272 }
 273
 274 /* Write to 32 bit MMIO register address */
 275 static inline void
 276 mmio_write_32(void *addr, uint32_t value)
 277 {
 278         *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
 279 }
 280
 281 /* Write to 64 bit MMIO register address */
 282 static inline void
 283 mmio_write_64(void *addr, uint64_t value)
 284 {
 285         *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);
 286 }
 287
 288 /* Write a 8 bit register of a FPGA LTE FEC device */
 289 static inline void
 290 fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)
 291 {
 292         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 293         *((volatile uint8_t *)(reg_addr)) = payload;
 294 }
 295
 296 /* Write a 16 bit register of a FPGA LTE FEC device */
 297 static inline void
 298 fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)
 299 {
 300         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 301         mmio_write_16(reg_addr, payload);
 302 }
 303
 304 /* Write a 32 bit register of a FPGA LTE FEC device */
 305 static inline void
 306 fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)
 307 {
 308         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 309         mmio_write_32(reg_addr, payload);
 310 }
 311
 312 /* Write a 64 bit register of a FPGA LTE FEC device */
 313 static inline void
 314 fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)
 315 {
 316         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 317         mmio_write_64(reg_addr, payload);
 318 }
 319
 320 /* Write a ring control register of a FPGA LTE FEC device */
 321 static inline void
 322 fpga_ring_reg_write(void *mmio_base, uint32_t offset,
 323                 struct fpga_ring_ctrl_reg payload)
 324 {
 325         fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);
 326         fpga_reg_write_64(mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_ADDR,
 327                         payload.ring_head_addr);
 328         fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_SIZE,
 329                         payload.ring_size);
 330         fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_POINT,
 331                         payload.head_point);
 332         fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN,
 333                         payload.flush_queue_en);
 334         fpga_reg_write_16(mmio_base, offset + FPGA_LTE_FEC_RING_SHADOW_TAIL,
 335                         payload.shadow_tail);
 336         fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_MISC,
 337                         payload.misc);
 338         fpga_reg_write_8(mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE,
 339                         payload.enable);
 340 }
 341
 342 /* Read a register of FPGA LTE FEC device */
 343 static uint32_t
 344 fpga_reg_read_32(void *mmio_base, uint32_t offset)
 345 {
 346         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 347         uint32_t ret = *((volatile uint32_t *)(reg_addr));
 348         return rte_le_to_cpu_32(ret);
 349 }
 350
 351 #ifdef RTE_LIBRTE_BBDEV_DEBUG
 352 /* Read a register of FPGA LTE FEC device */
 353 static uint8_t
 354 fpga_reg_read_8(void *mmio_base, uint32_t offset)
 355 {
 356         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 357         return *((volatile uint8_t *)(reg_addr));
 358 }
 359
 360 /* Read a register of FPGA LTE FEC device */
 361 static uint16_t
 362 fpga_reg_read_16(void *mmio_base, uint32_t offset)
 363 {
 364         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 365         uint16_t ret = *((volatile uint16_t *)(reg_addr));
 366         return rte_le_to_cpu_16(ret);
 367 }
 368
 369 /* Read a register of FPGA LTE FEC device */
 370 static uint64_t
 371 fpga_reg_read_64(void *mmio_base, uint32_t offset)
 372 {
 373         void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
 374         uint64_t ret = *((volatile uint64_t *)(reg_addr));
 375         return rte_le_to_cpu_64(ret);
 376 }
 377
 378 /* Read Ring Control Register of FPGA LTE FEC device */
 379 static inline void
 380 print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
 381 {
 382         rte_bbdev_log_debug(
 383                 "FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
 384                 PRIx32, mmio_base, offset);
 385         rte_bbdev_log_debug(
 386                 "RING_BASE_ADDR = 0x%016"PRIx64,
 387                 fpga_reg_read_64(mmio_base, offset));
 388         rte_bbdev_log_debug(
 389                 "RING_HEAD_ADDR = 0x%016"PRIx64,
 390                 fpga_reg_read_64(mmio_base, offset +
 391                                 FPGA_LTE_FEC_RING_HEAD_ADDR));
 392         rte_bbdev_log_debug(
 393                 "RING_SIZE = 0x%04"PRIx16,
 394                 fpga_reg_read_16(mmio_base, offset +
 395                                 FPGA_LTE_FEC_RING_SIZE));
 396         rte_bbdev_log_debug(
 397                 "RING_MISC = 0x%02"PRIx8,
 398                 fpga_reg_read_8(mmio_base, offset +
 399                                 FPGA_LTE_FEC_RING_MISC));
 400         rte_bbdev_log_debug(
 401                 "RING_ENABLE = 0x%02"PRIx8,
 402                 fpga_reg_read_8(mmio_base, offset +
 403                                 FPGA_LTE_FEC_RING_ENABLE));
 404         rte_bbdev_log_debug(
 405                 "RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
 406                 fpga_reg_read_8(mmio_base, offset +
 407                                 FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN));
 408         rte_bbdev_log_debug(
 409                 "RING_SHADOW_TAIL = 0x%04"PRIx16,
 410                 fpga_reg_read_16(mmio_base, offset +
 411                                 FPGA_LTE_FEC_RING_SHADOW_TAIL));
 412         rte_bbdev_log_debug(
 413                 "RING_HEAD_POINT = 0x%04"PRIx16,
 414                 fpga_reg_read_16(mmio_base, offset +
 415                                 FPGA_LTE_FEC_RING_HEAD_POINT));
 416 }
 417
 418 /* Read Static Register of FPGA LTE FEC device */
 419 static inline void
 420 print_static_reg_debug_info(void *mmio_base)
 421 {
 422         uint16_t config = fpga_reg_read_16(mmio_base,
 423                         FPGA_LTE_FEC_CONFIGURATION);
 424         uint8_t qmap_done = fpga_reg_read_8(mmio_base,
 425                         FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE);
 426         uint16_t lb_factor = fpga_reg_read_16(mmio_base,
 427                         FPGA_LTE_FEC_LOAD_BALANCE_FACTOR);
 428         uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
 429                         FPGA_LTE_FEC_RING_DESC_LEN);
 430         uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
 431                         FPGA_LTE_FEC_FLR_TIME_OUT);
 432
 433         rte_bbdev_log_debug("UL.DL Weights = %u.%u",
 434                         ((uint8_t)config), ((uint8_t)(config >> 8)));
 435         rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
 436                         ((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
 437         rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
 438                         (qmap_done > 0) ? "READY" : "NOT-READY");
 439         rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
 440                         ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
 441         rte_bbdev_log_debug("FLR Timeout = %f usec",
 442                         (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
 443 }
 444
 445 /* Print decode DMA Descriptor of FPGA LTE FEC device */
 446 static void
 447 print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
 448 {
 449         rte_bbdev_log_debug("DMA response desc %p\n"
 450                 "\t-- done(%"PRIu32") | iter(%"PRIu32") | crc_pass(%"PRIu32")"
 451                 " | error (%"PRIu32") | crc_type(%"PRIu32")\n"
 452                 "\t-- max_iter(%"PRIu32") | bypass_rm(%"PRIu32") | "
 453                 "irq_en (%"PRIu32") | drop_crc(%"PRIu32") | offset(%"PRIu32")\n"
 454                 "\t-- k(%"PRIu32") | in_len (%"PRIu16") | op_add(%p)\n"
 455                 "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32") | "
 456                 "out_add (0x%08"PRIx32"%08"PRIx32")",
 457                 desc,
 458                 (uint32_t)desc->dec_req.done,
 459                 (uint32_t)desc->dec_req.iter,
 460                 (uint32_t)desc->dec_req.crc_pass,
 461                 (uint32_t)desc->dec_req.error,
 462                 (uint32_t)desc->dec_req.crc_type,
 463                 (uint32_t)desc->dec_req.max_iter,
 464                 (uint32_t)desc->dec_req.bypass_rm,
 465                 (uint32_t)desc->dec_req.irq_en,
 466                 (uint32_t)desc->dec_req.drop_crc,
 467                 (uint32_t)desc->dec_req.offset,
 468                 (uint32_t)desc->dec_req.k,
 469                 (uint16_t)desc->dec_req.in_len,
 470                 desc->dec_req.op_addr,
 471                 (uint32_t)desc->dec_req.cbs_in_op,
 472                 (uint32_t)desc->dec_req.in_addr_hi,
 473                 (uint32_t)desc->dec_req.in_addr_lw,
 474                 (uint32_t)desc->dec_req.out_addr_hi,
 475                 (uint32_t)desc->dec_req.out_addr_lw);
 476 }
 477 #endif
 478
 479 static int
 480 fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
 481 {
 482         /* Number of queues bound to a PF/VF */
 483         uint32_t hw_q_num = 0;
 484         uint32_t ring_size, payload, address, q_id, offset;
 485         rte_iova_t phys_addr;
 486         struct fpga_ring_ctrl_reg ring_reg;
 487         struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private;
 488
 489         address = FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE;
 490         if (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) {
 491                 rte_bbdev_log(ERR,
 492                                 "Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?",
 493                                 dev->data->name);
 494                 return -EPERM;
 495         }
 496
 497         /* Clear queue registers structure */
 498         memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
 499
 500         /* Scan queue map.
 501          * If a queue is valid and mapped to a calling PF/VF the read value is
 502          * replaced with a queue ID and if it's not then
 503          * FPGA_INVALID_HW_QUEUE_ID is returned.
 504          */
 505         for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
 506                 uint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base,
 507                                 FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2));
 508
 509                 rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u",
 510                                 dev->device->name, q_id, hw_q_id);
 511
 512                 if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) {
 513                         fpga_dev->q_bound_bit_map |= (1ULL << q_id);
 514                         /* Clear queue register of found queue */
 515                         offset = FPGA_LTE_FEC_RING_CTRL_REGS +
 516                                 (sizeof(struct fpga_ring_ctrl_reg) * q_id);
 517                         fpga_ring_reg_write(fpga_dev->mmio_base,
 518                                         offset, ring_reg);
 519                         ++hw_q_num;
 520                 }
 521         }
 522         if (hw_q_num == 0) {
 523                 rte_bbdev_log(ERR,
 524                         "No HW queues assigned to this device. Probably this is a VF configured for PF mode. Check device configuration!");
 525                 return -ENODEV;
 526         }
 527
 528         if (num_queues > hw_q_num) {
 529                 rte_bbdev_log(ERR,
 530                         "Not enough queues for device %s! Requested: %u, available: %u",
 531                         dev->device->name, num_queues, hw_q_num);
 532                 return -EINVAL;
 533         }
 534
 535         ring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);
 536
 537         /* Enforce 32 byte alignment */
 538         RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);
 539
 540         /* Allocate memory for SW descriptor rings */
 541         fpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name,
 542                         num_queues * ring_size, RTE_CACHE_LINE_SIZE,
 543                         socket_id);
 544         if (fpga_dev->sw_rings == NULL) {
 545                 rte_bbdev_log(ERR,
 546                                 "Failed to allocate memory for %s:%u sw_rings",
 547                                 dev->device->driver->name, dev->data->dev_id);
 548                 return -ENOMEM;
 549         }
 550
 551         fpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings);
 552         fpga_dev->sw_ring_size = ring_size;
 553         fpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE;
 554
 555         /* Allocate memory for ring flush status */
 556         fpga_dev->flush_queue_status = rte_zmalloc_socket(NULL,
 557                         sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);
 558         if (fpga_dev->flush_queue_status == NULL) {
 559                 rte_bbdev_log(ERR,
 560                                 "Failed to allocate memory for %s:%u flush_queue_status",
 561                                 dev->device->driver->name, dev->data->dev_id);
 562                 return -ENOMEM;
 563         }
 564
 565         /* Set the flush status address registers */
 566         phys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status);
 567
 568         address = FPGA_LTE_FEC_VFQ_FLUSH_STATUS_LW;
 569         payload = (uint32_t)(phys_addr);
 570         fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
 571
 572         address = FPGA_LTE_FEC_VFQ_FLUSH_STATUS_HI;
 573         payload = (uint32_t)(phys_addr >> 32);
 574         fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
 575
 576         return 0;
 577 }
 578
 579 static int
 580 fpga_dev_close(struct rte_bbdev *dev)
 581 {
 582         struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private;
 583
 584         rte_free(fpga_dev->sw_rings);
 585         rte_free(fpga_dev->flush_queue_status);
 586
 587         return 0;
 588 }
 589
 590 static void
 591 fpga_dev_info_get(struct rte_bbdev *dev,
 592                 struct rte_bbdev_driver_info *dev_info)
 593 {
 594         struct fpga_lte_fec_device *d = dev->data->dev_private;
 595         uint32_t q_id = 0;
 596
 597         /* TODO RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN and numbers of buffers are set
 598          * to temporary values as they are required by test application while
 599          * validation phase.
 600          */
 601         static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
 602                 {
 603                         .type = RTE_BBDEV_OP_TURBO_DEC,
 604                         .cap.turbo_dec = {
 605                                 .capability_flags =
 606                                         RTE_BBDEV_TURBO_CRC_TYPE_24B |
 607                                         RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE |
 608                                         RTE_BBDEV_TURBO_DEC_INTERRUPTS |
 609                                         RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |
 610                                         RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP,
 611                                 .max_llr_modulus = INT8_MAX,
 612                                 .num_buffers_src =
 613                                                 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
 614                                 .num_buffers_hard_out =
 615                                         RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
 616                                 .num_buffers_soft_out = 0
 617                         }
 618                 },
 619                 {
 620                         .type = RTE_BBDEV_OP_TURBO_ENC,
 621                         .cap.turbo_enc = {
 622                                 .capability_flags =
 623                                         RTE_BBDEV_TURBO_CRC_24B_ATTACH |
 624                                         RTE_BBDEV_TURBO_RATE_MATCH |
 625                                         RTE_BBDEV_TURBO_ENC_INTERRUPTS,
 626                                 .num_buffers_src =
 627                                                 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
 628                                 .num_buffers_dst =
 629                                                 RTE_BBDEV_TURBO_MAX_CODE_BLOCKS
 630                         }
 631                 },
 632                 RTE_BBDEV_END_OF_CAPABILITIES_LIST()
 633         };
 634
 635         static struct rte_bbdev_queue_conf default_queue_conf;
 636         default_queue_conf.socket = dev->data->socket_id;
 637         default_queue_conf.queue_size = FPGA_RING_MAX_SIZE;
 638
 639
 640         dev_info->driver_name = dev->device->driver->name;
 641         dev_info->queue_size_lim = FPGA_RING_MAX_SIZE;
 642         dev_info->hardware_accelerated = true;
 643         dev_info->min_alignment = 64;
 644         dev_info->default_queue_conf = default_queue_conf;
 645         dev_info->capabilities = bbdev_capabilities;
 646         dev_info->cpu_flag_reqs = NULL;
 647         dev_info->data_endianness = RTE_LITTLE_ENDIAN;
 648
 649         /* Calculates number of queues assigned to device */
 650         dev_info->max_num_queues = 0;
 651         for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
 652                 uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,
 653                                 FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2));
 654                 if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)
 655                         dev_info->max_num_queues++;
 656         }
 657 }
 658
 659 /**
 660  * Find index of queue bound to current PF/VF which is unassigned. Return -1
 661  * when there is no available queue
 662  */
 663 static int
 664 fpga_find_free_queue_idx(struct rte_bbdev *dev,
 665                 const struct rte_bbdev_queue_conf *conf)
 666 {
 667         struct fpga_lte_fec_device *d = dev->data->dev_private;
 668         uint64_t q_idx;
 669         uint8_t i = 0;
 670         uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1;
 671
 672         if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) {
 673                 i = FPGA_NUM_DL_QUEUES;
 674                 range = FPGA_TOTAL_NUM_QUEUES;
 675         }
 676
 677         for (; i < range; ++i) {
 678                 q_idx = 1ULL << i;
 679                 /* Check if index of queue is bound to current PF/VF */
 680                 if (d->q_bound_bit_map & q_idx)
 681                         /* Check if found queue was not already assigned */
 682                         if (!(d->q_assigned_bit_map & q_idx)) {
 683                                 d->q_assigned_bit_map |= q_idx;
 684                                 return i;
 685                         }
 686         }
 687
 688         rte_bbdev_log(INFO, "Failed to find free queue on %s", dev->data->name);
 689
 690         return -1;
 691 }
 692
 693 static int
 694 fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
 695                 const struct rte_bbdev_queue_conf *conf)
 696 {
 697         uint32_t address, ring_offset;
 698         struct fpga_lte_fec_device *d = dev->data->dev_private;
 699         struct fpga_queue *q;
 700         int8_t q_idx;
 701
 702         /* Check if there is a free queue to assign */
 703         q_idx = fpga_find_free_queue_idx(dev, conf);
 704         if (q_idx == -1)
 705                 return -1;
 706
 707         /* Allocate the queue data structure. */
 708         q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
 709                         RTE_CACHE_LINE_SIZE, conf->socket);
 710         if (q == NULL) {
 711                 /* Mark queue as un-assigned */
 712                 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
 713                 rte_bbdev_log(ERR, "Failed to allocate queue memory");
 714                 return -ENOMEM;
 715         }
 716
 717         q->d = d;
 718         q->q_idx = q_idx;
 719
 720         /* Set ring_base_addr */
 721         q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
 722         q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys +
 723                         (d->sw_ring_size * queue_id);
 724
 725         /* Allocate memory for Completion Head variable*/
 726         q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,
 727                         sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket);
 728         if (q->ring_head_addr == NULL) {
 729                 /* Mark queue as un-assigned */
 730                 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
 731                 rte_free(q);
 732                 rte_bbdev_log(ERR,
 733                                 "Failed to allocate memory for %s:%u completion_head",
 734                                 dev->device->driver->name, dev->data->dev_id);
 735                 return -ENOMEM;
 736         }
 737         /* Set ring_head_addr */
 738         q->ring_ctrl_reg.ring_head_addr =
 739                         rte_malloc_virt2iova(q->ring_head_addr);
 740
 741         /* Clear shadow_completion_head */
 742         q->shadow_completion_head = 0;
 743
 744         /* Set ring_size */
 745         if (conf->queue_size > FPGA_RING_MAX_SIZE) {
 746                 /* Mark queue as un-assigned */
 747                 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
 748                 rte_free(q->ring_head_addr);
 749                 rte_free(q);
 750                 rte_bbdev_log(ERR,
 751                                 "Size of queue is too big %d (MAX: %d ) for %s:%u",
 752                                 conf->queue_size, FPGA_RING_MAX_SIZE,
 753                                 dev->device->driver->name, dev->data->dev_id);
 754                 return -EINVAL;
 755         }
 756         q->ring_ctrl_reg.ring_size = conf->queue_size;
 757
 758         /* Set Miscellaneous FPGA register*/
 759         /* Max iteration number for TTI mitigation - todo */
 760         q->ring_ctrl_reg.max_ul_dec = 0;
 761         /* Enable max iteration number for TTI - todo */
 762         q->ring_ctrl_reg.max_ul_dec_en = 0;
 763
 764         /* Enable the ring */
 765         q->ring_ctrl_reg.enable = 1;
 766
 767         /* Set FPGA head_point and tail registers */
 768         q->ring_ctrl_reg.head_point = q->tail = 0;
 769
 770         /* Set FPGA shadow_tail register */
 771         q->ring_ctrl_reg.shadow_tail = q->tail;
 772
 773         /* Calculates the ring offset for found queue */
 774         ring_offset = FPGA_LTE_FEC_RING_CTRL_REGS +
 775                         (sizeof(struct fpga_ring_ctrl_reg) * q_idx);
 776
 777         /* Set FPGA Ring Control Registers */
 778         fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);
 779
 780         /* Store MMIO register of shadow_tail */
 781         address = ring_offset + FPGA_LTE_FEC_RING_SHADOW_TAIL;
 782         q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address);
 783
 784         q->head_free_desc = q->tail;
 785
 786         /* Set wrap mask */
 787         q->sw_ring_wrap_mask = conf->queue_size - 1;
 788
 789         rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u",
 790                         dev->data->dev_id, queue_id, q->q_idx);
 791
 792         dev->data->queues[queue_id].queue_private = q;
 793
 794         rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]",
 795                         queue_id, q_idx);
 796
 797 #ifdef RTE_LIBRTE_BBDEV_DEBUG
 798         /* Read FPGA Ring Control Registers after configuration*/
 799         print_ring_reg_debug_info(d->mmio_base, ring_offset);
 800 #endif
 801         return 0;
 802 }
 803
 804 static int
 805 fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)
 806 {
 807         struct fpga_lte_fec_device *d = dev->data->dev_private;
 808         struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
 809         struct fpga_ring_ctrl_reg ring_reg;
 810         uint32_t offset;
 811
 812         rte_bbdev_log_debug("FPGA Queue[%d] released", queue_id);
 813
 814         if (q != NULL) {
 815                 memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
 816                 offset = FPGA_LTE_FEC_RING_CTRL_REGS +
 817                         (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
 818                 /* Disable queue */
 819                 fpga_reg_write_8(d->mmio_base,
 820                                 offset + FPGA_LTE_FEC_RING_ENABLE, 0x00);
 821                 /* Clear queue registers */
 822                 fpga_ring_reg_write(d->mmio_base, offset, ring_reg);
 823
 824                 /* Mark the Queue as un-assigned */
 825                 d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx));
 826                 rte_free(q->ring_head_addr);
 827                 rte_free(q);
 828                 dev->data->queues[queue_id].queue_private = NULL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 /* Function starts a device queue. */
 835 static int
 836 fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)
 837 {
 838         struct fpga_lte_fec_device *d = dev->data->dev_private;
 839 #ifdef RTE_LIBRTE_BBDEV_DEBUG
 840         if (d == NULL) {
 841                 rte_bbdev_log(ERR, "Invalid device pointer");
 842                 return -1;
 843         }
 844 #endif
 845         struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
 846         uint32_t offset = FPGA_LTE_FEC_RING_CTRL_REGS +
 847                         (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
 848         uint8_t enable = 0x01;
 849         uint16_t zero = 0x0000;
 850
 851         /* Clear queue head and tail variables */
 852         q->tail = q->head_free_desc = 0;
 853
 854         /* Clear FPGA head_point and tail registers */
 855         fpga_reg_write_16(d->mmio_base, offset + FPGA_LTE_FEC_RING_HEAD_POINT,
 856                         zero);
 857         fpga_reg_write_16(d->mmio_base, offset + FPGA_LTE_FEC_RING_SHADOW_TAIL,
 858                         zero);
 859
 860         /* Enable queue */
 861         fpga_reg_write_8(d->mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE,
 862                         enable);
 863
 864         rte_bbdev_log_debug("FPGA Queue[%d] started", queue_id);
 865         return 0;
 866 }
 867
 868 /* Function stops a device queue. */
 869 static int
 870 fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)
 871 {
 872         struct fpga_lte_fec_device *d = dev->data->dev_private;
 873 #ifdef RTE_LIBRTE_BBDEV_DEBUG
 874         if (d == NULL) {
 875                 rte_bbdev_log(ERR, "Invalid device pointer");
 876                 return -1;
 877         }
 878 #endif
 879         struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
 880         uint32_t offset = FPGA_LTE_FEC_RING_CTRL_REGS +
 881                         (sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
 882         uint8_t payload = 0x01;
 883         uint8_t counter = 0;
 884         uint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US /
 885                         FPGA_TIMEOUT_CHECK_INTERVAL;
 886
 887         /* Set flush_queue_en bit to trigger queue flushing */
 888         fpga_reg_write_8(d->mmio_base,
 889                         offset + FPGA_LTE_FEC_RING_FLUSH_QUEUE_EN, payload);
 890
 891         /** Check if queue flush is completed.
 892          * FPGA will update the completion flag after queue flushing is
 893          * completed. If completion flag is not updated within 1ms it is
 894          * considered as a failure.
 895          */
 896         while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {
 897                 if (counter > timeout) {
 898                         rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
 899                                         queue_id);
 900                         return -1;
 901                 }
 902                 usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
 903                 counter++;
 904         }
 905
 906         /* Disable queue */
 907         payload = 0x00;
 908         fpga_reg_write_8(d->mmio_base, offset + FPGA_LTE_FEC_RING_ENABLE,
 909                         payload);
 910
 911         rte_bbdev_log_debug("FPGA Queue[%d] stopped", queue_id);
 912         return 0;
 913 }
 914
 915 static inline uint16_t
 916 get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)
 917 {
 918         uint16_t queue_id;
 919
 920         for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
 921                 struct fpga_queue *q = data->queues[queue_id].queue_private;
 922                 if (q != NULL && q->q_idx == q_idx)
 923                         return queue_id;
 924         }
 925
 926         return -1;
 927 }
 928
 929 /* Interrupt handler triggered by FPGA dev for handling specific interrupt */
 930 static void
 931 fpga_dev_interrupt_handler(void *cb_arg)
 932 {
 933         struct rte_bbdev *dev = cb_arg;
 934         struct fpga_lte_fec_device *fpga_dev = dev->data->dev_private;
 935         struct fpga_queue *q;
 936         uint64_t ring_head;
 937         uint64_t q_idx;
 938         uint16_t queue_id;
 939         uint8_t i;
 940
 941         /* Scan queue assigned to this device */
 942         for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {
 943                 q_idx = 1ULL << i;
 944                 if (fpga_dev->q_bound_bit_map & q_idx) {
 945                         queue_id = get_queue_id(dev->data, i);
 946                         if (queue_id == (uint16_t) -1)
 947                                 continue;
 948
 949                         /* Check if completion head was changed */
 950                         q = dev->data->queues[queue_id].queue_private;
 951                         ring_head = *q->ring_head_addr;
 952                         if (q->shadow_completion_head != ring_head &&
 953                                 q->irq_enable == 1) {
 954                                 q->shadow_completion_head = ring_head;
 955                                 rte_bbdev_pmd_callback_process(
 956                                                 dev,
 957                                                 RTE_BBDEV_EVENT_DEQUEUE,
 958                                                 &queue_id);
 959                         }
 960                 }
 961         }
 962 }
 963
 964 static int
 965 fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)
 966 {
 967         struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
 968
 969         if (!rte_intr_cap_multiple(dev->intr_handle))
 970                 return -ENOTSUP;
 971
 972         q->irq_enable = 1;
 973
 974         return 0;
 975 }
 976
 977 static int
 978 fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)
 979 {
 980         struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
 981         q->irq_enable = 0;
 982
 983         return 0;
 984 }
 985
 986 static int
 987 fpga_intr_enable(struct rte_bbdev *dev)
 988 {
 989         int ret;
 990         uint8_t i;
 991
 992         if (!rte_intr_cap_multiple(dev->intr_handle)) {
 993                 rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)",
 994                                 dev->data->name);
 995                 return -ENOTSUP;
 996         }
 997
 998         /* Create event file descriptors for each of 64 queue. Event fds will be
 999          * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where
1000          * the IRQ number is a direct translation to the queue number.
1001          *
1002          * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()
1003          * mapped the first IRQ to already created interrupt event file
1004          * descriptor (intr_handle->fd).
1005          */
1006         if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {
1007                 rte_bbdev_log(ERR, "Failed to create fds for %u queues",
1008                                 dev->data->num_queues);
1009                 return -1;
1010         }
1011
1012         /* TODO Each event file descriptor is overwritten by interrupt event
1013          * file descriptor. That descriptor is added to epoll observed list.
1014          * It ensures that callback function assigned to that descriptor will
1015          * invoked when any FPGA queue issues interrupt.
1016          */
1017         for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) {
1018                 if (rte_intr_efds_index_set(dev->intr_handle, i,
1019                                 rte_intr_fd_get(dev->intr_handle)))
1020                         return -rte_errno;
1021         }
1022
1023         if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
1024                         dev->data->num_queues)) {
1025                 rte_bbdev_log(ERR, "Failed to allocate %u vectors",
1026                                 dev->data->num_queues);
1027                 return -ENOMEM;
1028         }
1029
1030         ret = rte_intr_enable(dev->intr_handle);
1031         if (ret < 0) {
1032                 rte_bbdev_log(ERR,
1033                                 "Couldn't enable interrupts for device: %s",
1034                                 dev->data->name);
1035                 return ret;
1036         }
1037
1038         ret = rte_intr_callback_register(dev->intr_handle,
1039                         fpga_dev_interrupt_handler, dev);
1040         if (ret < 0) {
1041                 rte_bbdev_log(ERR,
1042                                 "Couldn't register interrupt callback for device: %s",
1043                                 dev->data->name);
1044                 return ret;
1045         }
1046
1047         return 0;
1048 }
1049
1050 static const struct rte_bbdev_ops fpga_ops = {
1051         .setup_queues = fpga_setup_queues,
1052         .intr_enable = fpga_intr_enable,
1053         .close = fpga_dev_close,
1054         .info_get = fpga_dev_info_get,
1055         .queue_setup = fpga_queue_setup,
1056         .queue_stop = fpga_queue_stop,
1057         .queue_start = fpga_queue_start,
1058         .queue_release = fpga_queue_release,
1059         .queue_intr_enable = fpga_queue_intr_enable,
1060         .queue_intr_disable = fpga_queue_intr_disable
1061 };
1062
1063 static inline void
1064 fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
1065                 struct rte_bbdev_stats *queue_stats)
1066 {
1067 #ifdef RTE_BBDEV_OFFLOAD_COST
1068         uint64_t start_time = 0;
1069         queue_stats->acc_offload_cycles = 0;
1070 #else
1071         RTE_SET_USED(queue_stats);
1072 #endif
1073
1074         /* Update tail and shadow_tail register */
1075         q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;
1076
1077         rte_wmb();
1078
1079 #ifdef RTE_BBDEV_OFFLOAD_COST
1080         /* Start time measurement for enqueue function offload. */
1081         start_time = rte_rdtsc_precise();
1082 #endif
1083         mmio_write_16(q->shadow_tail_addr, q->tail);
1084
1085 #ifdef RTE_BBDEV_OFFLOAD_COST
1086         rte_wmb();
1087         queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;
1088 #endif
1089 }
1090
1091 /* Calculates number of CBs in processed encoder TB based on 'r' and input
1092  * length.
1093  */
1094 static inline uint8_t
1095 get_num_cbs_in_op_enc(struct rte_bbdev_op_turbo_enc *turbo_enc)
1096 {
1097         uint8_t c, c_neg, r, crc24_bits = 0;
1098         uint16_t k, k_neg, k_pos;
1099         uint8_t cbs_in_op = 0;
1100         int32_t length;
1101
1102         length = turbo_enc->input.length;
1103         r = turbo_enc->tb_params.r;
1104         c = turbo_enc->tb_params.c;
1105         c_neg = turbo_enc->tb_params.c_neg;
1106         k_neg = turbo_enc->tb_params.k_neg;
1107         k_pos = turbo_enc->tb_params.k_pos;
1108         crc24_bits = 24;
1109         while (length > 0 && r < c) {
1110                 k = (r < c_neg) ? k_neg : k_pos;
1111                 length -= (k - crc24_bits) >> 3;
1112                 r++;
1113                 cbs_in_op++;
1114         }
1115
1116         return cbs_in_op;
1117 }
1118
1119 /* Calculates number of CBs in processed decoder TB based on 'r' and input
1120  * length.
1121  */
1122 static inline uint16_t
1123 get_num_cbs_in_op_dec(struct rte_bbdev_op_turbo_dec *turbo_dec)
1124 {
1125         uint8_t c, c_neg, r = 0;
1126         uint16_t kw, k, k_neg, k_pos, cbs_in_op = 0;
1127         int32_t length;
1128
1129         length = turbo_dec->input.length;
1130         r = turbo_dec->tb_params.r;
1131         c = turbo_dec->tb_params.c;
1132         c_neg = turbo_dec->tb_params.c_neg;
1133         k_neg = turbo_dec->tb_params.k_neg;
1134         k_pos = turbo_dec->tb_params.k_pos;
1135         while (length > 0 && r < c) {
1136                 k = (r < c_neg) ? k_neg : k_pos;
1137                 kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
1138                 length -= kw;
1139                 r++;
1140                 cbs_in_op++;
1141         }
1142
1143         return cbs_in_op;
1144 }
1145
1146 /* Read flag value 0/1/ from bitmap */
1147 static inline bool
1148 check_bit(uint32_t bitmap, uint32_t bitmask)
1149 {
1150         return bitmap & bitmask;
1151 }
1152
1153 /* Print an error if a descriptor error has occurred.
1154  *  Return 0 on success, 1 on failure
1155  */
1156 static inline int
1157 check_desc_error(uint32_t error_code) {
1158         switch (error_code) {
1159         case DESC_ERR_NO_ERR:
1160                 return 0;
1161         case DESC_ERR_K_OUT_OF_RANGE:
1162                 rte_bbdev_log(ERR, "Block_size_k is out of range (k<40 or k>6144)");
1163                 break;
1164         case DESC_ERR_K_NOT_NORMAL:
1165                 rte_bbdev_log(ERR, "Block_size_k is not a normal value within normal range");
1166                 break;
1167         case DESC_ERR_KPAI_NOT_NORMAL:
1168                 rte_bbdev_log(ERR, "Three_kpai is not a normal value for UL only");
1169                 break;
1170         case DESC_ERR_DESC_OFFSET_ERR:
1171                 rte_bbdev_log(ERR, "Queue offset does not meet the expectation in the FPGA");
1172                 break;
1173         case (DESC_ERR_K_OUT_OF_RANGE | DESC_ERR_DESC_OFFSET_ERR):
1174                 rte_bbdev_log(ERR, "Block_size_k is out of range (k<40 or k>6144) and queue offset error");
1175                 break;
1176         case (DESC_ERR_K_NOT_NORMAL | DESC_ERR_DESC_OFFSET_ERR):
1177                 rte_bbdev_log(ERR, "Block_size_k is not a normal value within normal range and queue offset error");
1178                 break;
1179         case (DESC_ERR_KPAI_NOT_NORMAL | DESC_ERR_DESC_OFFSET_ERR):
1180                 rte_bbdev_log(ERR, "Three_kpai is not a normal value for UL only and queue offset error");
1181                 break;
1182         case DESC_ERR_DESC_READ_FAIL:
1183                 rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read");
1184                 break;
1185         case DESC_ERR_DESC_READ_TIMEOUT:
1186                 rte_bbdev_log(ERR, "Descriptor read time-out");
1187                 break;
1188         case DESC_ERR_DESC_READ_TLP_POISONED:
1189                 rte_bbdev_log(ERR, "Descriptor read TLP poisoned");
1190                 break;
1191         case DESC_ERR_CB_READ_FAIL:
1192                 rte_bbdev_log(ERR, "Unsuccessful completion for code block");
1193                 break;
1194         case DESC_ERR_CB_READ_TIMEOUT:
1195                 rte_bbdev_log(ERR, "Code block read time-out");
1196                 break;
1197         case DESC_ERR_CB_READ_TLP_POISONED:
1198                 rte_bbdev_log(ERR, "Code block read TLP poisoned");
1199                 break;
1200         default:
1201                 rte_bbdev_log(ERR, "Descriptor error unknown error code %u",
1202                                 error_code);
1203                 break;
1204         }
1205         return 1;
1206 }
1207
1208 /**
1209  * Set DMA descriptor for encode operation (1 Code Block)
1210  *
1211  * @param op
1212  *   Pointer to a single encode operation.
1213  * @param desc
1214  *   Pointer to DMA descriptor.
1215  * @param input
1216  *   Pointer to pointer to input data which will be decoded.
1217  * @param k
1218  *   K value (length of input in bits).
1219  * @param e
1220  *   E value (length of output in bits).
1221  * @param ncb
1222  *   Ncb value (size of the soft buffer).
1223  * @param out_length
1224  *   Length of output buffer
1225  * @param in_offset
1226  *   Input offset in rte_mbuf structure. It is used for calculating the point
1227  *   where data is starting.
1228  * @param out_offset
1229  *   Output offset in rte_mbuf structure. It is used for calculating the point
1230  *   where hard output data will be stored.
1231  * @param cbs_in_op
1232  *   Number of CBs contained in one operation.
1233  */
1234 static inline int
1235 fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,
1236                 struct fpga_dma_enc_desc *desc, struct rte_mbuf *input,
1237                 struct rte_mbuf *output, uint16_t k, uint16_t e, uint16_t ncb,
1238                 uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
1239                 uint8_t cbs_in_op)
1240
1241 {
1242         /* reset */
1243         desc->done = 0;
1244         desc->crc_en = check_bit(op->turbo_enc.op_flags,
1245                 RTE_BBDEV_TURBO_CRC_24B_ATTACH);
1246         desc->bypass_rm = !check_bit(op->turbo_enc.op_flags,
1247                 RTE_BBDEV_TURBO_RATE_MATCH);
1248         desc->k = k;
1249         desc->e = e;
1250         desc->ncb = ncb;
1251         desc->rv = op->turbo_enc.rv_index;
1252         desc->offset = desc_offset;
1253         /* Set inbound data buffer address */
1254         desc->in_addr_hi = (uint32_t)(
1255                         rte_pktmbuf_iova_offset(input, in_offset) >> 32);
1256         desc->in_addr_lw = (uint32_t)(
1257                         rte_pktmbuf_iova_offset(input, in_offset));
1258
1259         desc->out_addr_hi = (uint32_t)(
1260                         rte_pktmbuf_iova_offset(output, out_offset) >> 32);
1261         desc->out_addr_lw = (uint32_t)(
1262                         rte_pktmbuf_iova_offset(output, out_offset));
1263
1264         /* Save software context needed for dequeue */
1265         desc->op_addr = op;
1266
1267         /* Set total number of CBs in an op */
1268         desc->cbs_in_op = cbs_in_op;
1269
1270         return 0;
1271 }
1272
1273 /**
1274  * Set DMA descriptor for encode operation (1 Code Block)
1275  *
1276  * @param op
1277  *   Pointer to a single encode operation.
1278  * @param desc
1279  *   Pointer to DMA descriptor.
1280  * @param input
1281  *   Pointer to pointer to input data which will be decoded.
1282  * @param in_length
1283  *   Length of an input.
1284  * @param k
1285  *   K value (length of an output in bits).
1286  * @param in_offset
1287  *   Input offset in rte_mbuf structure. It is used for calculating the point
1288  *   where data is starting.
1289  * @param out_offset
1290  *   Output offset in rte_mbuf structure. It is used for calculating the point
1291  *   where hard output data will be stored.
1292  * @param cbs_in_op
1293  *   Number of CBs contained in one operation.
1294  */
1295 static inline int
1296 fpga_dma_desc_td_fill(struct rte_bbdev_dec_op *op,
1297                 struct fpga_dma_dec_desc *desc, struct rte_mbuf *input,
1298                 struct rte_mbuf *output, uint16_t in_length, uint16_t k,
1299                 uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
1300                 uint8_t cbs_in_op)
1301 {
1302         /* reset */
1303         desc->done = 0;
1304         /* Set inbound data buffer address */
1305         desc->in_addr_hi = (uint32_t)(
1306                         rte_pktmbuf_iova_offset(input, in_offset) >> 32);
1307         desc->in_addr_lw = (uint32_t)(
1308                         rte_pktmbuf_iova_offset(input, in_offset));
1309         desc->in_len = in_length;
1310         desc->k = k;
1311         desc->crc_type = !check_bit(op->turbo_dec.op_flags,
1312                         RTE_BBDEV_TURBO_CRC_TYPE_24B);
1313         if ((op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
1314                 && !check_bit(op->turbo_dec.op_flags,
1315                 RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP))
1316                 desc->drop_crc = 1;
1317         desc->max_iter = op->turbo_dec.iter_max * 2;
1318         desc->offset = desc_offset;
1319         desc->out_addr_hi = (uint32_t)(
1320                         rte_pktmbuf_iova_offset(output, out_offset) >> 32);
1321         desc->out_addr_lw = (uint32_t)(
1322                         rte_pktmbuf_iova_offset(output, out_offset));
1323
1324         /* Save software context needed for dequeue */
1325         desc->op_addr = op;
1326
1327         /* Set total number of CBs in an op */
1328         desc->cbs_in_op = cbs_in_op;
1329
1330         return 0;
1331 }
1332
1333 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1334 /* Validates turbo encoder parameters */
1335 static int
1336 validate_enc_op(struct rte_bbdev_enc_op *op)
1337 {
1338         struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
1339         struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
1340         struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
1341         uint16_t kw, kw_neg, kw_pos;
1342
1343         if (turbo_enc->input.length >
1344                         RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) {
1345                 rte_bbdev_log(ERR, "TB size (%u) is too big, max: %d",
1346                                 turbo_enc->input.length,
1347                                 RTE_BBDEV_TURBO_MAX_TB_SIZE);
1348                 op->status = 1 << RTE_BBDEV_DATA_ERROR;
1349                 return -1;
1350         }
1351
1352         if (op->mempool == NULL) {
1353                 rte_bbdev_log(ERR, "Invalid mempool pointer");
1354                 return -1;
1355         }
1356         if (turbo_enc->input.data == NULL) {
1357                 rte_bbdev_log(ERR, "Invalid input pointer");
1358                 return -1;
1359         }
1360         if (turbo_enc->output.data == NULL) {
1361                 rte_bbdev_log(ERR, "Invalid output pointer");
1362                 return -1;
1363         }
1364         if (turbo_enc->rv_index > 3) {
1365                 rte_bbdev_log(ERR,
1366                                 "rv_index (%u) is out of range 0 <= value <= 3",
1367                                 turbo_enc->rv_index);
1368                 return -1;
1369         }
1370         if (turbo_enc->code_block_mode != RTE_BBDEV_TRANSPORT_BLOCK &&
1371                         turbo_enc->code_block_mode != RTE_BBDEV_CODE_BLOCK) {
1372                 rte_bbdev_log(ERR,
1373                                 "code_block_mode (%u) is out of range 0 <= value <= 1",
1374                                 turbo_enc->code_block_mode);
1375                 return -1;
1376         }
1377
1378         if (turbo_enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {
1379                 tb = &turbo_enc->tb_params;
1380                 if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE
1381                                 || tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)
1382                                 && tb->c_neg > 0) {
1383                         rte_bbdev_log(ERR,
1384                                         "k_neg (%u) is out of range %u <= value <= %u",
1385                                         tb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1386                                         RTE_BBDEV_TURBO_MAX_CB_SIZE);
1387                         return -1;
1388                 }
1389                 if (tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE
1390                                 || tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE) {
1391                         rte_bbdev_log(ERR,
1392                                         "k_pos (%u) is out of range %u <= value <= %u",
1393                                         tb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1394                                         RTE_BBDEV_TURBO_MAX_CB_SIZE);
1395                         return -1;
1396                 }
1397                 if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))
1398                         rte_bbdev_log(ERR,
1399                                         "c_neg (%u) is out of range 0 <= value <= %u",
1400                                         tb->c_neg,
1401                                         RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1);
1402                 if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {
1403                         rte_bbdev_log(ERR,
1404                                         "c (%u) is out of range 1 <= value <= %u",
1405                                         tb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);
1406                         return -1;
1407                 }
1408                 if (tb->cab > tb->c) {
1409                         rte_bbdev_log(ERR,
1410                                         "cab (%u) is greater than c (%u)",
1411                                         tb->cab, tb->c);
1412                         return -1;
1413                 }
1414                 if ((tb->ea < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->ea % 2))
1415                                 && tb->r < tb->cab) {
1416                         rte_bbdev_log(ERR,
1417                                         "ea (%u) is less than %u or it is not even",
1418                                         tb->ea, RTE_BBDEV_TURBO_MIN_CB_SIZE);
1419                         return -1;
1420                 }
1421                 if ((tb->eb < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->eb % 2))
1422                                 && tb->c > tb->cab) {
1423                         rte_bbdev_log(ERR,
1424                                         "eb (%u) is less than %u or it is not even",
1425                                         tb->eb, RTE_BBDEV_TURBO_MIN_CB_SIZE);
1426                         return -1;
1427                 }
1428
1429                 kw_neg = 3 * RTE_ALIGN_CEIL(tb->k_neg + 4,
1430                                         RTE_BBDEV_TURBO_C_SUBBLOCK);
1431                 if (tb->ncb_neg < tb->k_neg || tb->ncb_neg > kw_neg) {
1432                         rte_bbdev_log(ERR,
1433                                         "ncb_neg (%u) is out of range (%u) k_neg <= value <= (%u) kw_neg",
1434                                         tb->ncb_neg, tb->k_neg, kw_neg);
1435                         return -1;
1436                 }
1437
1438                 kw_pos = 3 * RTE_ALIGN_CEIL(tb->k_pos + 4,
1439                                         RTE_BBDEV_TURBO_C_SUBBLOCK);
1440                 if (tb->ncb_pos < tb->k_pos || tb->ncb_pos > kw_pos) {
1441                         rte_bbdev_log(ERR,
1442                                         "ncb_pos (%u) is out of range (%u) k_pos <= value <= (%u) kw_pos",
1443                                         tb->ncb_pos, tb->k_pos, kw_pos);
1444                         return -1;
1445                 }
1446                 if (tb->r > (tb->c - 1)) {
1447                         rte_bbdev_log(ERR,
1448                                         "r (%u) is greater than c - 1 (%u)",
1449                                         tb->r, tb->c - 1);
1450                         return -1;
1451                 }
1452         } else {
1453                 cb = &turbo_enc->cb_params;
1454                 if (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE
1455                                 || cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {
1456                         rte_bbdev_log(ERR,
1457                                         "k (%u) is out of range %u <= value <= %u",
1458                                         cb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1459                                         RTE_BBDEV_TURBO_MAX_CB_SIZE);
1460                         return -1;
1461                 }
1462
1463                 if (cb->e < RTE_BBDEV_TURBO_MIN_CB_SIZE || (cb->e % 2)) {
1464                         rte_bbdev_log(ERR,
1465                                         "e (%u) is less than %u or it is not even",
1466                                         cb->e, RTE_BBDEV_TURBO_MIN_CB_SIZE);
1467                         return -1;
1468                 }
1469
1470                 kw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_TURBO_C_SUBBLOCK) * 3;
1471                 if (cb->ncb < cb->k || cb->ncb > kw) {
1472                         rte_bbdev_log(ERR,
1473                                         "ncb (%u) is out of range (%u) k <= value <= (%u) kw",
1474                                         cb->ncb, cb->k, kw);
1475                         return -1;
1476                 }
1477         }
1478
1479         return 0;
1480 }
1481 #endif
1482
1483 static inline char *
1484 mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
1485 {
1486         if (unlikely(len > rte_pktmbuf_tailroom(m)))
1487                 return NULL;
1488
1489         char *tail = (char *)m->buf_addr + m->data_off + m->data_len;
1490         m->data_len = (uint16_t)(m->data_len + len);
1491         m_head->pkt_len  = (m_head->pkt_len + len);
1492         return tail;
1493 }
1494
1495 static inline int
1496 enqueue_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
1497                 uint16_t desc_offset)
1498 {
1499         union fpga_dma_desc *desc;
1500         struct rte_mbuf *input;
1501         struct rte_mbuf *output;
1502         int ret;
1503         uint16_t k, e, ncb, ring_offset;
1504         uint32_t total_left, in_length, out_length, in_offset, out_offset;
1505
1506 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1507         /* Validate op structure */
1508         if (validate_enc_op(op) == -1) {
1509                 rte_bbdev_log(ERR, "Turbo encoder validation failed");
1510                 return -EINVAL;
1511         }
1512 #endif
1513
1514         input = op->turbo_enc.input.data;
1515         output = op->turbo_enc.output.data;
1516         in_offset = op->turbo_enc.input.offset;
1517         out_offset = op->turbo_enc.output.offset;
1518         total_left = op->turbo_enc.input.length;
1519         k = op->turbo_enc.cb_params.k;
1520         e = op->turbo_enc.cb_params.e;
1521         ncb = op->turbo_enc.cb_params.ncb;
1522
1523         if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_CRC_24B_ATTACH))
1524                 in_length = ((k - 24) >> 3);
1525         else
1526                 in_length = k >> 3;
1527
1528         if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_RATE_MATCH))
1529                 out_length = (e + 7) >> 3;
1530         else
1531                 out_length = (k >> 3) * 3 + 2;
1532
1533         mbuf_append(output, output, out_length);
1534
1535         /* Offset into the ring */
1536         ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1537         /* Setup DMA Descriptor */
1538         desc = q->ring_addr + ring_offset;
1539
1540         ret = fpga_dma_desc_te_fill(op, &desc->enc_req, input, output, k, e,
1541                         ncb, in_offset, out_offset, ring_offset, 1);
1542         if (unlikely(ret < 0))
1543                 return ret;
1544
1545         /* Update lengths */
1546         total_left -= in_length;
1547         op->turbo_enc.output.length += out_length;
1548
1549         if (total_left > 0) {
1550                 rte_bbdev_log(ERR,
1551                         "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
1552                                 total_left, in_length);
1553                 return -1;
1554         }
1555
1556         return 1;
1557 }
1558
1559 static inline int
1560 enqueue_enc_one_op_tb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
1561                 uint16_t desc_offset, uint8_t cbs_in_op)
1562 {
1563         union fpga_dma_desc *desc;
1564         struct rte_mbuf *input, *output_head, *output;
1565         int ret;
1566         uint8_t r, c, crc24_bits = 0;
1567         uint16_t k, e, ncb, ring_offset;
1568         uint32_t mbuf_total_left, in_length, out_length, in_offset, out_offset;
1569         uint32_t seg_total_left;
1570         uint16_t current_enqueued_cbs = 0;
1571
1572 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1573         /* Validate op structure */
1574         if (validate_enc_op(op) == -1) {
1575                 rte_bbdev_log(ERR, "Turbo encoder validation failed");
1576                 return -EINVAL;
1577         }
1578 #endif
1579
1580         input = op->turbo_enc.input.data;
1581         output_head = output = op->turbo_enc.output.data;
1582         in_offset = op->turbo_enc.input.offset;
1583         out_offset = op->turbo_enc.output.offset;
1584         mbuf_total_left = op->turbo_enc.input.length;
1585
1586         c = op->turbo_enc.tb_params.c;
1587         r = op->turbo_enc.tb_params.r;
1588
1589         if (check_bit(op->turbo_enc.op_flags, RTE_BBDEV_TURBO_CRC_24B_ATTACH))
1590                 crc24_bits = 24;
1591
1592         while (mbuf_total_left > 0 && r < c && input != NULL) {
1593                 seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
1594
1595                 e = (r < op->turbo_enc.tb_params.cab) ?
1596                                 op->turbo_enc.tb_params.ea :
1597                                 op->turbo_enc.tb_params.eb;
1598                 k = (r < op->turbo_enc.tb_params.c_neg) ?
1599                                 op->turbo_enc.tb_params.k_neg :
1600                                 op->turbo_enc.tb_params.k_pos;
1601                 ncb = (r < op->turbo_enc.tb_params.c_neg) ?
1602                                 op->turbo_enc.tb_params.ncb_neg :
1603                                 op->turbo_enc.tb_params.ncb_pos;
1604
1605                 in_length = ((k - crc24_bits) >> 3);
1606
1607                 if (check_bit(op->turbo_enc.op_flags,
1608                         RTE_BBDEV_TURBO_RATE_MATCH))
1609                         out_length = (e + 7) >> 3;
1610                 else
1611                         out_length = (k >> 3) * 3 + 2;
1612
1613                 mbuf_append(output_head, output, out_length);
1614
1615                 /* Setup DMA Descriptor */
1616                 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1617                 desc = q->ring_addr + ring_offset;
1618                 ret = fpga_dma_desc_te_fill(op, &desc->enc_req, input, output,
1619                                 k, e, ncb, in_offset, out_offset, ring_offset,
1620                                 cbs_in_op);
1621                 if (unlikely(ret < 0))
1622                         return ret;
1623
1624                 rte_bbdev_log_debug("DMA request desc %p", desc);
1625
1626                 /* Update lengths */
1627                 op->turbo_enc.output.length += out_length;
1628                 mbuf_total_left -= in_length;
1629
1630                 /* Update offsets */
1631                 if (seg_total_left == in_length) {
1632                         /* Go to the next mbuf */
1633                         input = input->next;
1634                         output = output->next;
1635                         in_offset = 0;
1636                         out_offset = 0;
1637                 } else {
1638                         in_offset += in_length;
1639                         out_offset += out_length;
1640                 }
1641
1642                 r++;
1643                 desc_offset++;
1644                 current_enqueued_cbs++;
1645         }
1646
1647         if (mbuf_total_left > 0) {
1648                 rte_bbdev_log(ERR,
1649                                 "Some date still left for processing: mbuf_total_left = %u",
1650                                 mbuf_total_left);
1651                 return -1;
1652         }
1653
1654         return current_enqueued_cbs;
1655 }
1656
1657 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1658 /* Validates turbo decoder parameters */
1659 static int
1660 validate_dec_op(struct rte_bbdev_dec_op *op)
1661 {
1662         struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
1663         struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
1664         struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
1665
1666         if (op->mempool == NULL) {
1667                 rte_bbdev_log(ERR, "Invalid mempool pointer");
1668                 return -1;
1669         }
1670         if (turbo_dec->input.data == NULL) {
1671                 rte_bbdev_log(ERR, "Invalid input pointer");
1672                 return -1;
1673         }
1674         if (turbo_dec->hard_output.data == NULL) {
1675                 rte_bbdev_log(ERR, "Invalid hard_output pointer");
1676                 return -1;
1677         }
1678         if (turbo_dec->rv_index > 3) {
1679                 rte_bbdev_log(ERR,
1680                                 "rv_index (%u) is out of range 0 <= value <= 3",
1681                                 turbo_dec->rv_index);
1682                 return -1;
1683         }
1684         if (turbo_dec->iter_min < 1) {
1685                 rte_bbdev_log(ERR,
1686                                 "iter_min (%u) is less than 1",
1687                                 turbo_dec->iter_min);
1688                 return -1;
1689         }
1690         if (turbo_dec->iter_max <= 2) {
1691                 rte_bbdev_log(ERR,
1692                                 "iter_max (%u) is less than or equal to 2",
1693                                 turbo_dec->iter_max);
1694                 return -1;
1695         }
1696         if (turbo_dec->iter_min > turbo_dec->iter_max) {
1697                 rte_bbdev_log(ERR,
1698                                 "iter_min (%u) is greater than iter_max (%u)",
1699                                 turbo_dec->iter_min, turbo_dec->iter_max);
1700                 return -1;
1701         }
1702         if (turbo_dec->code_block_mode != RTE_BBDEV_TRANSPORT_BLOCK &&
1703                         turbo_dec->code_block_mode != RTE_BBDEV_CODE_BLOCK) {
1704                 rte_bbdev_log(ERR,
1705                                 "code_block_mode (%u) is out of range 0 <= value <= 1",
1706                                 turbo_dec->code_block_mode);
1707                 return -1;
1708         }
1709
1710         if (turbo_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {
1711
1712                 if ((turbo_dec->op_flags &
1713                         RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) &&
1714                         !(turbo_dec->op_flags & RTE_BBDEV_TURBO_CRC_TYPE_24B)) {
1715                         rte_bbdev_log(ERR,
1716                                 "RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP should accompany RTE_BBDEV_TURBO_CRC_TYPE_24B");
1717                         return -1;
1718                 }
1719
1720                 tb = &turbo_dec->tb_params;
1721                 if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE
1722                                 || tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)
1723                                 && tb->c_neg > 0) {
1724                         rte_bbdev_log(ERR,
1725                                         "k_neg (%u) is out of range %u <= value <= %u",
1726                                         tb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1727                                         RTE_BBDEV_TURBO_MAX_CB_SIZE);
1728                         return -1;
1729                 }
1730                 if ((tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE
1731                                 || tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE)
1732                                 && tb->c > tb->c_neg) {
1733                         rte_bbdev_log(ERR,
1734                                         "k_pos (%u) is out of range %u <= value <= %u",
1735                                         tb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1736                                         RTE_BBDEV_TURBO_MAX_CB_SIZE);
1737                         return -1;
1738                 }
1739                 if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))
1740                         rte_bbdev_log(ERR,
1741                                         "c_neg (%u) is out of range 0 <= value <= %u",
1742                                         tb->c_neg,
1743                                         RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1);
1744                 if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {
1745                         rte_bbdev_log(ERR,
1746                                         "c (%u) is out of range 1 <= value <= %u",
1747                                         tb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);
1748                         return -1;
1749                 }
1750                 if (tb->cab > tb->c) {
1751                         rte_bbdev_log(ERR,
1752                                         "cab (%u) is greater than c (%u)",
1753                                         tb->cab, tb->c);
1754                         return -1;
1755                 }
1756         } else {
1757
1758                 if (turbo_dec->op_flags & RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) {
1759                         rte_bbdev_log(ERR,
1760                                         "RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP is invalid in CB-mode");
1761                         return -1;
1762                 }
1763
1764                 cb = &turbo_dec->cb_params;
1765                 if (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE
1766                                 || cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {
1767                         rte_bbdev_log(ERR,
1768                                         "k (%u) is out of range %u <= value <= %u",
1769                                         cb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE,
1770                                         RTE_BBDEV_TURBO_MAX_CB_SIZE);
1771                         return -1;
1772                 }
1773         }
1774
1775         return 0;
1776 }
1777 #endif
1778
1779 static inline int
1780 enqueue_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
1781                 uint16_t desc_offset)
1782 {
1783         union fpga_dma_desc *desc;
1784         struct rte_mbuf *input;
1785         struct rte_mbuf *output;
1786         int ret;
1787         uint16_t k, kw, ring_offset;
1788         uint32_t total_left, in_length, out_length, in_offset, out_offset;
1789
1790 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1791         /* Validate op structure */
1792         if (validate_dec_op(op) == -1) {
1793                 rte_bbdev_log(ERR, "Turbo decoder validation failed");
1794                 return -EINVAL;
1795         }
1796 #endif
1797
1798         input = op->turbo_dec.input.data;
1799         output = op->turbo_dec.hard_output.data;
1800         total_left = op->turbo_dec.input.length;
1801         in_offset = op->turbo_dec.input.offset;
1802         out_offset = op->turbo_dec.hard_output.offset;
1803
1804         k = op->turbo_dec.cb_params.k;
1805         kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
1806         in_length = kw;
1807         out_length = k >> 3;
1808
1809         mbuf_append(output, output, out_length);
1810
1811         /* Setup DMA Descriptor */
1812         ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1813         desc = q->ring_addr + ring_offset;
1814         ret = fpga_dma_desc_td_fill(op, &desc->dec_req, input, output,
1815                         in_length, k, in_offset, out_offset, ring_offset, 1);
1816         if (unlikely(ret < 0))
1817                 return ret;
1818
1819 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1820         print_dma_dec_desc_debug_info(desc);
1821 #endif
1822
1823         /* Update lengths */
1824         total_left -= in_length;
1825         op->turbo_dec.hard_output.length += out_length;
1826
1827         if (total_left > 0) {
1828                 rte_bbdev_log(ERR,
1829                                 "Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
1830                                 total_left, in_length);
1831                 return -1;
1832         }
1833
1834         return 1;
1835 }
1836
1837
1838 static inline int
1839 enqueue_dec_one_op_tb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
1840                 uint16_t desc_offset, uint8_t cbs_in_op)
1841 {
1842         union fpga_dma_desc *desc;
1843         struct rte_mbuf *input, *output_head, *output;
1844         int ret;
1845         uint8_t r, c;
1846         uint16_t k, kw, in_length, out_length, ring_offset;
1847         uint32_t mbuf_total_left, seg_total_left, in_offset, out_offset;
1848         uint16_t current_enqueued_cbs = 0;
1849         uint16_t crc24_overlap = 0;
1850
1851 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1852         /* Validate op structure */
1853         if (validate_dec_op(op) == -1) {
1854                 rte_bbdev_log(ERR, "Turbo decoder validation failed");
1855                 return -EINVAL;
1856         }
1857 #endif
1858
1859         input = op->turbo_dec.input.data;
1860         output_head = output = op->turbo_dec.hard_output.data;
1861         mbuf_total_left = op->turbo_dec.input.length;
1862         in_offset = op->turbo_dec.input.offset;
1863         out_offset = op->turbo_dec.hard_output.offset;
1864
1865         if (!check_bit(op->turbo_dec.op_flags,
1866                 RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP))
1867                 crc24_overlap = 24;
1868
1869         c = op->turbo_dec.tb_params.c;
1870         r = op->turbo_dec.tb_params.r;
1871
1872         while (mbuf_total_left > 0 && r < c && input != NULL) {
1873                 seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
1874                 k = (r < op->turbo_dec.tb_params.c_neg) ?
1875                                 op->turbo_dec.tb_params.k_neg :
1876                                 op->turbo_dec.tb_params.k_pos;
1877                 kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
1878
1879                 in_length = kw;
1880                 out_length = (k - crc24_overlap) >> 3;
1881
1882                 mbuf_append(output_head, output, out_length);
1883
1884                 if (seg_total_left < in_length) {
1885                         rte_bbdev_log(ERR,
1886                                         "Partial CB found in a TB. FPGA Driver doesn't support scatter-gather operations!");
1887                         return -1;
1888                 }
1889
1890                 /* Setup DMA Descriptor */
1891                 ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
1892                 desc = q->ring_addr + ring_offset;
1893                 ret = fpga_dma_desc_td_fill(op, &desc->dec_req, input, output,
1894                                 in_length, k, in_offset, out_offset,
1895                                 ring_offset, cbs_in_op);
1896                 if (unlikely(ret < 0))
1897                         return ret;
1898
1899                 /* Update lengths */
1900                 ret = rte_pktmbuf_trim(op->turbo_dec.hard_output.data,
1901                                 (crc24_overlap >> 3));
1902 #ifdef RTE_LIBRTE_BBDEV_DEBUG
1903                 if (ret < 0) {
1904                         rte_bbdev_log(ERR,
1905                                         "The length to remove is greater than the length of the last segment");
1906                         return -EINVAL;
1907                 }
1908 #endif
1909                 op->turbo_dec.hard_output.length += out_length;
1910                 mbuf_total_left -= in_length;
1911
1912                 /* Update offsets */
1913                 if (seg_total_left == in_length) {
1914                         /* Go to the next mbuf */
1915                         input = input->next;
1916                         output = output->next;
1917                         in_offset = 0;
1918                         out_offset = 0;
1919                 } else {
1920                         in_offset += in_length;
1921                         out_offset += out_length;
1922                 }
1923
1924                 r++;
1925                 desc_offset++;
1926                 current_enqueued_cbs++;
1927         }
1928
1929         if (mbuf_total_left > 0) {
1930                 rte_bbdev_log(ERR,
1931                                 "Some date still left for processing: mbuf_total_left = %u",
1932                                 mbuf_total_left);
1933                 return -1;
1934         }
1935
1936         return current_enqueued_cbs;
1937 }
1938
1939 static uint16_t
1940 fpga_enqueue_enc(struct rte_bbdev_queue_data *q_data,
1941                 struct rte_bbdev_enc_op **ops, uint16_t num)
1942 {
1943         uint8_t cbs_in_op;
1944         uint16_t i, total_enqueued_cbs = 0;
1945         int32_t avail;
1946         int enqueued_cbs;
1947         struct fpga_queue *q = q_data->queue_private;
1948         union fpga_dma_desc *desc;
1949
1950         /* Check if queue is not full */
1951         if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
1952                         q->head_free_desc))
1953                 return 0;
1954
1955         /* Calculates available space */
1956         avail = (q->head_free_desc > q->tail) ?
1957                 q->head_free_desc - q->tail - 1 :
1958                 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
1959
1960         for (i = 0; i < num; ++i) {
1961                 if (ops[i]->turbo_enc.code_block_mode ==
1962                                 RTE_BBDEV_TRANSPORT_BLOCK) {
1963                         cbs_in_op = get_num_cbs_in_op_enc(&ops[i]->turbo_enc);
1964                         /* Check if there is available space for further
1965                          * processing
1966                          */
1967                         if (unlikely(avail - cbs_in_op < 0))
1968                                 break;
1969                         avail -= cbs_in_op;
1970                         enqueued_cbs = enqueue_enc_one_op_tb(q, ops[i],
1971                                         total_enqueued_cbs, cbs_in_op);
1972                 } else {
1973                         /* Check if there is available space for further
1974                          * processing
1975                          */
1976                         if (unlikely(avail - 1 < 0))
1977                                 break;
1978                         avail -= 1;
1979                         enqueued_cbs = enqueue_enc_one_op_cb(q, ops[i],
1980                                         total_enqueued_cbs);
1981                 }
1982
1983                 if (enqueued_cbs < 0)
1984                         break;
1985
1986                 total_enqueued_cbs += enqueued_cbs;
1987
1988                 rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d",
1989                                 total_enqueued_cbs, num,
1990                                 q->head_free_desc, q->tail);
1991         }
1992
1993         /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
1994          * only when all previous CBs were already processed.
1995          */
1996         desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
1997                         & q->sw_ring_wrap_mask);
1998         desc->enc_req.irq_en = q->irq_enable;
1999
2000         fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
2001
2002         /* Update stats */
2003         q_data->queue_stats.enqueued_count += i;
2004         q_data->queue_stats.enqueue_err_count += num - i;
2005
2006         return i;
2007 }
2008
2009 static uint16_t
2010 fpga_enqueue_dec(struct rte_bbdev_queue_data *q_data,
2011                 struct rte_bbdev_dec_op **ops, uint16_t num)
2012 {
2013         uint8_t cbs_in_op;
2014         uint16_t i, total_enqueued_cbs = 0;
2015         int32_t avail;
2016         int enqueued_cbs;
2017         struct fpga_queue *q = q_data->queue_private;
2018         union fpga_dma_desc *desc;
2019
2020         /* Check if queue is not full */
2021         if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
2022                         q->head_free_desc))
2023                 return 0;
2024
2025         /* Calculates available space */
2026         avail = (q->head_free_desc > q->tail) ?
2027                 q->head_free_desc - q->tail - 1 :
2028                 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
2029
2030         for (i = 0; i < num; ++i) {
2031                 if (ops[i]->turbo_dec.code_block_mode ==
2032                                 RTE_BBDEV_TRANSPORT_BLOCK) {
2033                         cbs_in_op = get_num_cbs_in_op_dec(&ops[i]->turbo_dec);
2034                         /* Check if there is available space for further
2035                          * processing
2036                          */
2037                         if (unlikely(avail - cbs_in_op < 0))
2038                                 break;
2039                         avail -= cbs_in_op;
2040                         enqueued_cbs = enqueue_dec_one_op_tb(q, ops[i],
2041                                         total_enqueued_cbs, cbs_in_op);
2042                 } else {
2043                         /* Check if there is available space for further
2044                          * processing
2045                          */
2046                         if (unlikely(avail - 1 < 0))
2047                                 break;
2048                         avail -= 1;
2049                         enqueued_cbs = enqueue_dec_one_op_cb(q, ops[i],
2050                                         total_enqueued_cbs);
2051                 }
2052
2053                 if (enqueued_cbs < 0)
2054                         break;
2055
2056                 total_enqueued_cbs += enqueued_cbs;
2057
2058                 rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d",
2059                                 total_enqueued_cbs, num,
2060                                 q->head_free_desc, q->tail);
2061         }
2062
2063         /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
2064          * only when all previous CBs were already processed.
2065          */
2066         desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
2067                         & q->sw_ring_wrap_mask);
2068         desc->dec_req.irq_en = q->irq_enable;
2069
2070         fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
2071
2072         /* Update stats */
2073         q_data->queue_stats.enqueued_count += i;
2074         q_data->queue_stats.enqueue_err_count += num - i;
2075
2076         return i;
2077 }
2078
2079 static inline int
2080 dequeue_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,
2081                 uint16_t desc_offset)
2082 {
2083         union fpga_dma_desc *desc;
2084         int desc_error = 0;
2085
2086         /* Set current desc */
2087         desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2088                         & q->sw_ring_wrap_mask);
2089
2090         /*check if done */
2091         if (desc->enc_req.done == 0)
2092                 return -1;
2093
2094         /* make sure the response is read atomically */
2095         rte_smp_rmb();
2096
2097         rte_bbdev_log_debug("DMA response desc %p", desc);
2098
2099         *op = desc->enc_req.op_addr;
2100         /* Check the decriptor error field, return 1 on error */
2101         desc_error = check_desc_error(desc->enc_req.error);
2102         (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
2103
2104         return 1;
2105 }
2106
2107 static inline int
2108 dequeue_enc_one_op_tb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,
2109                 uint16_t desc_offset)
2110 {
2111         union fpga_dma_desc *desc;
2112         uint8_t cbs_in_op, cb_idx;
2113         int desc_error = 0;
2114         int status = 0;
2115
2116         /* Set descriptor */
2117         desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2118                         & q->sw_ring_wrap_mask);
2119
2120         /* Verify if done bit is set */
2121         if (desc->enc_req.done == 0)
2122                 return -1;
2123
2124         /* Make sure the response is read atomically */
2125         rte_smp_rmb();
2126
2127         /* Verify if done bit in all CBs is set */
2128         cbs_in_op = desc->enc_req.cbs_in_op;
2129         for (cb_idx = 1; cb_idx < cbs_in_op; ++cb_idx) {
2130                 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2131                                 cb_idx) & q->sw_ring_wrap_mask);
2132                 if (desc->enc_req.done == 0)
2133                         return -1;
2134         }
2135
2136         /* Make sure the response is read atomically */
2137         rte_smp_rmb();
2138
2139         for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) {
2140                 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2141                                 cb_idx) & q->sw_ring_wrap_mask);
2142                 /* Check the decriptor error field, return 1 on error */
2143                 desc_error = check_desc_error(desc->enc_req.error);
2144                 status |=  desc_error << RTE_BBDEV_DATA_ERROR;
2145                 rte_bbdev_log_debug("DMA response desc %p", desc);
2146         }
2147
2148         *op = desc->enc_req.op_addr;
2149         (*op)->status = status;
2150         return cbs_in_op;
2151 }
2152
2153 static inline int
2154 dequeue_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
2155                 uint16_t desc_offset)
2156 {
2157         union fpga_dma_desc *desc;
2158         int desc_error = 0;
2159         /* Set descriptor */
2160         desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2161                         & q->sw_ring_wrap_mask);
2162
2163         /* Verify done bit is set */
2164         if (desc->dec_req.done == 0)
2165                 return -1;
2166
2167         /* make sure the response is read atomically */
2168         rte_smp_rmb();
2169
2170 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2171         print_dma_dec_desc_debug_info(desc);
2172
2173 #endif
2174
2175         *op = desc->dec_req.op_addr;
2176         /* FPGA reports in half-iterations, from 0 to 31. get ceiling */
2177         (*op)->turbo_dec.iter_count = (desc->dec_req.iter + 2) >> 1;
2178         /* crc_pass = 0 when decoder fails */
2179         (*op)->status = !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
2180         /* Check the decriptor error field, return 1 on error */
2181         desc_error = check_desc_error(desc->enc_req.error);
2182         (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
2183         return 1;
2184 }
2185
2186 static inline int
2187 dequeue_dec_one_op_tb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
2188                 uint16_t desc_offset)
2189 {
2190         union fpga_dma_desc *desc;
2191         uint8_t cbs_in_op, cb_idx, iter_count = 0;
2192         int status = 0;
2193         int  desc_error = 0;
2194         /* Set descriptor */
2195         desc = q->ring_addr + ((q->head_free_desc + desc_offset)
2196                         & q->sw_ring_wrap_mask);
2197
2198         /* Verify if done bit is set */
2199         if (desc->dec_req.done == 0)
2200                 return -1;
2201
2202         /* Make sure the response is read atomically */
2203         rte_smp_rmb();
2204
2205         /* Verify if done bit in all CBs is set */
2206         cbs_in_op = desc->dec_req.cbs_in_op;
2207         for (cb_idx = 1; cb_idx < cbs_in_op; ++cb_idx) {
2208                 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2209                                 cb_idx) & q->sw_ring_wrap_mask);
2210                 if (desc->dec_req.done == 0)
2211                         return -1;
2212         }
2213
2214         /* Make sure the response is read atomically */
2215         rte_smp_rmb();
2216
2217         for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) {
2218                 desc = q->ring_addr + ((q->head_free_desc + desc_offset +
2219                                 cb_idx) & q->sw_ring_wrap_mask);
2220                 /* get max iter_count for all CBs in op */
2221                 iter_count = RTE_MAX(iter_count, (uint8_t) desc->dec_req.iter);
2222                 /* crc_pass = 0 when decoder fails, one fails all */
2223                 status |= !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
2224                 /* Check the decriptor error field, return 1 on error */
2225                 desc_error = check_desc_error(desc->enc_req.error);
2226                 status |= desc_error << RTE_BBDEV_DATA_ERROR;
2227                 rte_bbdev_log_debug("DMA response desc %p", desc);
2228         }
2229
2230         *op = desc->dec_req.op_addr;
2231
2232         /* FPGA reports in half-iterations, get ceiling */
2233         (*op)->turbo_dec.iter_count = (iter_count + 2) >> 1;
2234         (*op)->status = status;
2235         return cbs_in_op;
2236 }
2237
2238 static uint16_t
2239 fpga_dequeue_enc(struct rte_bbdev_queue_data *q_data,
2240                 struct rte_bbdev_enc_op **ops, uint16_t num)
2241 {
2242         struct fpga_queue *q = q_data->queue_private;
2243         uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
2244         uint16_t i;
2245         uint16_t dequeued_cbs = 0;
2246         struct rte_bbdev_enc_op *op;
2247         int ret;
2248
2249         for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
2250                 op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs)
2251                         & q->sw_ring_wrap_mask))->enc_req.op_addr;
2252                 if (op->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
2253                         ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs);
2254                 else
2255                         ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs);
2256
2257                 if (ret < 0)
2258                         break;
2259
2260                 dequeued_cbs += ret;
2261
2262                 rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d",
2263                                 dequeued_cbs, num, q->head_free_desc, q->tail);
2264         }
2265
2266         /* Update head */
2267         q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
2268                         q->sw_ring_wrap_mask;
2269
2270         /* Update stats */
2271         q_data->queue_stats.dequeued_count += i;
2272
2273         return i;
2274 }
2275
2276 static uint16_t
2277 fpga_dequeue_dec(struct rte_bbdev_queue_data *q_data,
2278                 struct rte_bbdev_dec_op **ops, uint16_t num)
2279 {
2280         struct fpga_queue *q = q_data->queue_private;
2281         uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
2282         uint16_t i;
2283         uint16_t dequeued_cbs = 0;
2284         struct rte_bbdev_dec_op *op;
2285         int ret;
2286
2287         for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
2288                 op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs)
2289                         & q->sw_ring_wrap_mask))->dec_req.op_addr;
2290                 if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
2291                         ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs);
2292                 else
2293                         ret = dequeue_dec_one_op_cb(q, &ops[i], dequeued_cbs);
2294
2295                 if (ret < 0)
2296                         break;
2297
2298                 dequeued_cbs += ret;
2299
2300                 rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d",
2301                                 dequeued_cbs, num, q->head_free_desc, q->tail);
2302         }
2303
2304         /* Update head */
2305         q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
2306                         q->sw_ring_wrap_mask;
2307
2308         /* Update stats */
2309         q_data->queue_stats.dequeued_count += i;
2310
2311         return i;
2312 }
2313
2314 /* Initialization Function */
2315 static void
2316 fpga_lte_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
2317 {
2318         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2319
2320         dev->dev_ops = &fpga_ops;
2321         dev->enqueue_enc_ops = fpga_enqueue_enc;
2322         dev->enqueue_dec_ops = fpga_enqueue_dec;
2323         dev->dequeue_enc_ops = fpga_dequeue_enc;
2324         dev->dequeue_dec_ops = fpga_dequeue_dec;
2325
2326         ((struct fpga_lte_fec_device *) dev->data->dev_private)->pf_device =
2327                         !strcmp(drv->driver.name,
2328                                         RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME));
2329         ((struct fpga_lte_fec_device *) dev->data->dev_private)->mmio_base =
2330                         pci_dev->mem_resource[0].addr;
2331
2332         rte_bbdev_log_debug(
2333                         "Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
2334                         drv->driver.name, dev->data->name,
2335                         (void *)pci_dev->mem_resource[0].addr,
2336                         pci_dev->mem_resource[0].phys_addr);
2337 }
2338
2339 static int
2340 fpga_lte_fec_probe(struct rte_pci_driver *pci_drv,
2341         struct rte_pci_device *pci_dev)
2342 {
2343         struct rte_bbdev *bbdev = NULL;
2344         char dev_name[RTE_BBDEV_NAME_MAX_LEN];
2345
2346         if (pci_dev == NULL) {
2347                 rte_bbdev_log(ERR, "NULL PCI device");
2348                 return -EINVAL;
2349         }
2350
2351         rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));
2352
2353         /* Allocate memory to be used privately by drivers */
2354         bbdev = rte_bbdev_allocate(pci_dev->device.name);
2355         if (bbdev == NULL)
2356                 return -ENODEV;
2357
2358         /* allocate device private memory */
2359         bbdev->data->dev_private = rte_zmalloc_socket(dev_name,
2360                         sizeof(struct fpga_lte_fec_device), RTE_CACHE_LINE_SIZE,
2361                         pci_dev->device.numa_node);
2362
2363         if (bbdev->data->dev_private == NULL) {
2364                 rte_bbdev_log(CRIT,
2365                                 "Allocate of %zu bytes for device \"%s\" failed",
2366                                 sizeof(struct fpga_lte_fec_device), dev_name);
2367                                 rte_bbdev_release(bbdev);
2368                         return -ENOMEM;
2369         }
2370
2371         /* Fill HW specific part of device structure */
2372         bbdev->device = &pci_dev->device;
2373         bbdev->intr_handle = pci_dev->intr_handle;
2374         bbdev->data->socket_id = pci_dev->device.numa_node;
2375
2376         /* Invoke FEC FPGA device initialization function */
2377         fpga_lte_fec_init(bbdev, pci_drv);
2378
2379         rte_bbdev_log_debug("bbdev id = %u [%s]",
2380                         bbdev->data->dev_id, dev_name);
2381
2382         struct fpga_lte_fec_device *d = bbdev->data->dev_private;
2383         uint32_t version_id = fpga_reg_read_32(d->mmio_base,
2384                         FPGA_LTE_FEC_VERSION_ID);
2385         rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u",
2386                 ((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
2387
2388 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2389         if (!strcmp(pci_drv->driver.name,
2390                         RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME)))
2391                 print_static_reg_debug_info(d->mmio_base);
2392 #endif
2393         return 0;
2394 }
2395
2396 static int
2397 fpga_lte_fec_remove(struct rte_pci_device *pci_dev)
2398 {
2399         struct rte_bbdev *bbdev;
2400         int ret;
2401         uint8_t dev_id;
2402
2403         if (pci_dev == NULL)
2404                 return -EINVAL;
2405
2406         /* Find device */
2407         bbdev = rte_bbdev_get_named_dev(pci_dev->device.name);
2408         if (bbdev == NULL) {
2409                 rte_bbdev_log(CRIT,
2410                                 "Couldn't find HW dev \"%s\" to uninitialise it",
2411                                 pci_dev->device.name);
2412                 return -ENODEV;
2413         }
2414         dev_id = bbdev->data->dev_id;
2415
2416         /* free device private memory before close */
2417         rte_free(bbdev->data->dev_private);
2418
2419         /* Close device */
2420         ret = rte_bbdev_close(dev_id);
2421         if (ret < 0)
2422                 rte_bbdev_log(ERR,
2423                                 "Device %i failed to close during uninit: %i",
2424                                 dev_id, ret);
2425
2426         /* release bbdev from library */
2427         ret = rte_bbdev_release(bbdev);
2428         if (ret)
2429                 rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id,
2430                                 ret);
2431
2432         rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id);
2433
2434         return 0;
2435 }
2436
2437 static inline void
2438 set_default_fpga_conf(struct rte_fpga_lte_fec_conf *def_conf)
2439 {
2440         /* clear default configuration before initialization */
2441         memset(def_conf, 0, sizeof(struct rte_fpga_lte_fec_conf));
2442         /* Set pf mode to true */
2443         def_conf->pf_mode_en = true;
2444
2445         /* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */
2446         def_conf->ul_bandwidth = 3;
2447         def_conf->dl_bandwidth = 3;
2448
2449         /* Set Load Balance Factor to 64 */
2450         def_conf->dl_load_balance = 64;
2451         def_conf->ul_load_balance = 64;
2452 }
2453
2454 /* Initial configuration of FPGA LTE FEC device */
2455 int
2456 rte_fpga_lte_fec_configure(const char *dev_name,
2457                 const struct rte_fpga_lte_fec_conf *conf)
2458 {
2459         uint32_t payload_32, address;
2460         uint16_t payload_16;
2461         uint8_t payload_8;
2462         uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;
2463         struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
2464         struct rte_fpga_lte_fec_conf def_conf;
2465
2466         if (bbdev == NULL) {
2467                 rte_bbdev_log(ERR,
2468                                 "Invalid dev_name (%s), or device is not yet initialised",
2469                                 dev_name);
2470                 return -ENODEV;
2471         }
2472
2473         struct fpga_lte_fec_device *d = bbdev->data->dev_private;
2474
2475         if (conf == NULL) {
2476                 rte_bbdev_log(ERR,
2477                                 "FPGA Configuration was not provided. Default configuration will be loaded.");
2478                 set_default_fpga_conf(&def_conf);
2479                 conf = &def_conf;
2480         }
2481
2482         /*
2483          * Configure UL:DL ratio.
2484          * [7:0]: UL weight
2485          * [15:8]: DL weight
2486          */
2487         payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;
2488         address = FPGA_LTE_FEC_CONFIGURATION;
2489         fpga_reg_write_16(d->mmio_base, address, payload_16);
2490
2491         /* Clear all queues registers */
2492         payload_32 = FPGA_INVALID_HW_QUEUE_ID;
2493         for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
2494                 address = (q_id << 2) + FPGA_LTE_FEC_QUEUE_MAP;
2495                 fpga_reg_write_32(d->mmio_base, address, payload_32);
2496         }
2497
2498         /*
2499          * If PF mode is enabled allocate all queues for PF only.
2500          *
2501          * For VF mode each VF can have different number of UL and DL queues.
2502          * Total number of queues to configure cannot exceed FPGA
2503          * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.
2504          * Queues mapping is done according to configuration:
2505          *
2506          * UL queues:
2507          * |                Q_ID              | VF_ID |
2508          * |                 0                |   0   |
2509          * |                ...               |   0   |
2510          * | conf->vf_dl_queues_number[0] - 1 |   0   |
2511          * | conf->vf_dl_queues_number[0]     |   1   |
2512          * |                ...               |   1   |
2513          * | conf->vf_dl_queues_number[1] - 1 |   1   |
2514          * |                ...               |  ...  |
2515          * | conf->vf_dl_queues_number[7] - 1 |   7   |
2516          *
2517          * DL queues:
2518          * |                Q_ID              | VF_ID |
2519          * |                 32               |   0   |
2520          * |                ...               |   0   |
2521          * | conf->vf_ul_queues_number[0] - 1 |   0   |
2522          * | conf->vf_ul_queues_number[0]     |   1   |
2523          * |                ...               |   1   |
2524          * | conf->vf_ul_queues_number[1] - 1 |   1   |
2525          * |                ...               |  ...  |
2526          * | conf->vf_ul_queues_number[7] - 1 |   7   |
2527          *
2528          * Example of configuration:
2529          * conf->vf_ul_queues_number[0] = 4;  -> 4 UL queues for VF0
2530          * conf->vf_dl_queues_number[0] = 4;  -> 4 DL queues for VF0
2531          * conf->vf_ul_queues_number[1] = 2;  -> 2 UL queues for VF1
2532          * conf->vf_dl_queues_number[1] = 2;  -> 2 DL queues for VF1
2533          *
2534          * UL:
2535          * | Q_ID | VF_ID |
2536          * |   0  |   0   |
2537          * |   1  |   0   |
2538          * |   2  |   0   |
2539          * |   3  |   0   |
2540          * |   4  |   1   |
2541          * |   5  |   1   |
2542          *
2543          * DL:
2544          * | Q_ID | VF_ID |
2545          * |  32  |   0   |
2546          * |  33  |   0   |
2547          * |  34  |   0   |
2548          * |  35  |   0   |
2549          * |  36  |   1   |
2550          * |  37  |   1   |
2551          */
2552         if (conf->pf_mode_en) {
2553                 payload_32 = 0x1;
2554                 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
2555                         address = (q_id << 2) + FPGA_LTE_FEC_QUEUE_MAP;
2556                         fpga_reg_write_32(d->mmio_base, address, payload_32);
2557                 }
2558         } else {
2559                 /* Calculate total number of UL and DL queues to configure */
2560                 total_ul_q_id = total_dl_q_id = 0;
2561                 for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) {
2562                         total_ul_q_id += conf->vf_ul_queues_number[vf_id];
2563                         total_dl_q_id += conf->vf_dl_queues_number[vf_id];
2564                 }
2565                 total_q_id = total_dl_q_id + total_ul_q_id;
2566                 /*
2567                  * Check if total number of queues to configure does not exceed
2568                  * FPGA capabilities (64 queues - 32 UL and 32 DL queues)
2569                  */
2570                 if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||
2571                         (total_dl_q_id > FPGA_NUM_DL_QUEUES) ||
2572                         (total_q_id > FPGA_TOTAL_NUM_QUEUES)) {
2573                         rte_bbdev_log(ERR,
2574                                         "FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u",
2575                                         total_ul_q_id, total_dl_q_id,
2576                                         FPGA_TOTAL_NUM_QUEUES);
2577                         return -EINVAL;
2578                 }
2579                 total_ul_q_id = 0;
2580                 for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) {
2581                         for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];
2582                                         ++q_id, ++total_ul_q_id) {
2583                                 address = (total_ul_q_id << 2) +
2584                                                 FPGA_LTE_FEC_QUEUE_MAP;
2585                                 payload_32 = ((0x80 + vf_id) << 16) | 0x1;
2586                                 fpga_reg_write_32(d->mmio_base, address,
2587                                                 payload_32);
2588                         }
2589                 }
2590                 total_dl_q_id = 0;
2591                 for (vf_id = 0; vf_id < FPGA_LTE_FEC_NUM_VFS; ++vf_id) {
2592                         for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];
2593                                         ++q_id, ++total_dl_q_id) {
2594                                 address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)
2595                                                 << 2) + FPGA_LTE_FEC_QUEUE_MAP;
2596                                 payload_32 = ((0x80 + vf_id) << 16) | 0x1;
2597                                 fpga_reg_write_32(d->mmio_base, address,
2598                                                 payload_32);
2599                         }
2600                 }
2601         }
2602
2603         /* Setting Load Balance Factor */
2604         payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);
2605         address = FPGA_LTE_FEC_LOAD_BALANCE_FACTOR;
2606         fpga_reg_write_16(d->mmio_base, address, payload_16);
2607
2608         /* Setting length of ring descriptor entry */
2609         payload_16 = FPGA_RING_DESC_ENTRY_LENGTH;
2610         address = FPGA_LTE_FEC_RING_DESC_LEN;
2611         fpga_reg_write_16(d->mmio_base, address, payload_16);
2612
2613         /* Setting FLR timeout value */
2614         payload_16 = conf->flr_time_out;
2615         address = FPGA_LTE_FEC_FLR_TIME_OUT;
2616         fpga_reg_write_16(d->mmio_base, address, payload_16);
2617
2618         /* Queue PF/VF mapping table is ready */
2619         payload_8 = 0x1;
2620         address = FPGA_LTE_FEC_QUEUE_PF_VF_MAP_DONE;
2621         fpga_reg_write_8(d->mmio_base, address, payload_8);
2622
2623         rte_bbdev_log_debug("PF FPGA LTE FEC configuration complete for %s",
2624                         dev_name);
2625
2626 #ifdef RTE_LIBRTE_BBDEV_DEBUG
2627         print_static_reg_debug_info(d->mmio_base);
2628 #endif
2629         return 0;
2630 }
2631
2632 /* FPGA LTE FEC PCI PF address map */
2633 static struct rte_pci_id pci_id_fpga_lte_fec_pf_map[] = {
2634         {
2635                 RTE_PCI_DEVICE(FPGA_LTE_FEC_VENDOR_ID,
2636                                 FPGA_LTE_FEC_PF_DEVICE_ID)
2637         },
2638         {.device_id = 0},
2639 };
2640
2641 static struct rte_pci_driver fpga_lte_fec_pci_pf_driver = {
2642         .probe = fpga_lte_fec_probe,
2643         .remove = fpga_lte_fec_remove,
2644         .id_table = pci_id_fpga_lte_fec_pf_map,
2645         .drv_flags = RTE_PCI_DRV_NEED_MAPPING
2646 };
2647
2648 /* FPGA LTE FEC PCI VF address map */
2649 static struct rte_pci_id pci_id_fpga_lte_fec_vf_map[] = {
2650         {
2651                 RTE_PCI_DEVICE(FPGA_LTE_FEC_VENDOR_ID,
2652                                 FPGA_LTE_FEC_VF_DEVICE_ID)
2653         },
2654         {.device_id = 0},
2655 };
2656
2657 static struct rte_pci_driver fpga_lte_fec_pci_vf_driver = {
2658         .probe = fpga_lte_fec_probe,
2659         .remove = fpga_lte_fec_remove,
2660         .id_table = pci_id_fpga_lte_fec_vf_map,
2661         .drv_flags = RTE_PCI_DRV_NEED_MAPPING
2662 };
2663
2664
2665 RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_PF_DRIVER_NAME, fpga_lte_fec_pci_pf_driver);
2666 RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_PF_DRIVER_NAME,
2667                 pci_id_fpga_lte_fec_pf_map);
2668 RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_VF_DRIVER_NAME, fpga_lte_fec_pci_vf_driver);
2669 RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_VF_DRIVER_NAME,
2670                 pci_id_fpga_lte_fec_vf_map);