1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020-2021 NXP
4 #ifndef __BBDEV_LA12XX_IPC_H__
5 #define __BBDEV_LA12XX_IPC_H__
7 #define LA12XX_MAX_QUEUES 20
8 #define HOST_RX_QUEUEID_OFFSET LA12XX_MAX_QUEUES
10 /** No. of max channel per instance */
11 #define IPC_MAX_CHANNEL_COUNT (64)
13 /** No. of max channel per instance */
14 #define IPC_MAX_DEPTH (16)
16 /** No. of max IPC instance per modem */
17 #define IPC_MAX_INSTANCE_COUNT (1)
20 #define IPC_SUCCESS (0) /** IPC operation success */
21 #define IPC_INPUT_INVALID (-1) /** Invalid input to API */
22 #define IPC_CH_INVALID (-2) /** Channel no is invalid */
23 #define IPC_INSTANCE_INVALID (-3) /** Instance no is invalid */
24 #define IPC_MEM_INVALID (-4) /** Insufficient memory */
25 #define IPC_CH_FULL (-5) /** Channel is full */
26 #define IPC_CH_EMPTY (-6) /** Channel is empty */
27 #define IPC_BL_EMPTY (-7) /** Free buffer list is empty */
28 #define IPC_BL_FULL (-8) /** Free buffer list is full */
29 #define IPC_HOST_BUF_ALLOC_FAIL (-9) /** DPDK malloc fail */
30 #define IPC_MD_SZ_MISS_MATCH (-10) /** META DATA size in mhif miss matched*/
31 #define IPC_MALLOC_FAIL (-11) /** system malloc fail */
32 #define IPC_IOCTL_FAIL (-12) /** IOCTL call failed */
33 #define IPC_MMAP_FAIL (-14) /** MMAP fail */
34 #define IPC_OPEN_FAIL (-15) /** OPEN fail */
35 #define IPC_EVENTFD_FAIL (-16) /** eventfd initialization failed */
36 #define IPC_NOT_IMPLEMENTED (-17) /** IPC feature is not implemented yet*/
38 #define SET_HIF_HOST_RDY(hif, RDY_MASK) (hif->host_ready |= RDY_MASK)
39 #define CHK_HIF_MOD_RDY(hif, RDY_MASK) (hif->mod_ready & RDY_MASK)
42 #define HIF_HOST_READY_HOST_REGIONS (1 << 0)
43 #define HIF_HOST_READY_IPC_LIB (1 << 12)
44 #define HIF_HOST_READY_IPC_APP (1 << 13)
45 #define HIF_HOST_READY_FECA (1 << 14)
47 /* Modem Ready bits */
48 #define HIF_MOD_READY_IPC_LIB (1 << 5)
49 #define HIF_MOD_READY_IPC_APP (1 << 6)
50 #define HIF_MOD_READY_FECA (1 << 7)
68 #define GUL_IPC_MAGIC 'R'
70 #define IOCTL_GUL_IPC_GET_SYS_MAP _IOW(GUL_IPC_MAGIC, 1, struct ipc_msg *)
71 #define IOCTL_GUL_IPC_CHANNEL_REGISTER _IOWR(GUL_IPC_MAGIC, 4, struct ipc_msg *)
72 #define IOCTL_GUL_IPC_CHANNEL_DEREGISTER \
73 _IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *)
74 #define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *)
76 #define GUL_USER_HUGE_PAGE_OFFSET (0)
77 #define GUL_PCI1_ADDR_BASE (0x00000000ULL)
79 #define GUL_USER_HUGE_PAGE_ADDR (GUL_PCI1_ADDR_BASE + GUL_USER_HUGE_PAGE_OFFSET)
81 /* IPC PI/CI index & flag manipulation helpers */
82 #define IPC_PI_CI_FLAG_MASK 0x80000000 /* (1<<31) */
83 #define IPC_PI_CI_INDEX_MASK 0x7FFFFFFF /* ~(1<<31) */
85 #define IPC_SET_PI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK)
86 #define IPC_RESET_PI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK)
87 #define IPC_GET_PI_FLAG(x) (x >> 31)
88 #define IPC_GET_PI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK)
90 #define IPC_SET_CI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK)
91 #define IPC_RESET_CI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK)
92 #define IPC_GET_CI_FLAG(x) (x >> 31)
93 #define IPC_GET_CI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK)
95 /** buffer ring common metadata */
96 typedef struct ipc_bd_ring_md {
97 volatile uint32_t pi; /**< Producer index and flag (MSB)
98 * which flip for each Ring wrapping
100 volatile uint32_t ci; /**< Consumer index and flag (MSB)
101 * which flip for each Ring wrapping
103 uint32_t ring_size; /**< depth (Used to roll-over pi/ci) */
104 uint32_t msg_size; /**< Size of the each buffer */
105 } __rte_packed ipc_br_md_t;
107 /** IPC buffer descriptor */
108 typedef struct ipc_buffer_desc {
110 uint64_t host_virt; /**< msg's host virtual address */
112 uint32_t host_virt_l;
113 uint32_t host_virt_h;
116 uint32_t modem_ptr; /**< msg's modem physical address */
117 uint32_t len; /**< msg len */
118 } __rte_packed ipc_bd_t;
120 typedef struct ipc_channel {
121 uint32_t ch_id; /**< Channel id */
122 ipc_br_md_t md; /**< Metadata for BD ring */
123 ipc_bd_t bd_h[IPC_MAX_DEPTH]; /**< Buffer Descriptor on Host */
124 ipc_bd_t bd_m[IPC_MAX_DEPTH]; /**< Buffer Descriptor on Modem */
125 uint32_t op_type; /**< Type of the BBDEV operation
126 * supported on this channel
128 uint32_t depth; /**< Channel depth */
129 uint32_t feca_blk_id; /**< FECA Transport Block ID for processing */
130 uint32_t la12xx_core_id;/**< LA12xx core ID on which this will be
133 uint32_t feca_input_circ_size; /**< FECA transport block input
134 * circular buffer size
136 uint32_t host_ipc_params; /**< Address for host IPC parameters */
137 } __rte_packed ipc_ch_t;
139 typedef struct ipc_instance {
140 uint32_t instance_id; /**< instance id, use to init this
141 * instance by ipc_init API
143 uint32_t initialized; /**< Set in ipc_init */
144 ipc_ch_t ch_list[IPC_MAX_CHANNEL_COUNT];
145 /**< Channel descriptors in this instance */
146 } __rte_packed ipc_instance_t;
148 typedef struct ipc_metadata {
149 uint32_t ipc_host_signature; /**< IPC host signature, Set by host/L2 */
150 uint32_t ipc_geul_signature; /**< IPC geul signature, Set by modem */
151 ipc_instance_t instance_list[IPC_MAX_INSTANCE_COUNT];
152 } __rte_packed ipc_metadata_t;
154 typedef struct ipc_channel_us_priv {
157 /* In flight packets status for buffer list. */
158 uint8_t bufs_inflight[IPC_MAX_DEPTH];
168 mem_strt_addr_t modem_ccsrbar;
169 mem_strt_addr_t peb_start; /* PEB meta data */
170 mem_strt_addr_t mhif_start; /* MHIF meta daat */
171 mem_strt_addr_t hugepg_start; /* Modem to access hugepage */
174 typedef struct ipc_priv_t {
179 mem_range_t modem_ccsrbar;
180 mem_range_t peb_start;
181 mem_range_t mhif_start;
182 mem_range_t hugepg_start;
183 ipc_channel_us_t *channels[IPC_MAX_CHANNEL_COUNT];
184 ipc_instance_t *instance;
185 ipc_instance_t *instance_bk;
188 /** Structure specifying enqueue operation (enqueue at LA1224) */
189 struct bbdev_ipc_enqueue_op {
190 /** Status of operation that was performed */
192 /** CRC Status of SD operation that was performed */
193 int32_t crc_stat_addr;
194 /** HARQ Output buffer memory length for Shared Decode.
198 /** Reserved (for 8 byte alignment) */
202 /** Structure specifying dequeue operation (dequeue at LA1224) */
203 struct bbdev_ipc_dequeue_op {
204 /** Input buffer memory address */
206 /** Input buffer memory length */
208 /** Output buffer memory address */
210 /** Output buffer memory length */
212 /* Number of code blocks. Only set when HARQ is used */
213 uint32_t num_code_blocks;
214 /** Dequeue Operation flags */
216 /** Shared metadata between L1 and L2 */
217 uint32_t shared_metadata;
220 /* This shared memory would be on the host side which have copy of some
221 * of the parameters which are also part of Shared BD ring. Read access
222 * of these parameters from the host side would not be over PCI.
224 typedef struct host_ipc_params {
225 volatile uint32_t pi;
226 volatile uint32_t ci;
227 volatile uint32_t bd_m_modem_ptr[IPC_MAX_DEPTH];
228 } __rte_packed host_ipc_params_t;
230 struct hif_ipc_regs {
231 uint32_t ipc_mdata_offset;
232 uint32_t ipc_mdata_size;
239 volatile uint32_t host_ready;
240 volatile uint32_t mod_ready;
241 struct hif_ipc_regs ipc_regs;