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41 #include "qman_priv.h"
43 /***************************/
44 /* Portal register assists */
45 /***************************/
46 #define QM_REG_EQCR_PI_CINH 0x3000
47 #define QM_REG_EQCR_CI_CINH 0x3040
48 #define QM_REG_EQCR_ITR 0x3080
49 #define QM_REG_DQRR_PI_CINH 0x3100
50 #define QM_REG_DQRR_CI_CINH 0x3140
51 #define QM_REG_DQRR_ITR 0x3180
52 #define QM_REG_DQRR_DCAP 0x31C0
53 #define QM_REG_DQRR_SDQCR 0x3200
54 #define QM_REG_DQRR_VDQCR 0x3240
55 #define QM_REG_DQRR_PDQCR 0x3280
56 #define QM_REG_MR_PI_CINH 0x3300
57 #define QM_REG_MR_CI_CINH 0x3340
58 #define QM_REG_MR_ITR 0x3380
59 #define QM_REG_CFG 0x3500
60 #define QM_REG_ISR 0x3600
61 #define QM_REG_IIR 0x36C0
62 #define QM_REG_ITPR 0x3740
64 /* Cache-enabled register offsets */
65 #define QM_CL_EQCR 0x0000
66 #define QM_CL_DQRR 0x1000
67 #define QM_CL_MR 0x2000
68 #define QM_CL_EQCR_PI_CENA 0x3000
69 #define QM_CL_EQCR_CI_CENA 0x3040
70 #define QM_CL_DQRR_PI_CENA 0x3100
71 #define QM_CL_DQRR_CI_CENA 0x3140
72 #define QM_CL_MR_PI_CENA 0x3300
73 #define QM_CL_MR_CI_CENA 0x3340
74 #define QM_CL_CR 0x3800
75 #define QM_CL_RR0 0x3900
76 #define QM_CL_RR1 0x3940
78 /* BTW, the drivers (and h/w programming model) already obtain the required
79 * synchronisation for portal accesses via lwsync(), hwsync(), and
80 * data-dependencies. Use of barrier()s or other order-preserving primitives
81 * simply degrade performance. Hence the use of the __raw_*() interfaces, which
82 * simply ensure that the compiler treats the portal registers as volatile (ie.
86 /* Cache-inhibited register access. */
87 #define __qm_in(qm, o) be32_to_cpu(__raw_readl((qm)->ci + (o)))
88 #define __qm_out(qm, o, val) __raw_writel((cpu_to_be32(val)), \
90 #define qm_in(reg) __qm_in(&portal->addr, QM_REG_##reg)
91 #define qm_out(reg, val) __qm_out(&portal->addr, QM_REG_##reg, val)
93 /* Cache-enabled (index) register access */
94 #define __qm_cl_touch_ro(qm, o) dcbt_ro((qm)->ce + (o))
95 #define __qm_cl_touch_rw(qm, o) dcbt_rw((qm)->ce + (o))
96 #define __qm_cl_in(qm, o) be32_to_cpu(__raw_readl((qm)->ce + (o)))
97 #define __qm_cl_out(qm, o, val) \
99 u32 *__tmpclout = (qm)->ce + (o); \
100 __raw_writel(cpu_to_be32(val), __tmpclout); \
103 #define __qm_cl_invalidate(qm, o) dccivac((qm)->ce + (o))
104 #define qm_cl_touch_ro(reg) __qm_cl_touch_ro(&portal->addr, QM_CL_##reg##_CENA)
105 #define qm_cl_touch_rw(reg) __qm_cl_touch_rw(&portal->addr, QM_CL_##reg##_CENA)
106 #define qm_cl_in(reg) __qm_cl_in(&portal->addr, QM_CL_##reg##_CENA)
107 #define qm_cl_out(reg, val) __qm_cl_out(&portal->addr, QM_CL_##reg##_CENA, val)
108 #define qm_cl_invalidate(reg)\
109 __qm_cl_invalidate(&portal->addr, QM_CL_##reg##_CENA)
111 /* Cache-enabled ring access */
112 #define qm_cl(base, idx) ((void *)base + ((idx) << 6))
114 /* Cyclic helper for rings. FIXME: once we are able to do fine-grain perf
115 * analysis, look at using the "extra" bit in the ring index registers to avoid
118 static inline u8 qm_cyc_diff(u8 ringsize, u8 first, u8 last)
120 /* 'first' is included, 'last' is excluded */
123 return ringsize + last - first;
128 * pmode == production mode
129 * cmode == consumption mode,
130 * dmode == h/w dequeue mode.
131 * Enum values use 3 letter codes. First letter matches the portal mode,
132 * remaining two letters indicate;
133 * ci == cache-inhibited portal register
134 * ce == cache-enabled portal register
135 * vb == in-band valid-bit (cache-enabled)
136 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
137 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
139 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
140 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
141 qm_eqcr_pce = 1, /* PI index, cache-enabled */
142 qm_eqcr_pvb = 2 /* valid-bit */
145 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
146 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
147 qm_dqrr_dpull = 1 /* PDQCR */
150 enum qm_dqrr_pmode { /* s/w-only */
151 qm_dqrr_pci, /* reads DQRR_PI_CINH */
152 qm_dqrr_pce, /* reads DQRR_PI_CENA */
153 qm_dqrr_pvb /* reads valid-bit */
156 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
157 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
158 qm_dqrr_cce = 1, /* CI index, cache-enabled */
159 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
162 enum qm_mr_pmode { /* s/w-only */
163 qm_mr_pci, /* reads MR_PI_CINH */
164 qm_mr_pce, /* reads MR_PI_CENA */
165 qm_mr_pvb /* reads valid-bit */
168 enum qm_mr_cmode { /* matches QCSP_CFG::MM */
169 qm_mr_cci = 0, /* CI index, cache-inhibited */
170 qm_mr_cce = 1 /* CI index, cache-enabled */
173 /* ------------------------- */
174 /* --- Portal structures --- */
176 #define QM_EQCR_SIZE 8
177 #define QM_DQRR_SIZE 16
181 struct qm_eqcr_entry *ring, *cursor;
182 u8 ci, available, ithresh, vbit;
183 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
185 enum qm_eqcr_pmode pmode;
190 const struct qm_dqrr_entry *ring, *cursor;
191 u8 pi, ci, fill, ithresh, vbit;
192 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
193 enum qm_dqrr_dmode dmode;
194 enum qm_dqrr_pmode pmode;
195 enum qm_dqrr_cmode cmode;
200 const struct qm_mr_entry *ring, *cursor;
201 u8 pi, ci, fill, ithresh, vbit;
202 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
203 enum qm_mr_pmode pmode;
204 enum qm_mr_cmode cmode;
209 struct qm_mc_command *cr;
210 struct qm_mc_result *rr;
212 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
214 /* Can be _mc_start()ed */
216 /* Can be _mc_commit()ed or _mc_abort()ed */
218 /* Can only be _mc_retry()ed */
224 #define QM_PORTAL_ALIGNMENT ____cacheline_aligned
227 void __iomem *ce; /* cache-enabled */
228 void __iomem *ci; /* cache-inhibited */
237 } QM_PORTAL_ALIGNMENT;
239 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
240 #define EQCR_CARRYCLEAR(p) \
241 (void *)((unsigned long)(p) & (~(unsigned long)(QM_EQCR_SIZE << 6)))
243 extern dma_addr_t rte_mem_virt2phy(const void *addr);
245 /* Bit-wise logic to convert a ring pointer to a ring index */
246 static inline u8 EQCR_PTR2IDX(struct qm_eqcr_entry *e)
248 return ((uintptr_t)e >> 6) & (QM_EQCR_SIZE - 1);
251 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */
252 static inline void EQCR_INC(struct qm_eqcr *eqcr)
254 /* NB: this is odd-looking, but experiments show that it generates fast
255 * code with essentially no branching overheads. We increment to the
256 * next EQCR pointer and handle overflow and 'vbit'.
258 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
260 eqcr->cursor = EQCR_CARRYCLEAR(partial);
261 if (partial != eqcr->cursor)
262 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
265 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
268 register struct qm_eqcr *eqcr = &portal->eqcr;
270 DPAA_ASSERT(!eqcr->busy);
271 if (!eqcr->available)
274 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
281 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
284 register struct qm_eqcr *eqcr = &portal->eqcr;
287 DPAA_ASSERT(!eqcr->busy);
288 if (!eqcr->available) {
290 eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
291 diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
292 eqcr->available += diff;
296 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
302 static inline void qm_eqcr_abort(struct qm_portal *portal)
304 __maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
306 DPAA_ASSERT(eqcr->busy);
307 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
312 static inline struct qm_eqcr_entry *qm_eqcr_pend_and_next(
313 struct qm_portal *portal, u8 myverb)
315 register struct qm_eqcr *eqcr = &portal->eqcr;
317 DPAA_ASSERT(eqcr->busy);
318 DPAA_ASSERT(eqcr->pmode != qm_eqcr_pvb);
319 if (eqcr->available == 1)
321 eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
328 #define EQCR_COMMIT_CHECKS(eqcr) \
330 DPAA_ASSERT(eqcr->busy); \
331 DPAA_ASSERT(eqcr->cursor->orp == (eqcr->cursor->orp & 0x00ffffff)); \
332 DPAA_ASSERT(eqcr->cursor->fqid == (eqcr->cursor->fqid & 0x00ffffff)); \
335 static inline void qm_eqcr_pci_commit(struct qm_portal *portal, u8 myverb)
337 register struct qm_eqcr *eqcr = &portal->eqcr;
339 EQCR_COMMIT_CHECKS(eqcr);
340 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pci);
341 eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
346 qm_out(EQCR_PI_CINH, EQCR_PTR2IDX(eqcr->cursor));
347 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
352 static inline void qm_eqcr_pce_prefetch(struct qm_portal *portal)
354 __maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
356 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pce);
357 qm_cl_invalidate(EQCR_PI);
358 qm_cl_touch_rw(EQCR_PI);
361 static inline void qm_eqcr_pce_commit(struct qm_portal *portal, u8 myverb)
363 register struct qm_eqcr *eqcr = &portal->eqcr;
365 EQCR_COMMIT_CHECKS(eqcr);
366 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pce);
367 eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
372 qm_cl_out(EQCR_PI, EQCR_PTR2IDX(eqcr->cursor));
373 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
378 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
380 register struct qm_eqcr *eqcr = &portal->eqcr;
381 struct qm_eqcr_entry *eqcursor;
383 EQCR_COMMIT_CHECKS(eqcr);
384 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
386 eqcursor = eqcr->cursor;
387 eqcursor->__dont_write_directly__verb = myverb | eqcr->vbit;
391 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
396 static inline u8 qm_eqcr_cci_update(struct qm_portal *portal)
398 register struct qm_eqcr *eqcr = &portal->eqcr;
399 u8 diff, old_ci = eqcr->ci;
401 eqcr->ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
402 diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
403 eqcr->available += diff;
407 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
409 __maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
411 qm_cl_touch_ro(EQCR_CI);
414 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
416 register struct qm_eqcr *eqcr = &portal->eqcr;
417 u8 diff, old_ci = eqcr->ci;
419 eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
420 qm_cl_invalidate(EQCR_CI);
421 diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
422 eqcr->available += diff;
426 static inline u8 qm_eqcr_get_ithresh(struct qm_portal *portal)
428 register struct qm_eqcr *eqcr = &portal->eqcr;
430 return eqcr->ithresh;
433 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
435 register struct qm_eqcr *eqcr = &portal->eqcr;
437 eqcr->ithresh = ithresh;
438 qm_out(EQCR_ITR, ithresh);
441 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
443 register struct qm_eqcr *eqcr = &portal->eqcr;
445 return eqcr->available;
448 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
450 register struct qm_eqcr *eqcr = &portal->eqcr;
452 return QM_EQCR_SIZE - 1 - eqcr->available;
455 #define DQRR_CARRYCLEAR(p) \
456 (void *)((unsigned long)(p) & (~(unsigned long)(QM_DQRR_SIZE << 6)))
458 static inline u8 DQRR_PTR2IDX(const struct qm_dqrr_entry *e)
460 return ((uintptr_t)e >> 6) & (QM_DQRR_SIZE - 1);
463 static inline const struct qm_dqrr_entry *DQRR_INC(
464 const struct qm_dqrr_entry *e)
466 return DQRR_CARRYCLEAR(e + 1);
469 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
471 qm_out(CFG, (qm_in(CFG) & 0xff0fffff) |
472 ((mf & (QM_DQRR_SIZE - 1)) << 20));
475 static inline const struct qm_dqrr_entry *qm_dqrr_current(
476 struct qm_portal *portal)
478 register struct qm_dqrr *dqrr = &portal->dqrr;
485 static inline u8 qm_dqrr_cursor(struct qm_portal *portal)
487 register struct qm_dqrr *dqrr = &portal->dqrr;
489 return DQRR_PTR2IDX(dqrr->cursor);
492 static inline u8 qm_dqrr_next(struct qm_portal *portal)
494 register struct qm_dqrr *dqrr = &portal->dqrr;
496 DPAA_ASSERT(dqrr->fill);
497 dqrr->cursor = DQRR_INC(dqrr->cursor);
501 static inline u8 qm_dqrr_pci_update(struct qm_portal *portal)
503 register struct qm_dqrr *dqrr = &portal->dqrr;
504 u8 diff, old_pi = dqrr->pi;
506 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pci);
507 dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
508 diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi);
513 static inline void qm_dqrr_pce_prefetch(struct qm_portal *portal)
515 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
517 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pce);
518 qm_cl_invalidate(DQRR_PI);
519 qm_cl_touch_ro(DQRR_PI);
522 static inline u8 qm_dqrr_pce_update(struct qm_portal *portal)
524 register struct qm_dqrr *dqrr = &portal->dqrr;
525 u8 diff, old_pi = dqrr->pi;
527 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pce);
528 dqrr->pi = qm_cl_in(DQRR_PI) & (QM_DQRR_SIZE - 1);
529 diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi);
534 static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
536 register struct qm_dqrr *dqrr = &portal->dqrr;
537 const struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
539 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
540 /* when accessing 'verb', use __raw_readb() to ensure that compiler
541 * inlining doesn't try to optimise out "excess reads".
543 if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
544 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
546 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
551 static inline void qm_dqrr_cci_consume(struct qm_portal *portal, u8 num)
553 register struct qm_dqrr *dqrr = &portal->dqrr;
555 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cci);
556 dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1);
557 qm_out(DQRR_CI_CINH, dqrr->ci);
560 static inline void qm_dqrr_cci_consume_to_current(struct qm_portal *portal)
562 register struct qm_dqrr *dqrr = &portal->dqrr;
564 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cci);
565 dqrr->ci = DQRR_PTR2IDX(dqrr->cursor);
566 qm_out(DQRR_CI_CINH, dqrr->ci);
569 static inline void qm_dqrr_cce_prefetch(struct qm_portal *portal)
571 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
573 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
574 qm_cl_invalidate(DQRR_CI);
575 qm_cl_touch_rw(DQRR_CI);
578 static inline void qm_dqrr_cce_consume(struct qm_portal *portal, u8 num)
580 register struct qm_dqrr *dqrr = &portal->dqrr;
582 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
583 dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1);
584 qm_cl_out(DQRR_CI, dqrr->ci);
587 static inline void qm_dqrr_cce_consume_to_current(struct qm_portal *portal)
589 register struct qm_dqrr *dqrr = &portal->dqrr;
591 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
592 dqrr->ci = DQRR_PTR2IDX(dqrr->cursor);
593 qm_cl_out(DQRR_CI, dqrr->ci);
596 static inline void qm_dqrr_cdc_consume_1(struct qm_portal *portal, u8 idx,
599 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
601 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
602 DPAA_ASSERT(idx < QM_DQRR_SIZE);
603 qm_out(DQRR_DCAP, (0 << 8) | /* S */
604 ((park ? 1 : 0) << 6) | /* PK */
608 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
609 const struct qm_dqrr_entry *dq,
612 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
613 u8 idx = DQRR_PTR2IDX(dq);
615 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
616 DPAA_ASSERT(idx < QM_DQRR_SIZE);
617 qm_out(DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
618 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
619 idx); /* DQRR_DCAP::DCAP_CI */
622 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u16 bitmask)
624 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
626 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
627 qm_out(DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
628 ((u32)bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
629 dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
630 dqrr->fill = qm_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
633 static inline u8 qm_dqrr_cdc_cci(struct qm_portal *portal)
635 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
637 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
638 return qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
641 static inline void qm_dqrr_cdc_cce_prefetch(struct qm_portal *portal)
643 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
645 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
646 qm_cl_invalidate(DQRR_CI);
647 qm_cl_touch_ro(DQRR_CI);
650 static inline u8 qm_dqrr_cdc_cce(struct qm_portal *portal)
652 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
654 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
655 return qm_cl_in(DQRR_CI) & (QM_DQRR_SIZE - 1);
658 static inline u8 qm_dqrr_get_ci(struct qm_portal *portal)
660 register struct qm_dqrr *dqrr = &portal->dqrr;
662 DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
666 static inline void qm_dqrr_park(struct qm_portal *portal, u8 idx)
668 __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
670 DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
671 qm_out(DQRR_DCAP, (0 << 8) | /* S */
673 (idx & (QM_DQRR_SIZE - 1))); /* DCAP_CI */
676 static inline void qm_dqrr_park_current(struct qm_portal *portal)
678 register struct qm_dqrr *dqrr = &portal->dqrr;
680 DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
681 qm_out(DQRR_DCAP, (0 << 8) | /* S */
683 DQRR_PTR2IDX(dqrr->cursor)); /* DCAP_CI */
686 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
688 qm_out(DQRR_SDQCR, sdqcr);
691 static inline u32 qm_dqrr_sdqcr_get(struct qm_portal *portal)
693 return qm_in(DQRR_SDQCR);
696 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
698 qm_out(DQRR_VDQCR, vdqcr);
701 static inline u32 qm_dqrr_vdqcr_get(struct qm_portal *portal)
703 return qm_in(DQRR_VDQCR);
706 static inline u8 qm_dqrr_get_ithresh(struct qm_portal *portal)
708 register struct qm_dqrr *dqrr = &portal->dqrr;
710 return dqrr->ithresh;
713 static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
715 qm_out(DQRR_ITR, ithresh);
718 static inline u8 qm_dqrr_get_maxfill(struct qm_portal *portal)
720 return (qm_in(CFG) & 0x00f00000) >> 20;
726 #define MR_CARRYCLEAR(p) \
727 (void *)((unsigned long)(p) & (~(unsigned long)(QM_MR_SIZE << 6)))
729 static inline u8 MR_PTR2IDX(const struct qm_mr_entry *e)
731 return ((uintptr_t)e >> 6) & (QM_MR_SIZE - 1);
734 static inline const struct qm_mr_entry *MR_INC(const struct qm_mr_entry *e)
736 return MR_CARRYCLEAR(e + 1);
739 static inline void qm_mr_finish(struct qm_portal *portal)
741 register struct qm_mr *mr = &portal->mr;
743 if (mr->ci != MR_PTR2IDX(mr->cursor))
744 pr_crit("Ignoring completed MR entries\n");
747 static inline const struct qm_mr_entry *qm_mr_current(struct qm_portal *portal)
749 register struct qm_mr *mr = &portal->mr;
756 static inline u8 qm_mr_next(struct qm_portal *portal)
758 register struct qm_mr *mr = &portal->mr;
760 DPAA_ASSERT(mr->fill);
761 mr->cursor = MR_INC(mr->cursor);
765 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
767 register struct qm_mr *mr = &portal->mr;
769 DPAA_ASSERT(mr->cmode == qm_mr_cci);
770 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
771 qm_out(MR_CI_CINH, mr->ci);
774 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
776 register struct qm_mr *mr = &portal->mr;
778 DPAA_ASSERT(mr->cmode == qm_mr_cci);
779 mr->ci = MR_PTR2IDX(mr->cursor);
780 qm_out(MR_CI_CINH, mr->ci);
783 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
785 qm_out(MR_ITR, ithresh);
788 /* ------------------------------ */
789 /* --- Management command API --- */
790 static inline int qm_mc_init(struct qm_portal *portal)
792 register struct qm_mc *mc = &portal->mc;
794 mc->cr = portal->addr.ce + QM_CL_CR;
795 mc->rr = portal->addr.ce + QM_CL_RR0;
796 mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) &
797 QM_MCC_VERB_VBIT) ? 0 : 1;
798 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
799 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
800 mc->state = qman_mc_idle;
805 static inline void qm_mc_finish(struct qm_portal *portal)
807 __maybe_unused register struct qm_mc *mc = &portal->mc;
809 DPAA_ASSERT(mc->state == qman_mc_idle);
810 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
811 if (mc->state != qman_mc_idle)
812 pr_crit("Losing incomplete MC command\n");
816 static inline struct qm_mc_command *qm_mc_start(struct qm_portal *portal)
818 register struct qm_mc *mc = &portal->mc;
820 DPAA_ASSERT(mc->state == qman_mc_idle);
821 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
822 mc->state = qman_mc_user;
828 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
830 register struct qm_mc *mc = &portal->mc;
831 struct qm_mc_result *rr = mc->rr + mc->rridx;
833 DPAA_ASSERT(mc->state == qman_mc_user);
835 mc->cr->__dont_write_directly__verb = myverb | mc->vbit;
838 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
839 mc->state = qman_mc_hw;
843 static inline struct qm_mc_result *qm_mc_result(struct qm_portal *portal)
845 register struct qm_mc *mc = &portal->mc;
846 struct qm_mc_result *rr = mc->rr + mc->rridx;
848 DPAA_ASSERT(mc->state == qman_mc_hw);
849 /* The inactive response register's verb byte always returns zero until
850 * its command is submitted and completed. This includes the valid-bit,
851 * in case you were wondering.
853 if (!__raw_readb(&rr->verb)) {
858 mc->vbit ^= QM_MCC_VERB_VBIT;
859 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
860 mc->state = qman_mc_idle;
865 /* Portal interrupt register API */
866 static inline void qm_isr_set_iperiod(struct qm_portal *portal, u16 iperiod)
868 qm_out(ITPR, iperiod);
871 static inline u32 __qm_isr_read(struct qm_portal *portal, enum qm_isr_reg n)
873 #if defined(RTE_ARCH_ARM64)
874 return __qm_in(&portal->addr, QM_REG_ISR + (n << 6));
876 return __qm_in(&portal->addr, QM_REG_ISR + (n << 2));
880 static inline void __qm_isr_write(struct qm_portal *portal, enum qm_isr_reg n,
883 #if defined(RTE_ARCH_ARM64)
884 __qm_out(&portal->addr, QM_REG_ISR + (n << 6), val);
886 __qm_out(&portal->addr, QM_REG_ISR + (n << 2), val);