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47 /* Congestion Groups */
49 * This wrapper represents a bit-array for the state of the 256 QMan congestion
50 * groups. Is also used as a *mask* for congestion groups, eg. so we ignore
51 * those that don't concern us. We harness the structure and accessor details
52 * already used in the management command to query congestion groups.
55 struct __qm_mcr_querycongestion q;
58 static inline void qman_cgrs_init(struct qman_cgrs *c)
60 memset(c, 0, sizeof(*c));
63 static inline void qman_cgrs_fill(struct qman_cgrs *c)
65 memset(c, 0xff, sizeof(*c));
68 static inline int qman_cgrs_get(struct qman_cgrs *c, int num)
70 return QM_MCR_QUERYCONGESTION(&c->q, num);
73 static inline void qman_cgrs_set(struct qman_cgrs *c, int num)
75 c->q.state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num));
78 static inline void qman_cgrs_unset(struct qman_cgrs *c, int num)
80 c->q.state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num));
83 static inline int qman_cgrs_next(struct qman_cgrs *c, int num)
85 while ((++num < (int)__CGR_NUM) && !qman_cgrs_get(c, num))
90 static inline void qman_cgrs_cp(struct qman_cgrs *dest,
91 const struct qman_cgrs *src)
93 memcpy(dest, src, sizeof(*dest));
96 static inline void qman_cgrs_and(struct qman_cgrs *dest,
97 const struct qman_cgrs *a,
98 const struct qman_cgrs *b)
101 u32 *_d = dest->q.state;
102 const u32 *_a = a->q.state;
103 const u32 *_b = b->q.state;
105 for (ret = 0; ret < 8; ret++)
106 *(_d++) = *(_a++) & *(_b++);
109 static inline void qman_cgrs_xor(struct qman_cgrs *dest,
110 const struct qman_cgrs *a,
111 const struct qman_cgrs *b)
114 u32 *_d = dest->q.state;
115 const u32 *_a = a->q.state;
116 const u32 *_b = b->q.state;
118 for (ret = 0; ret < 8; ret++)
119 *(_d++) = *(_a++) ^ *(_b++);
122 /* used by CCSR and portal interrupt code */
130 struct qm_portal_config {
132 * Corenet portal addresses;
133 * [0]==cache-enabled, [1]==cache-inhibited.
135 void __iomem *addr_virt[2];
136 struct device_node *node;
137 /* Allow these to be joined in lists */
138 struct list_head list;
139 /* User-visible portal configuration settings */
140 /* If the caller enables DQRR stashing (and thus wishes to operate the
141 * portal from only one cpu), this is the logical CPU that the portal
142 * will stash to. Whether stashing is enabled or not, this setting is
143 * also used for any "core-affine" portals, ie. default portals
144 * associated to the corresponding cpu. -1 implies that there is no
145 * core affinity configured.
148 /* portal interrupt line */
150 /* the unique index of this portal */
152 /* Is this portal shared? (If so, it has coarser locking and demuxes
153 * processing on behalf of other CPUs.).
156 /* The portal's dedicated channel id, use this value for initialising
157 * frame queues to target this portal when scheduled.
160 /* A mask of which pool channels this portal has dequeue access to
161 * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask).
167 /* Revision info (for errata and feature handling) */
168 #define QMAN_REV11 0x0101
169 #define QMAN_REV12 0x0102
170 #define QMAN_REV20 0x0200
171 #define QMAN_REV30 0x0300
172 #define QMAN_REV31 0x0301
173 #define QMAN_REV32 0x0302
174 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
177 int qm_set_wpm(int wpm);
178 int qm_get_wpm(int *wpm);
180 struct qman_portal *qman_create_affine_portal(
181 const struct qm_portal_config *config,
182 const struct qman_cgrs *cgrs);
183 const struct qm_portal_config *qman_destroy_affine_portal(void);
185 struct qm_portal_config *qm_get_unused_portal(void);
186 struct qm_portal_config *qm_get_unused_portal_idx(uint32_t idx);
188 void qm_put_unused_portal(struct qm_portal_config *pcfg);
189 void qm_set_liodns(struct qm_portal_config *pcfg);
191 /* This CGR feature is supported by h/w and required by unit-tests and the
192 * debugfs hooks, so is implemented in the driver. However it allows an explicit
193 * corruption of h/w fields by s/w that are usually incorruptible (because the
194 * counters are usually maintained entirely within h/w). As such, we declare
195 * this API internally.
197 int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
198 struct qm_mcr_cgrtestwrite *result);
200 /* QMan s/w corenet portal, low-level i/face */
203 * For Choose one SOURCE. Choose one COUNT. Choose one
204 * dequeue TYPE. Choose TOKEN (8-bit).
205 * If SOURCE == CHANNELS,
206 * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n).
207 * You can choose DEDICATED_PRECEDENCE if the portal channel should have
209 * If SOURCE == SPECIFICWQ,
210 * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
211 * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
212 * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
215 #define QM_SDQCR_SOURCE_CHANNELS 0x0
216 #define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
217 #define QM_SDQCR_COUNT_EXACT1 0x0
218 #define QM_SDQCR_COUNT_UPTO3 0x20000000
219 #define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
220 #define QM_SDQCR_TYPE_MASK 0x03000000
221 #define QM_SDQCR_TYPE_NULL 0x0
222 #define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
223 #define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
224 #define QM_SDQCR_TYPE_ACTIVE 0x03000000
225 #define QM_SDQCR_TOKEN_MASK 0x00ff0000
226 #define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
227 #define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
228 #define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
229 #define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
230 #define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
231 #define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
232 #define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
234 #define QM_VDQCR_FQID_MASK 0x00ffffff
235 #define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
237 #define QM_EQCR_VERB_VBIT 0x80
238 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
239 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01
240 #define QM_EQCR_VERB_COLOUR_MASK 0x18 /* 4 possible values; */
241 #define QM_EQCR_VERB_COLOUR_GREEN 0x00
242 #define QM_EQCR_VERB_COLOUR_YELLOW 0x08
243 #define QM_EQCR_VERB_COLOUR_RED 0x10
244 #define QM_EQCR_VERB_COLOUR_OVERRIDE 0x18
245 #define QM_EQCR_VERB_INTERRUPT 0x04 /* on command consumption */
246 #define QM_EQCR_VERB_ORP 0x02 /* enable order restoration */
247 #define QM_EQCR_DCA_ENABLE 0x80
248 #define QM_EQCR_DCA_PARK 0x40
249 #define QM_EQCR_DCA_IDXMASK 0x0f /* "DQRR::idx" goes here */
250 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
251 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
252 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
253 #define QM_EQCR_FQID_NULL 0 /* eg. for an ORP seqnum hole */
255 #define QM_MCC_VERB_VBIT 0x80
256 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
257 #define QM_MCC_VERB_INITFQ_PARKED 0x40
258 #define QM_MCC_VERB_INITFQ_SCHED 0x41
259 #define QM_MCC_VERB_QUERYFQ 0x44
260 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
261 #define QM_MCC_VERB_QUERYWQ 0x46
262 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
263 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
264 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
265 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
266 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
267 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
268 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
269 #define QM_MCC_VERB_INITCGR 0x50
270 #define QM_MCC_VERB_MODIFYCGR 0x51
271 #define QM_MCC_VERB_CGRTESTWRITE 0x52
272 #define QM_MCC_VERB_QUERYCGR 0x58
273 #define QM_MCC_VERB_QUERYCONGESTION 0x59
276 * Used by all portal interrupt registers except 'inhibit'
277 * Channels with frame availability
279 #define QM_PIRQ_DQAVAIL 0x0000ffff
281 /* The DQAVAIL interrupt fields break down into these bits; */
282 #define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */
283 #define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */
284 #define QM_DQAVAIL_MASK 0xffff
285 /* This mask contains all the "irqsource" bits visible to API users */
286 #define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
288 /* These are qm_<reg>_<verb>(). So for example, qm_disable_write() means "write
289 * the disable register" rather than "disable the ability to write".
291 #define qm_isr_status_read(qm) __qm_isr_read(qm, qm_isr_status)
292 #define qm_isr_status_clear(qm, m) __qm_isr_write(qm, qm_isr_status, m)
293 #define qm_isr_enable_read(qm) __qm_isr_read(qm, qm_isr_enable)
294 #define qm_isr_enable_write(qm, v) __qm_isr_write(qm, qm_isr_enable, v)
295 #define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable)
296 #define qm_isr_disable_write(qm, v) __qm_isr_write(qm, qm_isr_disable, v)
297 /* TODO: unfortunate name-clash here, reword? */
298 #define qm_isr_inhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 1)
299 #define qm_isr_uninhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 0)
301 #define QMAN_PORTAL_IRQ_PATH "/dev/fsl-usdpaa-irq"
303 #endif /* _QMAN_PRIV_H */